Additional risk level support - (step 1) Backward compatibility

The purpose of this commit is to avoid a coreq situation by
ensuring this commit is fully propagated through our repos and
test drivers before introducing the change to the new HW image
with two RLs.

The commit enables simultaneous support for producing a HW image
and retrieving rings from an image that has either one or two risk
level (RL) rings in the .rings section. The commit however does
NOT actually, yet, make any changes to the image which is the
aim of the (step 2) commit 53292. Nor does this commit generate
any raw ring files or process any RL2 level rings yet. Again this
will happen in 53292.

The commit also includes,
- various related cleanups in data naming and ring file processing,
- some data and invironment specific parts in ring_apply.C have
  been moved to common_ringId.C.

Key_Cronus_Test=XIP_REGRESS

HW-Image-Prereq=53292
- This commit (52659) must be fully merged before merging 53292.

Change-Id: I6f0b9614f7f7fa8f79f6d180f10d260f99d52562
Original-Change-Id: I402d53c4a3ca6a084c958321069cc6f60e04ad24
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52659
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

2 files changed, 4 insertions, 4 deletions

diff --git a/import/chips/centaur/utils/imageProcs/cen_ringId.C b/import/chips/centaur/utils/imageProcs/cen_ringId.C
index 3e721c44..07182f97 100644
--- a/import/chips/centaur/utils/imageProcs/cen_ringId.C
+++ b/import/chips/centaur/utils/imageProcs/cen_ringId.C
@@ -145,7 +145,7 @@ const GenRingIdList RING_ID_LIST_COMMON[] =
     {"tp_pll_bndy_bucket_8", 0x6a, 0x01, 0x01, CEN_RING, 0x01030088},
 };
 
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 
 }; // namespace CEN
 
@@ -160,14 +160,14 @@ ChipletType_t CEN_RID::ringid_get_chiplet(RingId_t i_ringId)
 }
 
 void CEN_RID::ringid_get_chiplet_properties(
-    ChipletType_t      i_chiplet,
+    ChipletType_t      i_chipletType,
     ChipletData_t**    o_cpltData,
     GenRingIdList**    o_ringComm,
     GenRingIdList**    o_ringInst,
     RingVariantOrder** o_varOrder,
     uint8_t*           o_varNumb)
 {
-    switch (i_chiplet)
+    switch (i_chipletType)
     {
         case CEN_TYPE :
             *o_cpltData = (ChipletData_t*)   &CEN::g_chipletData;
diff --git a/import/chips/centaur/utils/imageProcs/cen_ringId.H b/import/chips/centaur/utils/imageProcs/cen_ringId.H
index 9d0bc609..9af2e9e0 100644
--- a/import/chips/centaur/utils/imageProcs/cen_ringId.H
+++ b/import/chips/centaur/utils/imageProcs/cen_ringId.H
@@ -406,7 +406,7 @@ ringid_get_chiplet(RingId_t i_ringId);
 // as determined by ringId
 void
 ringid_get_chiplet_properties(
-    ChipletType_t      i_chiplet,
+    ChipletType_t      i_chipletType,
     ChipletData_t**    o_cpltData,
     GenRingIdList**    o_ringComm,
     GenRingIdList**    o_ringInst,