Additional risk level support - (step 1) Backward compatibility

The purpose of this commit is to avoid a coreq situation by
ensuring this commit is fully propagated through our repos and
test drivers before introducing the change to the new HW image
with two RLs.

The commit enables simultaneous support for producing a HW image
and retrieving rings from an image that has either one or two risk
level (RL) rings in the .rings section. The commit however does
NOT actually, yet, make any changes to the image which is the
aim of the (step 2) commit 53292. Nor does this commit generate
any raw ring files or process any RL2 level rings yet. Again this
will happen in 53292.

The commit also includes,
- various related cleanups in data naming and ring file processing,
- some data and invironment specific parts in ring_apply.C have
  been moved to common_ringId.C.

Key_Cronus_Test=XIP_REGRESS

HW-Image-Prereq=53292
- This commit (52659) must be fully merged before merging 53292.

Change-Id: I6f0b9614f7f7fa8f79f6d180f10d260f99d52562
Original-Change-Id: I402d53c4a3ca6a084c958321069cc6f60e04ad24
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52659
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

5 files changed, 250 insertions, 30 deletions

diff --git a/import/chips/centaur/utils/imageProcs/cen_ringId.C b/import/chips/centaur/utils/imageProcs/cen_ringId.C
index 3e721c44..07182f97 100644
--- a/import/chips/centaur/utils/imageProcs/cen_ringId.C
+++ b/import/chips/centaur/utils/imageProcs/cen_ringId.C
@@ -145,7 +145,7 @@ const GenRingIdList RING_ID_LIST_COMMON[] =
     {"tp_pll_bndy_bucket_8", 0x6a, 0x01, 0x01, CEN_RING, 0x01030088},
 };
 
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 
 }; // namespace CEN
 
@@ -160,14 +160,14 @@ ChipletType_t CEN_RID::ringid_get_chiplet(RingId_t i_ringId)
 }
 
 void CEN_RID::ringid_get_chiplet_properties(
-    ChipletType_t      i_chiplet,
+    ChipletType_t      i_chipletType,
     ChipletData_t**    o_cpltData,
     GenRingIdList**    o_ringComm,
     GenRingIdList**    o_ringInst,
     RingVariantOrder** o_varOrder,
     uint8_t*           o_varNumb)
 {
-    switch (i_chiplet)
+    switch (i_chipletType)
     {
         case CEN_TYPE :
             *o_cpltData = (ChipletData_t*)   &CEN::g_chipletData;
diff --git a/import/chips/centaur/utils/imageProcs/cen_ringId.H b/import/chips/centaur/utils/imageProcs/cen_ringId.H
index 9d0bc609..9af2e9e0 100644
--- a/import/chips/centaur/utils/imageProcs/cen_ringId.H
+++ b/import/chips/centaur/utils/imageProcs/cen_ringId.H
@@ -406,7 +406,7 @@ ringid_get_chiplet(RingId_t i_ringId);
 // as determined by ringId
 void
 ringid_get_chiplet_properties(
-    ChipletType_t      i_chiplet,
+    ChipletType_t      i_chipletType,
     ChipletData_t**    o_cpltData,
     GenRingIdList**    o_ringComm,
     GenRingIdList**    o_ringInst,
diff --git a/import/chips/common/utils/imageProcs/common_ringId.C b/import/chips/common/utils/imageProcs/common_ringId.C
index a99cddab..b631a259 100644
--- a/import/chips/common/utils/imageProcs/common_ringId.C
+++ b/import/chips/common/utils/imageProcs/common_ringId.C
@@ -44,11 +44,212 @@ const char* ppeTypeName[] = { "SBE",
 const char* ringVariantName[] = { "BASE",
                                   "CC",
                                   "RL",
-                                  "OVRD",
-                                  "OVLY"
+                                  "RL2",
                                 };
 
+#ifndef __HOSTBOOT_MODULE  // This is only used by ring_apply in EKB
 
+static int get_ipl_base_param( char*& l_ringPath )
+{
+    l_ringPath = getenv("IPL_BASE");
+
+    if (l_ringPath == NULL)
+    {
+        MY_ERR("p9_ring_apply.C: ring path: IPL_BASE environment parameter not set.\n");
+        return INFRASTRUCT_RC_ENV_ERROR;
+    }
+
+    return INFRASTRUCT_RC_SUCCESS;
+}
+
+static int get_ipl_cache_contained_param( char*& l_ringPath)
+{
+    l_ringPath = getenv("IPL_CACHE_CONTAINED");
+
+    if (l_ringPath == NULL)
+    {
+        MY_ERR("p9_ring_apply.C: ring path: IPL_CACHE_CONTAINED environment parameter not set.\n");
+        return INFRASTRUCT_RC_ENV_ERROR;
+    }
+
+    return INFRASTRUCT_RC_SUCCESS;
+}
+
+static int get_ipl_risk_param( char*& l_ringPath)
+{
+    l_ringPath = getenv("IPL_RISK");
+
+    if (l_ringPath == NULL)
+    {
+        MY_ERR("p9_ring_apply.C: ring path: IPL_RISK environment parameter not set.\n");
+        return INFRASTRUCT_RC_ENV_ERROR;
+    }
+
+    return INFRASTRUCT_RC_SUCCESS;
+}
+
+static int get_runtime_base_param( char*& l_ringPath)
+{
+    l_ringPath = getenv("RUNTIME_BASE");
+
+    if (l_ringPath == NULL)
+    {
+        MY_ERR("p9_ring_apply.C: ring path: RUNTIME_BASE environment parameter not set.\n");
+        return INFRASTRUCT_RC_ENV_ERROR;
+    }
+
+    return INFRASTRUCT_RC_SUCCESS;
+}
+static int get_runtime_risk_param( char*& l_ringPath)
+{
+    l_ringPath = getenv("RUNTIME_RISK");
+
+    if (l_ringPath == NULL)
+    {
+        MY_ERR("p9_ring_apply.C: ring path: RUNTIME_RISK environment parameter not set.\n");
+        return INFRASTRUCT_RC_ENV_ERROR;
+    }
+
+    return INFRASTRUCT_RC_SUCCESS;
+}
+
+static int get_runtime_risk2_param( char*& l_ringPath)
+{
+    l_ringPath = getenv("RUNTIME_RISK2");
+
+    if (l_ringPath == NULL)
+    {
+        MY_ERR("p9_ring_apply.C: ring path: RUNTIME_RISK2 environment parameter not set.\n");
+        return INFRASTRUCT_RC_ENV_ERROR;
+    }
+
+    return INFRASTRUCT_RC_SUCCESS;
+}
+
+int ringid_get_raw_ring_file_path( uint32_t        i_magic,
+                                   RingVariant_t   i_ringVariant,
+                                   char*           io_ringPath )
+{
+    int   rc = INFRASTRUCT_RC_SUCCESS;
+    char* l_ringDir = NULL;
+
+    do
+    {
+
+        if ( i_magic == TOR_MAGIC_SBE )
+        {
+            if ( i_ringVariant == RV_BASE )
+            {
+                rc = get_ipl_base_param(l_ringDir);
+            }
+            else if ( i_ringVariant == RV_CC )
+            {
+                rc = get_ipl_cache_contained_param(l_ringDir);
+            }
+            else if ( i_ringVariant == RV_RL )
+            {
+                rc = get_ipl_risk_param(l_ringDir);
+            }
+            else if ( i_ringVariant == RV_RL2 )
+            {
+                // Valid RV for Quad chiplets but there's just no RL2 rings for SBE phase (by convention).
+                rc = TOR_NO_RINGS_FOR_VARIANT;
+                break;
+            }
+            else
+            {
+                MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n",
+                       i_ringVariant, i_magic);
+                rc = TOR_INVALID_VARIANT;
+            }
+
+            if (rc)
+            {
+                break;
+            }
+
+            strcat(io_ringPath, l_ringDir);
+            strcat(io_ringPath, "/");
+        }
+        else if ( i_magic == TOR_MAGIC_CME ||
+                  i_magic == TOR_MAGIC_SGPE )
+        {
+            if ( i_ringVariant == RV_BASE )
+            {
+                rc = get_runtime_base_param(l_ringDir);
+            }
+            else if ( i_ringVariant == RV_CC )
+            {
+                // Valid RV for Quad chiplets but there's just no CC rings for runtime phases (by convention).
+                rc = TOR_NO_RINGS_FOR_VARIANT;
+                break;
+            }
+            else if ( i_ringVariant == RV_RL )
+            {
+                rc = get_runtime_risk_param(l_ringDir);
+            }
+            else if ( i_ringVariant == RV_RL2 )
+            {
+                rc = get_runtime_risk2_param(l_ringDir);
+            }
+            else
+            {
+                MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n",
+                       i_ringVariant, i_magic);
+                rc = TOR_INVALID_VARIANT;
+            }
+
+            if (rc)
+            {
+                break;
+            }
+
+            strcat(io_ringPath, l_ringDir);
+            strcat(io_ringPath, "/");
+        }
+        else if ( i_magic == TOR_MAGIC_CEN )
+        {
+            if ( i_ringVariant == RV_BASE )
+            {
+                rc = get_ipl_base_param(l_ringDir);
+            }
+            else if ( i_ringVariant == RV_RL )
+            {
+                rc = get_ipl_risk_param(l_ringDir);
+            }
+            else
+            {
+                MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n",
+                       i_ringVariant, i_magic);
+                rc = TOR_INVALID_VARIANT;
+            }
+
+            if (rc)
+            {
+                break;
+            }
+
+            strcat(io_ringPath, l_ringDir);
+            strcat(io_ringPath, "/");
+        }
+        else if ( i_magic == TOR_MAGIC_OVRD ||
+                  i_magic == TOR_MAGIC_OVLY )
+        {
+            // Path already fully qualified. Return io_ringPath as is.
+        }
+        else
+        {
+            MY_ERR("Unsupported value of TOR magic(=0x%X)\n", i_magic);
+            rc = TOR_INVALID_MAGIC_NUMBER;
+        }
+
+    }
+    while(0);
+
+    return rc;
+}
+
+#endif // End of  ifndef __HOSTBOOT_MODULE
 
 int ringid_get_noof_chiplets( ChipType_t  i_chipType,
                               uint32_t    i_torMagic,
@@ -58,6 +259,7 @@ int ringid_get_noof_chiplets( ChipType_t  i_chipType,
     {
         case CT_P9N:
         case CT_P9C:
+        case CT_P9A:
             if ( i_torMagic == TOR_MAGIC_SBE  ||
                  i_torMagic == TOR_MAGIC_OVRD ||
                  i_torMagic == TOR_MAGIC_OVLY )
@@ -105,7 +307,8 @@ int ringid_get_noof_chiplets( ChipType_t  i_chipType,
 
 int  ringid_get_properties( ChipType_t         i_chipType,
                             uint32_t           i_torMagic,
-                            ChipletType_t      i_chiplet,
+                            uint8_t            i_torVersion,
+                            ChipletType_t      i_chipletType,
                             ChipletData_t**    o_chipletData,
                             GenRingIdList**    o_ringIdListCommon,
                             GenRingIdList**    o_ringIdListInstance,
@@ -117,18 +320,25 @@ int  ringid_get_properties( ChipType_t         i_chipType,
     {
         case CT_P9N:
         case CT_P9C:
+        case CT_P9A:
             if ( i_torMagic == TOR_MAGIC_SBE  ||
                  i_torMagic == TOR_MAGIC_OVRD ||
                  i_torMagic == TOR_MAGIC_OVLY )
             {
                 P9_RID::ringid_get_chiplet_properties(
-                    i_chiplet,
+                    i_chipletType,
                     o_chipletData,
                     o_ringIdListCommon,
                     o_ringIdListInstance,
                     o_ringVariantOrder,
                     o_numVariants );
 
+                if ( i_torVersion < 6 &&
+                     (i_chipletType == P9_RID::EQ_TYPE || i_chipletType == P9_RID::EC_TYPE) )
+                {
+                    *o_numVariants = *o_numVariants - 1;
+                }
+
                 if ( i_torMagic == TOR_MAGIC_OVRD ||
                      i_torMagic == TOR_MAGIC_OVLY )
                 {
@@ -142,6 +352,11 @@ int  ringid_get_properties( ChipType_t         i_chipType,
                 *o_ringIdListInstance = (GenRingIdList*)P9_RID::EC::RING_ID_LIST_INSTANCE;
                 *o_ringVariantOrder   = (RingVariantOrder*)P9_RID::EC::RING_VARIANT_ORDER;
                 *o_numVariants        = P9_RID::EC::g_chipletData.iv_num_ring_variants;
+
+                if (i_torVersion < 6)
+                {
+                    *o_numVariants = *o_numVariants - 1;
+                }
             }
             else if ( i_torMagic == TOR_MAGIC_SGPE )
             {
@@ -150,6 +365,11 @@ int  ringid_get_properties( ChipType_t         i_chipType,
                 *o_ringIdListInstance = (GenRingIdList*)P9_RID::EQ::RING_ID_LIST_INSTANCE;
                 *o_ringVariantOrder   = (RingVariantOrder*)P9_RID::EQ::RING_VARIANT_ORDER;
                 *o_numVariants        = P9_RID::EQ::g_chipletData.iv_num_ring_variants;
+
+                if (i_torVersion < 6)
+                {
+                    *o_numVariants = *o_numVariants - 1;
+                }
             }
             else
             {
@@ -166,7 +386,7 @@ int  ringid_get_properties( ChipType_t         i_chipType,
                  i_torMagic == TOR_MAGIC_OVRD )
             {
                 CEN_RID::ringid_get_chiplet_properties(
-                    i_chiplet,
+                    i_chipletType,
                     o_chipletData,
                     o_ringIdListCommon,
                     o_ringIdListInstance,
diff --git a/import/chips/p9/utils/imageProcs/p9_ringId.C b/import/chips/p9/utils/imageProcs/p9_ringId.C
index d3e3a795..ebe24679 100644
--- a/import/chips/p9/utils/imageProcs/p9_ringId.C
+++ b/import/chips/p9/utils/imageProcs/p9_ringId.C
@@ -61,7 +61,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
     {"perv_repr"             , 0x13, 0x01, 0x01, VPD_RING    , 0x01034006},
     {"occ_repr"              , 0x14, 0x01, 0x01, VPD_RING    , 0x01030806},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -85,7 +85,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
     {"n0_nx_repr"          , 0x0a, 0x02, 0x02, VPD_RING    , 0x02032006},
     {"n0_cxa0_repr"        , 0x0b, 0x02, 0x02, VPD_RING    , 0x02031006},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID};
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT};
 };
 
 
@@ -113,7 +113,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
     {"n1_ioo1_repr"        , 0x0e, 0x03, 0x03, VPD_RING    , 0x03030406},
     {"n1_mcs23_repr"       , 0x0f, 0x03, 0x03, VPD_RING    , 0x03030206},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID};
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT};
 };
 
 
@@ -137,7 +137,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
     {"n2_cxa1_repr"        , 0x0a, 0x04, 0x04, VPD_RING    , 0x04032006},
     {"n2_psi_repr"         , 0x0b, 0x04, 0x04, VPD_RING    , 0x04030206},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -162,7 +162,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
     {"n3_mcs01_repr"       , 0x0b, 0x05, 0x05, VPD_RING    , 0x05030106},
     {"n3_np_repr"          , 0x0c, 0x05, 0x05, VPD_RING    , 0x05030806},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -193,7 +193,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
     {"xb_io1_repr"         , 0x15, 0x06, 0x06, VPD_RING    , 0x06031106},
     {"xb_io2_repr"         , 0x16, 0x06, 0x06, VPD_RING    , 0x06030886},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -224,7 +224,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
     {"mc_iom01_repr"       , 0x11, 0x07, 0x08, VPD_RING    , 0x07031006},
     {"mc_iom23_repr"       , 0x12, 0x07, 0x08, VPD_RING    , 0x07030806},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -244,7 +244,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
     {"ob0_repr"              , 0x07, 0x09, 0x09, VPD_RING    , 0x09037006},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -264,7 +264,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
     {"ob1_repr"              , 0x07, 0x0a, 0x0a, VPD_RING    , 0x0A037006},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -284,7 +284,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
     {"ob2_repr"              , 0x07, 0x0b, 0x0b, VPD_RING    , 0x0B037006},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -304,7 +304,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
     {"ob3_repr"              , 0x07, 0x0c, 0x0c, VPD_RING    , 0x0C037006},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -322,7 +322,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
     {"pci0_repr"           , 0x05, 0x0d, 0x0d, VPD_RING    , 0x0D037006},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -340,7 +340,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
     {"pci1_repr"           , 0x05, 0x0e, 0x0e, VPD_RING    , 0x0E037806},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -358,7 +358,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
     {"pci2_repr"           , 0x05, 0x0F, 0x0F, VPD_RING    , 0x0F037C06},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT };
 };
 
 
@@ -441,7 +441,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
     {"ex_l3_refr_repr"            , 0x45, 0x10, 0x1b, VPD_RING    , 0x10030046},
     {"ex_l3_refr_time"            , 0x46, 0x10, 0x1b, VPD_RING    , 0x10030047},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, CC, RL };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_CC, RV_RL, RV_RL2 };
 };
 
 
@@ -460,7 +460,7 @@ const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
     { "ec_repr"            , 0x05, 0x20, 0x37, VPD_RING    , 0x20037006},
 };
-const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, CC, RL };
+const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_CC, RV_RL, RV_RL2 };
 };
 
 
@@ -475,14 +475,14 @@ ChipletType_t P9_RID::ringid_get_chiplet(RingId_t i_ringId)
 }
 
 void P9_RID::ringid_get_chiplet_properties(
-    ChipletType_t      i_chiplet,
+    ChipletType_t      i_chipletType,
     ChipletData_t**    o_cpltData,
     GenRingIdList**    o_ringComm,
     GenRingIdList**    o_ringInst,
     RingVariantOrder** o_varOrder,
     uint8_t*           o_varNumb)
 {
-    switch (i_chiplet)
+    switch (i_chipletType)
     {
         case PERV_TYPE :
             *o_cpltData = (ChipletData_t*)   &PERV::g_chipletData;
diff --git a/import/chips/p9/utils/imageProcs/p9_ringId.H b/import/chips/p9/utils/imageProcs/p9_ringId.H
index 302cd562..be256bbf 100644
--- a/import/chips/p9/utils/imageProcs/p9_ringId.H
+++ b/import/chips/p9/utils/imageProcs/p9_ringId.H
@@ -686,7 +686,7 @@ static const ChipletData_t g_chipletData =
     66, // 66 common rings for Quad chiplet.
     5,  // 5 instance specific rings for each EQ chiplet
     9,  // 9 different rings since 2 per EX ring and 1 per EQ
-    3,  // 3 ring variants: BASE, CC, RL
+    4,  // 4 ring variants: BASE, CC, RL, RL2
 };
 }; // end of namespace EQ
 
@@ -711,7 +711,7 @@ static const ChipletData_t g_chipletData =
     6,  // 6 common rings for Core chiplet
     1,  // 1 instance specific ring for each Core chiplet
     1,
-    3,  // 3 ring variants: BASE, CC, RL
+    4,  // 4 ring variants: BASE, CC, RL, RL2
 };
 }; // end of namespace EC
 
@@ -1252,7 +1252,7 @@ ringid_get_chiplet(RingId_t i_ringId);
 // as determined by ringId
 void
 ringid_get_chiplet_properties(
-    ChipletType_t      i_chiplet,
+    ChipletType_t      i_chipletType,
     ChipletData_t**    o_cpltData,
     GenRingIdList**    o_ringComm,
     GenRingIdList**    o_ringInst,