diff options
| author | Yue Du <daviddu@us.ibm.com> | 2016-11-17 21:00:10 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 16:55:50 -0500 |
| commit | e86a2bc722c755f5d04dcd6c7258f5ceb41ba6e2 (patch) | |
| tree | b9294780d1352565e15e98accf8688b2211886d6 | |
| parent | d6ab1af3663b21708e5b15ea0166aecd63e5724a (diff) | |
| download | talos-hcode-e86a2bc722c755f5d04dcd6c7258f5ceb41ba6e2.tar.gz talos-hcode-e86a2bc722c755f5d04dcd6c7258f5ceb41ba6e2.zip | |
STOP: DD2 - scom hrmor instead of RAM
Change-Id: I5243f4940ef98952752171a3411f3bd4360a7cbb
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32798
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: ADAM S. HALE <ashale@us.ibm.com>
Dev-Ready: ADAM S. HALE <ashale@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h | 1 | ||||
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c | 25 |
2 files changed, 22 insertions, 4 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index 74f20016..12e7e9d9 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -81,6 +81,7 @@ #define SCRACTH1 0x20010A87 #define THREAD_INFO 0x20010A9B #define DIRECT_CONTROLS 0x20010A9C +#define HRMOR 0x20010AB9 #define C_SYNC_CONFIG 0x20030000 #define C_OPCG_ALIGN 0x20030001 diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index 022779ac..8ca64670 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -636,10 +636,14 @@ p9_cme_stop_exit() while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); - PK_TRACE_INF("SX4.O: Core Wakes Up, Ramming HRMOR with HOMER address"); + cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_BASE + CME_HEADER_IMAGE_OFFSET); + scom_data.value = pCmeImgHdr->g_cme_cpmr_PhyAddr & BITS64(13, 30); //HRMOR[13:42] +#if NIMBUS_DD_LEVEL == 1 #if !SKIP_RAM_HRMOR + PK_TRACE_INF("SX4.O: Core Wakes Up, Ramming HRMOR with HOMER address"); + PK_TRACE("Activate thread0 for RAM via THREAD_INFO[18]"); CME_PUTSCOM(THREAD_INFO, core, BIT64(18)); @@ -649,9 +653,6 @@ p9_cme_stop_exit() PK_TRACE("Set SPR mode to LT0-7 via SPR_MODE[20-27]"); CME_PUTSCOM(SPR_MODE, core, BITS64(20, 8)); - cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_BASE + CME_HEADER_IMAGE_OFFSET); - scom_data.value = pCmeImgHdr->g_cme_cpmr_PhyAddr & BITS64(13, 30); //HRMOR[13:42] - if (core & CME_MASK_C0) { PK_TRACE("Set SPRC to scratch0 for core0 via SCOM_SPRC"); @@ -703,6 +704,22 @@ p9_cme_stop_exit() CME_PUTSCOM(RAM_MODEREG, core, 0); #endif +// Nimbus DD2+ +#else + + PK_TRACE_INF("SX4.O: Core Wakes Up, Write HRMOR with HOMER address"); + +#if EPM_P9_TUNING + + CME_PUTSCOM(HRMOR, core, 0x200000); + +#else + + CME_PUTSCOM(HRMOR, core, scom_data.value); + +#endif + +#endif PK_TRACE_INF("SX4.P: S-Reset All Core Threads to Run Self Restore Image"); CME_PUTSCOM(DIRECT_CONTROLS, core, |
