SGPE and CME scanning integration

- Enable FAPI2 targets (move to .C)
- Add/enhance hcode_image_build and wrapper tracing for debug
- Fix CME boot to match the layout of CPMR with common scanning
- Add internal target creation to initf for testing
- Update p9_hcode_image_defines with realistic sizes.
- Cleaned up some wrappers for better debug and tracing
- Cleaned up some extraneous defines
- Fixed vector constructor functionality.
    - Removed -gc-sections from stop_gpe.mk so that constructor code remained
    - Fixed hcode_image_build in its adding of scan rings to not overlay the
      Hcode data region.
- Fix quad based creation of local target
- Redid boot_loader to properly deal with scan ring sections
- Fix boot copier header dependency
- Moved SGPE Hcode space to 38KB to deal with present size;  Made SGPE total
  OCC SRAM allocation 80KB for now.  This growth is due to fapi2 required
  vector support (4 x 128KB) plus target init (1KB) plus scan ring allocation
  per latest assumptions. The FAPI2 elements will be readdressed later.
- Remove skip arrayinit/scan0 from istep15_hack and into EPM_TUNING
- Some bug fixes in hcode_image_defines to get proper common ring offsets
  in SGPE header as well as proper placement of common rings in image
- Changes from Prasad with putrings updates
- Removed break points to call broadside scans in CME and SGPE codes.
- Added Prasad's changes for putring for CME and SGPE.
- Increased thread stack size
- Rebased and commented out memory faulting code for now
- Removed call in p9_pm_stop_gpe_init to ppe_state due to HB strings (for now)
- Fix SGPE_ALLOCATED_SIZE
- Boot loader fix
- Pulled in PK PBA context bug fix as this corrupts the PBASLVCTL0 and thus
  memory accesses
- Make CPMR and CME Header values have maximums. Add check to not allow overrun
- Hcode Image Wrapper update
- CME header debug output

Change-Id: I71718485ff3192f3723fdfa03b8bc6f558ef120e
RTC: 136960
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27421
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

31 files changed, 812 insertions, 674 deletions

diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
index 870051bf..15b1e6c3 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
@@ -46,7 +46,6 @@
 namespace p9_hcodeImageBuild
 {
 #endif //__PPE_PLAT
-
 #endif //__ASSEMBLER__
 
 // Constants used in both C++ and Assembler/Linker code
@@ -280,14 +279,15 @@ HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE);
 #endif
 
 #ifndef __ASSEMBLER__
+
 /**
  * @brief   summarizes constants associated with hcode image build.
  */
 enum
 {
+    HALF_KB                     = 512,
     ONE_KB                      = 1024,
     ONE_MB                      = 1024 * 1024,
-    HALF_KB                     = 512,
     HARDWARE_IMG_SIZE           = ONE_MB,
     OCC_HOST_AREA_SIZE          = ONE_MB,
     HOMER_OCC_REGION_NUM        = 0,
@@ -295,70 +295,122 @@ enum
     HOMER_CMPR_REGION_NUM       = 2,
     HOMER_PPMR_REGION_NUM       = 3,
     MAX_CORES_PER_CHIP          = 24,
+    THREADS_PER_CORE            = 4,
     MAX_CME_PER_CHIP            = 12,
+    MAX_CACHE_CHIPLETS          = 6,
+    CACH0_CHIPLET_ID            = 0x10,
     CORE0_CHIPLET_ID            = 0x20,
     PAD_OPCODE                  = 0x00000200,   //ATTN Opcode
     PPE_RESERVE_AREA            = 0x200,
     FUSE_STATE                  = 0xAA,
     UNFUSE_STATE                = 0xBB,
     PK_DBG_PTR_AREA_SIZE        = 64,
+    SCOM_ENTRY_SIZE             = 16,           // 4B pad, 4B address, 8B data
 
-    // QPMR
+    //---- QPMR  ----
     QPMR_OFFSET                 = HOMER_QPMR_REGION_NUM * ONE_MB,
+
+    //** Boot Loaders
     SGPE_LVL_1_BOOT_LOAD_SIZE   = ONE_KB,
     SGPE_LVL_2_BOOT_LOAD_SIZE   = ONE_KB,
+
+    //** Hcode
     SGPE_INT_VECT               = 384,
+    //SGPE_IMG_HEADER             = 64,
     SGPE_IMG_HEADER             = sizeof(sgpeHeader_t),
-    SGPE_HCODE_SIZE             = 32 * ONE_KB, // FIXME RTC 155018 Revisit after Hcode optimization
+    SGPE_DBG_PTR_AREA_SIZE      = 64,
+    //SGPE_HCODE_SIZE             = 32 * ONE_KB, // FIXME RTC 155018 Revisit after Hcode optimization
+    SGPE_HCODE_SIZE             = 38 * ONE_KB,  // @todo RTC 158543 Reallocate space
+
     SGPE_EXE_SIZE               = (SGPE_HCODE_SIZE - ( SGPE_INT_VECT +
                                    SGPE_IMG_HEADER + PK_DBG_PTR_AREA_SIZE )),
-    SGPE_COMMON_RING            = 13  * ONE_KB, // Common rings (10KB) + Override rings(3KB)
-    CACHE_INST_SPECIFIC_SIZE    = 19  * ONE_KB,
-    CACHE_SCOM_RESTORE_SIZE     = 6 * ONE_KB, //4488B rounded to 6KB
+
+    SGPE_ALLOCATED_SIZE         = SGPE_HCODE_SIZE,   // @todo RTC 158543 Reallocate space (collapse??)
+
+    //** Scan
+    //SGPE_COMMON_RING            = 13  * ONE_KB, // Common rings (10KB) + Override rings(3KB)
+    SGPE_COMMON_RING_SIZE       = 13 * ONE_KB,  // 400B * 9 rings * 3 types (base, RL, CC)
+    SGPE_OVERRIDE_RING_SIZE     = 3 * ONE_KB,   // 300B * 9 rings
+
+    CACHE_INST_SPECIFIC_SIZE    = (3 * ONE_KB) + HALF_KB, // per cache, 1KB/ring x 5 rings/cache
+    CACHE_SPECIFIC_RING_SIZE    = MAX_CACHE_CHIPLETS * CACHE_INST_SPECIFIC_SIZE,
     SGPE_INSTRUMENTATION_SIZE   = 2 * ONE_KB,
-    MAX_CACHE_CHIPLET           = 6,
-    CACH0_CHIPLET_ID            = 0x10,
 
-    SGPE_MAX_AREA_SIZE          = 64 * ONE_KB,
+    //** SCOM
+    NUM_CACHE_SCOM_REGS         = 47 + 1,       // 16 L2 repr, 16 L3 repr, 15 non-repr, 1 NULL
+    CACHE_SCOM_RESTORE_SIZE     = MAX_CACHE_CHIPLETS * NUM_CACHE_SCOM_REGS * SCOM_ENTRY_SIZE,
+
+    CACHE_SCOM_START            = 128 * ONE_KB, // HOMER offset from QPMR
+
+    //** OCC SRAM Allocation
+    SGPE_MAX_AREA_SIZE          = 80 * ONE_KB,  // Allocation within the OCC SRAM
+    SGPE_RESERVE_SIZE           = SGPE_MAX_AREA_SIZE -
+                                  ( SGPE_HCODE_SIZE +
+                                    SGPE_COMMON_RING_SIZE +
+                                    CACHE_SCOM_RESTORE_SIZE +
+                                    SGPE_OVERRIDE_RING_SIZE +
+                                    CACHE_SCOM_RESTORE_SIZE),
 
-    // CPMR
+    //---- CPMR ----
     CPMR_OFFSET                 = HOMER_CMPR_REGION_NUM * ONE_MB,
+
+    //** Self Restore
     THREAD_LAUNCHER_SIZE        = 256,
     CORE_INT_AREA               = 8 * ONE_KB,
     SELF_REST_SIZE              = CORE_INT_AREA + THREAD_LAUNCHER_SIZE,
-    CORE_RESTORE_SIZE           = 192 * ONE_KB,
+    CORE_RESTORE_SIZE           = ((2 * ONE_KB) * THREADS_PER_CORE) * MAX_CORES_PER_CHIP,
+
+    //** SCOM
     CORE_SCOM_START             = (256 * ONE_KB),
-    CORE_SCOM_RES_SIZE          = 6 * ONE_KB,
+    CORE_SCOM_RESTORE_SIZE      = SCOM_ENTRY_SIZE * 16, // (15 registers + 1 NULL) per core
+    CORE_SCOM_RES_SIZE          = CORE_SCOM_RESTORE_SIZE * MAX_CORES_PER_CHIP,
+    CME_SCOM_AREA               = CORE_SCOM_RESTORE_SIZE * 2, // 2 cores
+    SCOM_AREA_PER_CME           =  HALF_KB, // 256(ea ) * 2( CORES PER CME) (???)
+
+    //** Hcode
     CME_INT_VECTOR_SIZE         = 384,
+    CME_IMG_HEADER_SIZE         = 64,
     CPMR_CME_HCODE_OFFSET       = (CORE_SCOM_START + CORE_SCOM_RES_SIZE),
-    CME_HCODE_SIZE              = (25 * ONE_KB) + HALF_KB,
+    CME_HCODE_SIZE              = (27 * ONE_KB) + HALF_KB,
+
+    //** Scan
     CORE_COMMON_RING_SIZE       = 3  * ONE_KB, // common ring( 2KB) + common overrides (1KB)
-    CORE_SPECIFIC_RING          = 2  * ONE_KB,
-    SCOM_AREA_PER_CME           =  HALF_KB, // 256(ea ) * 2( CORES PER CME)
-    QUAD_PSTATE_SIZE            = HALF_KB,
-    INSTRUMENTATION_COUNTERS    = HALF_KB,
-    CME_SRAM_HCODE_OFFSET       = 0x00,
-    CORE_RESERVE_SIZE           =
-        CORE_SCOM_START - ( CORE_RESTORE_SIZE + CME_HCODE_SIZE + CORE_COMMON_RING_SIZE + QUAD_PSTATE_SIZE  ),
-
-    CME_REGION_START            =  (CORE_SCOM_START + CORE_SCOM_RES_SIZE),
-    CME_INST_SPEC_RING_START    =  (300 * ONE_KB ) ,
-    RESERVE_CME_RING_AREA       =  ( CME_INST_SPEC_RING_START  - ( CME_REGION_START +
+    CORE_SPECIFIC_RING          = 2 * ONE_KB,   // per core
+    CORE_OVERRIDE_RING          = 1 * ONE_KB,   // common for all cores
+    QUAD_PSTATE_SIZE            = HALF_KB,      // common for all cores
+    CME_INSTRUMENTATION_SIZE    = HALF_KB,      // per CME
+    INSTRUMENTATION_COUNTERS    = HALF_KB,      // (???)
+
+    CORE_RESERVE_SIZE           = CORE_SCOM_START -
+                                  ( CORE_RESTORE_SIZE +
+                                    CME_HCODE_SIZE +
+                                    CORE_COMMON_RING_SIZE +
+                                    QUAD_PSTATE_SIZE  ),
+
+    CME_SRAM_HCODE_OFFSET       = 0x00, //(???)
+    CME_REGION_START            = (CORE_SCOM_START + CORE_SCOM_RES_SIZE),
+    CME_INST_SPEC_RING_START    = 300 * ONE_KB,
+    RESERVE_CME_RING_AREA       = ( CME_INST_SPEC_RING_START  -
+                                    (CME_REGION_START +
                                      CME_HCODE_SIZE +
                                      CORE_COMMON_RING_SIZE +
                                      QUAD_PSTATE_SIZE)),
-    CME_BLOCK_READ_LEN          =  32,
-    CME_BLK_SIZE_SHIFT          =  0x05,
-    CACHE_SCOM_START            =  128 * ONE_KB,
+    CME_BLOCK_READ_LEN          = 32,
+    CME_BLK_SIZE_SHIFT          = 0x05,
 
     // PPMR
+
+    //** Boot Loaders
     PGPE_LVL_1_BOOT_LOAD_SIZE   = ONE_KB,
     PGPE_LVL_2_BOOT_LOAD_SIZE   = ONE_KB,
-    PGPE_INT_VECTOR             =  384,
-    PGPE_HCODE_SIZE             =  32 * ONE_KB,
-    PGPE_PARAM_BLOCK_SIZE       =  4 * ONE_KB,
-    PSTATE_OUTPUT_TABLE         =  4 * ONE_KB,
-    IGNORE_CHIPLET_INSTANCE     =  0xFF,
+    PGPE_INT_VECTOR             = 384,
+    PGPE_HCODE_SIZE             = 30 * ONE_KB,
+    PGPE_PARAM_BLOCK_SIZE       = 8 * ONE_KB,  //Global and OCC PPB
+    PSTATE_OUTPUT_TABLE         = 8 * ONE_KB,
+    IGNORE_CHIPLET_INSTANCE     = 0xFF,
+
+    PGPE_MAX_AREA_SIZE          = 48 * ONE_KB, // @todo RTC 158543 Reallocate space
+
 };
 
 /**
@@ -408,8 +460,10 @@ typedef struct
     uint8_t imgHeader[sizeof(sgpeHeader_t)];
     uint8_t debugPtrs[PK_DBG_PTR_AREA_SIZE];
     uint8_t hcode[SGPE_EXE_SIZE];
-    uint8_t commonRings[SGPE_COMMON_RING];
-    uint8_t cacheSpecificRing[CACHE_INST_SPECIFIC_SIZE];
+    uint8_t commonRings[SGPE_COMMON_RING_SIZE];
+    uint8_t cacheSpecificRing[CACHE_SPECIFIC_RING_SIZE];
+    uint8_t overrideRings[SGPE_OVERRIDE_RING_SIZE];
+    uint8_t cacheScomRestore[CACHE_SCOM_RESTORE_SIZE];
 } SgpeLayout_t;
 
 typedef union CPMRSelfRestoreLayout
diff --git a/import/chips/p9/procedures/ppe/hwpf/include/plat/hw_access.H b/import/chips/p9/procedures/ppe/hwpf/include/plat/hw_access.H
index 703165b4..e00bf5d5 100644
--- a/import/chips/p9/procedures/ppe/hwpf/include/plat/hw_access.H
+++ b/import/chips/p9/procedures/ppe/hwpf/include/plat/hw_access.H
@@ -104,9 +104,10 @@ inline OpModes getOpMode(void)
 /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
 template< TargetType K >
 inline ReturnCode putRing(const Target<K>& i_target,
-                          const RingID i_ringID)
+                          const RingID i_ringID,
+                          const RingMode i_ringMode = fapi2::RING_MODE_HEADER_CHECK)
 {
-    ReturnCode l_rc;
+    ReturnCode l_rc = FAPI2_RC_SUCCESS;
 
     // Find the RS4 string in the SEEPROM
     l_rc = findRS4InImageAndApply(i_target, i_ringID);
diff --git a/import/chips/p9/procedures/ppe/hwpf/include/vector.H b/import/chips/p9/procedures/ppe/hwpf/include/vector.H
index 01d32a9b..41c8bd80 100644
--- a/import/chips/p9/procedures/ppe/hwpf/include/vector.H
+++ b/import/chips/p9/procedures/ppe/hwpf/include/vector.H
@@ -36,7 +36,7 @@
     #define __STDC_LIMIT_MACROS
 #endif
 #include <stdint.h>
-//#include <new>
+#include <new>
 #include <algorithm>
 #include <assert.h>
 
diff --git a/import/chips/p9/procedures/ppe/hwpf/src/plat/fapi2ppeplatfiles.mk b/import/chips/p9/procedures/ppe/hwpf/src/plat/fapi2ppeplatfiles.mk
index 4446e5f8..36866e5f 100644
--- a/import/chips/p9/procedures/ppe/hwpf/src/plat/fapi2ppeplatfiles.mk
+++ b/import/chips/p9/procedures/ppe/hwpf/src/plat/fapi2ppeplatfiles.mk
@@ -43,7 +43,8 @@
 
 
 FAPI2PLAT-CPP-SOURCES +=  target.C
-FAPI2PLAT-CPP-SOURCES +=  plat_utils.C pool.C
+FAPI2PLAT-CPP-SOURCES +=  plat_utils.C
+FAPI2PLAT-CPP-SOURCES +=  pool.C
 
 FAPI2PLAT-S-SOURCES =
 
diff --git a/import/chips/p9/procedures/ppe/hwpf/src/plat/target.C b/import/chips/p9/procedures/ppe/hwpf/src/plat/target.C
index f508d2b5..63de9a4e 100644
--- a/import/chips/p9/procedures/ppe/hwpf/src/plat/target.C
+++ b/import/chips/p9/procedures/ppe/hwpf/src/plat/target.C
@@ -578,7 +578,7 @@ ReturnCode plat_ApplyGards()
 fapi_try_exit:
     return fapi2::current_err;
 }
-
+#endif
 /// @brief Function to return a platform target handle, given the chiplet
 //         number
 //  @param i_chipletNumber The chiplet number of the target
@@ -610,5 +610,5 @@ plat_target_handle_t plat_getTargetHandleByChipletNumber(
 
     return G_vec_targets[l_idx];
 }
-#endif
+
 } // fapi2
diff --git a/import/chips/p9/procedures/ppe/pk/gpe/gpe_common.h b/import/chips/p9/procedures/ppe/pk/gpe/gpe_common.h
index 79b4275a..6e8f8b54 100644
--- a/import/chips/p9/procedures/ppe/pk/gpe/gpe_common.h
+++ b/import/chips/p9/procedures/ppe/pk/gpe/gpe_common.h
@@ -70,7 +70,7 @@
         _liw        r5, pk_unified_irq_prty_mask_handler
         mtlr        r5
         blrl            // On return, d5 contains task prty irq vec.
-        mfsprg      r3, 0 // In case r3 is modified by unified handler, restore to sprg0
+	mfsprg      r3, 0 // In case r3 is modified by unified handler, restore to sprg0
 #else
         _lwzi       %r5, %r5, GPE_GISR0(APPCFG_OCC_INSTANCE_ID)
 #endif
diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S
index 843a4b16..40b672e4 100644
--- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S
+++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S
@@ -385,7 +385,7 @@ ctx_continue_push:
         ## Save the context of the PBASLVCTL reg
         _liw    %r7,  PBA_SLVCTLN(PBASLVCTLN)
         lvd     %d7, 0(%r7)
-        stvd    %d7, PK_CTX_PBASLVCTLV(%r4)
+        stvd    %d7, PK_CTX_PBASLVCTLV(%r1)
 #endif
 
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c
index 81eee16e..89e29279 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c
@@ -117,6 +117,7 @@ EXTERNAL_IRQ_TABLE_END
 
 #define  KERNEL_STACK_SIZE  256
 #define  THREAD_STACK_SIZE  512
+#define  STOP_THREAD_STACK_SIZE  512
 
 #define  CME_THREAD_PRIORITY_STOP_EXIT   1
 #define  CME_THREAD_PRIORITY_STOP_ENTRY  2
@@ -126,7 +127,7 @@ EXTERNAL_IRQ_TABLE_END
 uint8_t  G_kernel_stack[KERNEL_STACK_SIZE];
 
 uint8_t  G_p9_cme_stop_enter_thread_stack[THREAD_STACK_SIZE];
-uint8_t  G_p9_cme_stop_exit_thread_stack[THREAD_STACK_SIZE];
+uint8_t  G_p9_cme_stop_exit_thread_stack[STOP_THREAD_STACK_SIZE];
 uint8_t  G_p9_cme_db_thread_stack[THREAD_STACK_SIZE];
 uint8_t  G_p9_cme_pmcr_thread_stack[THREAD_STACK_SIZE];
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cpmr_img_edit.C b/import/chips/p9/procedures/ppe_closed/cme/p9_cpmr_img_edit.C
index 7aa765ea..1f9f24ef 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/p9_cpmr_img_edit.C
+++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cpmr_img_edit.C
@@ -28,10 +28,7 @@
 #include <time.h>
 #include <stddef.h>   /* offsetof  */
 
-
-//#include <p9_cpmr_header.H>
 #include <p9_cme_img_layout.h>
-//#include <p9_cme_header.H>
 #include <pk_debug_ptrs.h>
 #include <p9_hcode_image_defines.H>
 
@@ -69,11 +66,6 @@ int main(int narg, char* argv[])
     FILE* pCpmr = fopen( argv[2], "r+" );
     FILE* pSelfRest = fopen( argv[3], "r+");
 
-    //FILE* pImage = fopen( "./obj/cme/cme.bin", "r+" );
-    //FILE* pCpmr = fopen( "./obj/cme/cpmr_header.bin", "r+" );
-    //FILE* pSelfRest = fopen( "../../utils/stopreg/selfRest.bin", "r+");
-
-
     time_t buildTime = time(NULL);
     struct tm* headerTime = localtime(&buildTime);
 
@@ -92,26 +84,26 @@ int main(int narg, char* argv[])
             break;
         }
 
-        printf("Debug Pointers Offset   : %d (0x%X)\n", PPE_DEBUG_PTRS_OFFSET, PPE_DEBUG_PTRS_OFFSET);
-        printf("Debug Pointers size     : %d (0x%X)\n", sizeof(pk_debug_ptrs_t), sizeof(pk_debug_ptrs_t));
+        printf("                    Debug Pointers Offset   : %d (0x%X)\n", PPE_DEBUG_PTRS_OFFSET, PPE_DEBUG_PTRS_OFFSET);
+        printf("                    Debug Pointers size     : %d (0x%X)\n", sizeof(pk_debug_ptrs_t), sizeof(pk_debug_ptrs_t));
 
-        printf("CME Image Offset        : %d (0x%X)\n", PPE_DEBUG_PTRS_OFFSET + sizeof(pk_debug_ptrs_t),
+        printf("                    CME Image Offset        : %d (0x%X)\n", PPE_DEBUG_PTRS_OFFSET + sizeof(pk_debug_ptrs_t),
                PPE_DEBUG_PTRS_OFFSET + sizeof(pk_debug_ptrs_t));
 
         fseek (pCpmr, 0, SEEK_END);
         uint32_t Cpmrsize = ftell (pCpmr);
         rewind(pCpmr);
-        printf("CPMR size               : %d (0x%X)\n", Cpmrsize, Cpmrsize);
+        printf("                    CPMR size               : %d (0x%X)\n", Cpmrsize, Cpmrsize);
 
         fseek (pImage, 0, SEEK_END);
         uint32_t Imagesize = ftell (pImage);
         rewind(pImage);
-        printf("Hcode Image size        : %d (0x%X)\n", Imagesize, Imagesize);
+        printf("                    Hcode Image size        : %d (0x%X)\n", Imagesize, Imagesize);
 
         fseek (pSelfRest, 0, SEEK_END);
         uint32_t selfRestSize = ftell (pSelfRest);
         rewind(pSelfRest);
-        printf("Self Restore size       : %d (0x%X)\n", selfRestSize, selfRestSize);
+        printf("                    Self Restore size       : %d (0x%X)\n", selfRestSize, selfRestSize);
 
         // cme build date  yyyymmdd
         fseek ( pImage, CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_build_date) , SEEK_SET );
@@ -119,7 +111,7 @@ int main(int narg, char* argv[])
         uint32_t temp = (((headerTime->tm_year + 1900) << 16) |
                          ((headerTime->tm_mon + 1) << 8) |
                          (headerTime->tm_mday));
-        printf("Build date              : %X -> %04d/%02d/%02d (YYYY/MM/DD)\n",
+        printf("                    Build date              : %X -> %04d/%02d/%02d (YYYY/MM/DD)\n",
                temp, headerTime->tm_year + 1900, headerTime->tm_mon + 1, headerTime->tm_mday);
 
         temp = htonl(temp);
@@ -133,7 +125,7 @@ int main(int narg, char* argv[])
         fwrite(&temp, sizeof(cmeHeader.g_cme_build_ver), 1, pImage );
         fwrite(&temp, sizeof(cpmrHeader.cpmrVersion), 1, pCpmr );
 
-        printf("CME_HEADER_OFFSET        : %X\n", CME_HEADER_OFFSET);
+        printf("                    CME_HEADER_OFFSET        : %X\n", CME_HEADER_OFFSET);
 
         // cme hcode offset
         fseek ( pImage, HCODE_OFFSET_POS , SEEK_SET );
@@ -156,7 +148,8 @@ int main(int narg, char* argv[])
         temp = htonl( selfRestSize );
         fwrite(&temp, sizeof(uint32_t), 1, pCpmr );
 
-        printf("CME Hcode Offset Address: %X\n", CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_offset));
+        printf("                    CME Hcode Offset Address: %X\n", CME_HEADER_OFFSET + offsetof(cmeHeader_t,
+                g_cme_hcode_offset));
         fseek ( pImage, CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_offset) , SEEK_SET );
         temp = CME_HCODE_OFFSET;
         temp = htonl(temp);
@@ -164,7 +157,8 @@ int main(int narg, char* argv[])
         fwrite(&temp, sizeof(cpmrHeader.cmeImgOffset), 1, pCpmr );
 
         // cme hcode length
-        printf("CME HCode Length Address: %X\n", CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_length));
+        printf("                    CME HCode Length Address: %X\n", CME_HEADER_OFFSET + offsetof(cmeHeader_t,
+                g_cme_hcode_length));
         fseek ( pImage, CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_length) , SEEK_SET );
         fseek ( pCpmr, offsetof(cpmrHeader_t, cmeImgLength) , SEEK_SET );
         temp = htonl( Imagesize );
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c
index 5aeca982..d203a638 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c
@@ -25,34 +25,21 @@
 #include <stdio.h>
 #include <stdint.h>
 #include <netinet/in.h>
-#include <time.h>
 #include <stddef.h>   /* offsetof  */
 
 #include <p9_cme_img_layout.h>
 #include <pk_debug_ptrs.h>
 #include <p9_hcode_image_defines.H>
 
-//namespace p9_hcodeImageBuild;
-
 enum
 {
-    HCODE_OFFSET_POS    =   0x190,
-    HCODE_LEN_POS       =   0x194,
-    CME_HCODE_OFFSET    =   0x200,
-    CME_BUILD_DATE_POS  =   0x188,
-    CME_BUILD_VER_POS   =   0x18C,
-    CME_BUILD_VER       =   0x001,
-    CPMR_ATTN_WORD0     =   0x00,
-    CPMR_ATTN_WORD1     =   0x03,
-    CPMR_BUILD_DATE_POS =   0x10,
-    CPMR_BUILD_VER_POS  =   0x14,
-    CPMR_HCODE_OFFSET_POS =   0x20,
-    CPMR_HCODE_LEN_POS    =   0x24,
-    CPMR_SELFREST_OFF_POS =   0x48,
-    CPMR_SELFREST_OFF_VAL =   0x100,
-    CPMR_SELFREST_LEN_POS =   0x4C,
-    CME_IMAGE           =   1,
-    CPMR_IMAGE          =   2,
+
+    CME_HCODE_OFFSET        =   0x200,
+    CPMR_SELFREST_OFF_POS   =   0x48,
+    CPMR_SELFREST_OFF_VAL   =   0x100,
+    CPMR_SELFREST_LEN_POS   =   0x4C,
+    CME_IMAGE               =   1,
+    CPMR_IMAGE              =   2,
 };
 
 int main(int narg, char* argv[])
@@ -65,11 +52,8 @@ int main(int narg, char* argv[])
     }
 
     cmeHeader_t  cmeHeader;
-    //cpmrHeader_t cpmrHeader;
 
     int imageType = CME_IMAGE;
-    long int buildDatePos   = 0;
-    long int buildVerPos    = 0;
     long int hcodeLenPos    = CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_length);
     long int hcodeOffsetPos = CME_HEADER_OFFSET + offsetof(cmeHeader_t, g_cme_hcode_offset);
 
@@ -81,9 +65,6 @@ int main(int narg, char* argv[])
         return -2;
     }
 
-    time_t buildTime = time(NULL);
-    struct tm* headerTime = localtime(&buildTime);
-
     do
     {
         if( !pImage )
@@ -91,60 +72,40 @@ int main(int narg, char* argv[])
             break;
         }
 
-        printf("Debug Pointers Offset   : %d (0x%X)\n", PPE_DEBUG_PTRS_OFFSET, PPE_DEBUG_PTRS_OFFSET);
-        printf("Debug Pointers size     : %ld (0x%lX)\n", sizeof(pk_debug_ptrs_t), sizeof(pk_debug_ptrs_t));
-        printf("CME Image Offset        : %ld (0x%lX)\n", PPE_DEBUG_PTRS_OFFSET + sizeof(pk_debug_ptrs_t),
+        printf("                    Debug Pointers Offset   : %d (0x%X)\n", PPE_DEBUG_PTRS_OFFSET, PPE_DEBUG_PTRS_OFFSET);
+        printf("                    Debug Pointers size     : %ld (0x%lX)\n", sizeof(pk_debug_ptrs_t), sizeof(pk_debug_ptrs_t));
+        printf("                    CME Image Offset        : %ld (0x%lX)\n", PPE_DEBUG_PTRS_OFFSET + sizeof(pk_debug_ptrs_t),
                PPE_DEBUG_PTRS_OFFSET + sizeof(pk_debug_ptrs_t));
 
 
         fseek (pImage, 0, SEEK_END);
         uint32_t size = ftell (pImage);
         rewind (pImage);
-        printf("Hcode Image size        : %d (0x%X)\n", size, size);
+        printf("                    Hcode Image size        : %d (0x%X)\n", size, size);
 
         // For ekb build it's desired to detect the image type w/o special
         // make rules. Better way?
         if(size < CME_HCODE_OFFSET)
         {
             imageType = CPMR_IMAGE;
-            buildDatePos   = offsetof(cpmrHeader_t, cpmrbuildDate);
-            buildVerPos    = offsetof(cpmrHeader_t, cpmrVersion);
             hcodeLenPos    = offsetof(cpmrHeader_t, cmeImgLength);
             hcodeOffsetPos = offsetof(cpmrHeader_t, cmeImgOffset);
-            printf("CPMR size               : %d (0x%X)\n", size, size);
+            printf("                    CPMR size               : %d (0x%X)\n", size, size);
             FILE* pHcodeImage = fopen( argv[2], "r+" );
             fseek (pHcodeImage, 0, SEEK_END);
             size = ftell (pHcodeImage);
             rewind (pHcodeImage);
-            printf("CME Hcode size               : %d (0x%X)\n", size, size);
+            printf("                    CME Hcode size          : %d (0x%X)\n", size, size);
         }
 
-        // cme build date  yyyymmdd
-        fseek ( pImage, buildDatePos , SEEK_SET );
-
-        uint32_t temp = (((headerTime->tm_year + 1900) << 16) |
-                         ((headerTime->tm_mon + 1) << 8) |
-                         (headerTime->tm_mday));
-        printf("Build date              : %X -> %04d/%02d/%02d (YYYY/MM/DD)\n",
-               temp, headerTime->tm_year + 1900, headerTime->tm_mon + 1, headerTime->tm_mday);
-
-        temp = htonl(temp);
-        fwrite(&temp, sizeof(uint32_t), 1, pImage );
-
-        // cme build version
-        fseek ( pImage , buildVerPos, SEEK_SET );
-        temp = htonl(CME_BUILD_VER);
-        fwrite(&temp, sizeof(uint32_t), 1, pImage );
-        printf("CME_HEADER_OFFSET        : %X\n", CME_HEADER_OFFSET);
-
-        printf("CME Hcode Offset Address: %ld (0x%lX)\n", hcodeOffsetPos , hcodeOffsetPos);
+        printf("                    CME Hcode Offset Address: %ld (0x%lX)\n", hcodeOffsetPos , hcodeOffsetPos);
         fseek ( pImage, hcodeOffsetPos , SEEK_SET );
-        temp = CME_HCODE_OFFSET;
+        uint32_t temp = CME_HCODE_OFFSET;
         temp = htonl(temp);
         fwrite(&temp, sizeof(cmeHeader.g_cme_hcode_offset), 1, pImage );
 
         // cme hcode length
-        printf("CME HCode Length Address: %ld (0x%lX)\n", hcodeLenPos, hcodeLenPos);
+        printf("                    CME HCode Length Address: %ld (0x%lX)\n", hcodeLenPos, hcodeLenPos);
         fseek ( pImage, hcodeLenPos, SEEK_SET );
         temp = htonl( size );
         fwrite(&temp, sizeof(cmeHeader.g_cme_hcode_length), 1, pImage );
@@ -156,7 +117,7 @@ int main(int narg, char* argv[])
             fseek (pSelfRest, 0, SEEK_END);
             uint32_t selfRestSize = ftell (pSelfRest);
             rewind(pSelfRest);
-            printf("Self Restore size  %s     : %d (0x%X)\n", argv[3], selfRestSize, selfRestSize);
+            printf("                    Self Restore size  %s     : %d (0x%X)\n", argv[3], selfRestSize, selfRestSize);
 
             fseek ( pImage  , CPMR_SELFREST_OFF_POS , SEEK_SET );
             temp = htonl( CPMR_SELFREST_OFF_VAL );
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
index 94f5c0f5..cbbb2446 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
@@ -405,11 +405,6 @@ p9_cme_stop_exit()
             //=====================
 #if !SKIP_INITF
             PK_TRACE("X8: Core Func Scan");
-#if !ISTEP15_HACK
-            asm volatile ("nop");
-#else
-            asm volatile ("tw 31, 0, 0");
-#endif
             p9_hcd_core_initf(core);
 #endif
 #endif
@@ -576,13 +571,6 @@ p9_cme_stop_exit()
         CME_PUTSCOM(RAM_MODEREG, core, 0);
 #endif
 
-
-#if !ISTEP15_HACK
-        asm volatile ("nop");
-#else
-        asm volatile ("tw 31, 0, 0");
-#endif
-
         PK_TRACE("S-Reset all threads");
         CME_PUTSCOM(DIRECT_CONTROLS, core,
                     BIT64(4) | BIT64(12) | BIT64(20) | BIT64(28));
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c
index 455adf82..c3d3016d 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c
@@ -23,13 +23,22 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 
+#include "plat_ring_traverse.h"
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
+#include "p9_ringid_cme_enums.h"
 
 int
 p9_hcd_core_initf(uint32_t core)
 {
     int rc = CME_STOP_SUCCESS;
+
+    PK_TRACE("Scan ec_func ring core value %d", core);
+    putRing(core, CME_SCOM_EQ, ec_func);
+
+    PK_TRACE("Scan ec_mode ring core value %d", core);
+    putRing(core, CME_SCOM_EQ, ec_mode);
+
     // Markers needed for core ininf
     return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
index d9fa5718..20254411 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
@@ -30,8 +30,10 @@
 // *HWP Team: PM
 // *HWP Level: 2
 // *HWP Consumed by: CME
+
 #include "pk.h"
 #include "ppe42_scom.h"
+#include "p9_cme_irq.h"
 #include "p9_putringutils.h"
 
 //
@@ -50,7 +52,7 @@ uint8_t rs4_get_nibble(const uint8_t* i_rs4Str, const uint32_t i_nibbleIndx)
     uint8_t l_byte;
     uint8_t l_nibble;
 
-    l_byte = i_rs4Str[i_nibbleIndx / 2];
+    l_byte = i_rs4Str[i_nibbleIndx >> 1];
 
 
     if(i_nibbleIndx % 2)
@@ -87,7 +89,7 @@ uint64_t rs4_get_verbatim(const uint8_t* i_rs4Str,
 
     for(i = 1; i <= i_nibbleCount; i++, l_index++)
     {
-        l_byte = i_rs4Str[l_index / 2];
+        l_byte = i_rs4Str[l_index >> 1];
 
         if(l_index % 2)
         {
@@ -114,12 +116,12 @@ uint64_t rs4_get_verbatim(const uint8_t* i_rs4Str,
 /// @param[out] o_numRotate No.of rotates decoded from the stop-code.
 /// @return The number of nibbles decoded.
 ///
-uint64_t stop_decode(const uint8_t* i_rs4Str,
+uint32_t stop_decode(const uint8_t* i_rs4Str,
                      uint32_t i_nibbleIndx,
-                     uint64_t* o_numRotate)
+                     uint32_t* o_numRotate)
 {
-    uint64_t l_numNibblesParsed = 0; // No.of nibbles that make up the stop-code
-    uint64_t l_numNonZeroNibbles = 0;
+    uint32_t l_numNibblesParsed = 0; // No.of nibbles that make up the stop-code
+    uint32_t l_numNonZeroNibbles = 0;
     uint8_t l_nibble;
 
     do
@@ -164,33 +166,7 @@ uint64_t rs4_revle64(const uint64_t i_x)
     return rx;
 }
 
-void getRingProperties(const RingID i_ringId,
-                       uint32_t* o_torOffset,
-                       RINGTYPE* o_ringType)
-{
-    do
-    {
-        // Determine the TOR ID
-        *o_torOffset =
-            (INSTANCE_RING_MASK & (RING_PROPERTIES[i_ringId].iv_torOffSet));
-
-        if(INVALID_RING == *o_torOffset)
-        {
-            break;
-        }
 
-        // Determine Ring Type
-        if(INSTANCE_RING_MARK & (RING_PROPERTIES[i_ringId].iv_torOffSet))
-        {
-            *o_ringType = INSTANCE_RING;
-        }
-        else
-        {
-            *o_ringType = COMMON_RING;
-        }
-    }
-    while(0);
-}
 /// @brief Function to apply the Ring data using the queue method
 //  @param[in] i_core - core select value
 //  @param[in] i_scom_op - scom control value like queue/non-queue
@@ -200,29 +176,24 @@ void getRingProperties(const RingID i_ringId,
 /// @param[in] i_scanData This value has to be scanned when i_operation is SCAN
 void queuedScan(enum CME_CORE_MASKS i_core,
                 enum CME_SCOM_CONTROLS i_scom_op,
-                const uint8_t i_chipletId,
                 enum opType_t i_operation,
-                uint64_t i_opVal,
+                uint32_t i_opVal,
                 uint64_t i_scanData)
 {
-
-    uint32_t l_chiplet = i_chipletId << 24;
-
     do
     {
+        uint32_t l_scomAddress = 0;
+
         // **************
         // Scan or Rotate
         // **************
         if(ROTATE == i_operation)
         {
             // Setup Scom Address for rotate operation
-            uint32_t l_scomAddress = 0x00008000;
+            l_scomAddress = 0x00038000;
 
-            // Add the chiplet ID in the Scom Address
-            l_scomAddress |= l_chiplet;
-
-            const uint64_t l_maxRotates = 0x100000;
-            uint64_t l_rotateCount = i_opVal;
+            const uint32_t l_maxRotates = 4095;
+            uint32_t l_rotateCount = i_opVal;
             uint32_t l_numRotateScoms = 1; // 1 - We need to do atleast one scom
 
             if(i_opVal > l_maxRotates)
@@ -231,12 +202,11 @@ void queuedScan(enum CME_CORE_MASKS i_core,
                 l_rotateCount = l_maxRotates;
             }
 
-
             // Scom Data needs to have the no.of rotates in the bits 12-31
-            l_rotateCount <<= 32;
             uint32_t i;
+            l_scomAddress |= l_rotateCount;
 
-            for(i = 0; i < (l_numRotateScoms + 1); i++)
+            for(i = 0; i < (l_numRotateScoms + 1); ++i)
             {
                 if(i == l_numRotateScoms)
                 {
@@ -246,119 +216,28 @@ void queuedScan(enum CME_CORE_MASKS i_core,
                     }
 
                     l_rotateCount = (i_opVal % l_maxRotates);
-                    l_rotateCount <<= 32;
+                    l_scomAddress = 0x00038000 | l_rotateCount;
                 }
 
-                CME_GETSCOM(l_scomAddress, i_core, i_scom_op, l_rotateCount);
+                CME_GETSCOM(l_scomAddress, i_core, i_scom_op, i_scanData);
             }// end of for loop
         }
         else if(SCAN == i_operation)
         {
             // Setting Scom Address for a 64-bit scan
-            uint32_t l_scomAddress = 0x0000E000;
-
-            // Add the chiplet ID in the Scom Address
-            l_scomAddress |= l_chiplet;
-
-            uint32_t l_scanCount = i_opVal;
-
+            l_scomAddress = 0x0003E000;
 
             // Set the scan count to the actual value
-            l_scomAddress |= l_scanCount;
+            l_scomAddress |= i_opVal;
 
             CME_PUTSCOM(l_scomAddress, i_core, i_scanData);
 
         } // end of if(SCAN == i_operation)
     }
     while(0);
-
 }
 
 
-/// @brief Function to set the Scan Region
-//  @param[in] i_core - core select value
-/// @param[in] i_scanRegion Value to be set to select a Scan Region
-//  @param[in] i_chipletId data from RS4
-void setupScanRegion(enum CME_CORE_MASKS i_core,
-                     uint64_t i_scanRegion,
-                     const uint8_t i_chipletId)
-{
-    uint32_t l_chiplet =  i_chipletId << 24;
-
-    do
-    {
-        // **************************
-        // Setup Scan-Type and Region
-        // **************************
-        uint32_t l_scomAddress = 0x00030005;
-
-        // Add the chiplet ID in the Scom Address
-        l_scomAddress |= l_chiplet;
-
-        CME_PUTSCOM(l_scomAddress, i_core, i_scanRegion);
-    }
-    while(0);
-}
-
-/// @brief Function to write the header data to the ring.
-//  @param[in] i_core - core select value
-/// @param[in] i_header The header data that is to be written.
-//  @param[in] i_chipletId data from RS4
-void writeHeader(enum CME_CORE_MASKS i_core,
-                 const uint64_t i_header,
-                 const uint8_t i_chipletId)
-{
-    do
-    {
-        uint32_t l_chiplet = i_chipletId << 24;
-
-        uint32_t l_scomAddress = 0x0000E040; // 64-bit scan
-        // Add the chiplet ID in the Scom Address
-        l_scomAddress |= l_chiplet;
-
-        CME_PUTSCOM(l_scomAddress, i_core, i_header);
-    }
-    while(0);
-
-
-}
-
-/// @brief Function to reader the header data from the ring and verify it.
-//  @param[in] i_core - core select value
-//  @param[in] i_scom_op - scom control value like queue/non-queue
-/// @param[in] i_header The header data that is expected.
-//  @param[in] i_chipletId data from RS4
-int verifyHeader(enum CME_CORE_MASKS i_core,
-                 enum CME_SCOM_CONTROLS i_scom_op,
-                 const uint64_t i_header,
-                 const uint8_t i_chipletId)
-{
-    int l_rc = 0;
-    uint64_t l_readHeader = 0;
-
-    do
-    {
-        uint32_t l_chiplet = i_chipletId << 24;
-
-        uint32_t l_scomAddress = 0x0003E000; // 64-bit scan
-        // Add the chiplet ID in the Scom Address
-        l_scomAddress |= l_chiplet;
-
-        CME_GETSCOM(l_scomAddress, i_core, i_scom_op, l_readHeader);
-
-        if(l_readHeader != i_header)
-        {
-            PK_TRACE("Check word mismatch %016llx", l_readHeader);
-            pk_halt();
-            break;
-        }
-    }
-    while(0);
-
-    return l_rc;
-
-}
-
 /// @brief Function to decompress the RS4 and apply the Ring data
 //  @param[in] i_core - core select value
 //  @param[in] i_scom_op - scom control value like queue/non-queue
@@ -366,34 +245,31 @@ int verifyHeader(enum CME_CORE_MASKS i_core,
 int rs4DecompressionSvc(
     enum CME_CORE_MASKS i_core,
     enum CME_SCOM_CONTROLS i_scom_op,
-    const uint8_t* i_rs4)
+    uint8_t* i_rs4)
 {
     CompressedScanData_t* l_rs4Header = (CompressedScanData_t*) i_rs4;
-    const uint8_t* l_rs4Str = (i_rs4 + sizeof(CompressedScanData_t));
+    uint8_t* l_rs4Str = (i_rs4 + sizeof(CompressedScanData_t));
 
     enum opType_t l_opType = ROTATE;
-    uint64_t l_nibbleIndx = 0;
-    uint64_t l_bitsDecoded = 0;
+    enum opType_t l_opValue = ROTATE;
+    uint32_t l_nibbleIndx = 0;
+    uint32_t l_bitsDecoded = 0;
     uint64_t l_scanRegion = rs4_revle64(l_rs4Header->iv_scanSelect);
-    uint8_t l_chipletId = l_rs4Header->iv_chipletId;
+    uint32_t l_scanData = 0;
+    PK_TRACE ("rs4DecompressionSvc");
 
     do
     {
-        if (l_rs4Header->iv_length == 0)
-        {
-            break;
-        }
-
         // Set up the scan region for the ring.
-        setupScanRegion(i_core, l_scanRegion, l_chipletId);
+        CME_PUTSCOM(0x00030005, i_core, l_scanRegion);
 
         // Write a 64 bit value for header.
-        const uint64_t l_header = 0xa5a5a5a5a5a5a5a5;
-        writeHeader(i_core, l_header, l_chipletId);
+        CME_PUTSCOM(0x0003E040, i_core, 0xa5a5a5a5a5a5a5a5);
 
         //if the ring length is not 8bit aligned, then we need to skip the
         //padding bits
         uint8_t l_padding_bits = 0;
+        uint64_t l_scomData = 0;
 
         if (l_rs4Header->iv_length % 4)
         {
@@ -408,11 +284,11 @@ int rs4DecompressionSvc(
             if (l_opType == ROTATE)
             {
                 // Determine the no.of ROTATE operations encoded in stop-code
-                uint64_t l_count = 0;
+                uint32_t l_count = 0;
                 l_nibbleIndx += stop_decode(l_rs4Str, l_nibbleIndx, &l_count);
 
                 // Determine the no.of rotates in bits
-                uint64_t l_bitRotates = (4 * l_count);
+                uint32_t l_bitRotates = (4 * l_count);
 
                 //Need to skip 64bits , because we have already written header
                 //data.
@@ -427,91 +303,46 @@ int rs4DecompressionSvc(
                 // Do the ROTATE operation
                 if (l_bitRotates != 0)
                 {
-                    queuedScan(i_core,
-                               i_scom_op,
-                               l_chipletId,
-                               ROTATE,
-                               l_bitRotates, 0);
+                    l_opValue = ROTATE;
+                    l_scanData = l_bitRotates;
+                    l_scomData = 0;
                 }
 
                 l_opType = SCAN;
             }
             else if(l_opType == SCAN)
             {
-                uint8_t l_scanCount = rs4_get_nibble(l_rs4Str, l_nibbleIndx);
+                uint32_t l_scanCount = rs4_get_nibble(l_rs4Str, l_nibbleIndx);
                 l_nibbleIndx++;
 
                 if (l_scanCount == 0)
                 {
+                    PK_TRACE("SCAN COUNT 0");
                     break;
                 }
 
-                if (l_scanCount != 0xF)
-                {
-                    l_bitsDecoded += (4 * l_scanCount);
-                }
+                l_bitsDecoded += (4 * l_scanCount);
 
-                if(0xF == l_scanCount) // We are parsing RS4 for override rings
-                {
-                    uint8_t l_careMask = rs4_get_nibble(l_rs4Str, l_nibbleIndx);
-                    l_nibbleIndx++;
-                    uint8_t l_spyData = rs4_get_nibble(l_rs4Str, l_nibbleIndx);
-                    l_nibbleIndx++;
-
-                    uint8_t l_mask = 0x08;
-                    uint8_t i;
-
-                    for(i = 0; i < 4; i++)
-                    {
-                        if((l_careMask & (l_mask >> i)))
-                        {
-                            uint64_t l_scomData = 0x0;
-
-                            if((l_spyData & (l_mask >> i)))
-                            {
-                                l_scomData = 0xFFFFFFFFFFFFFFFF;
-                            }
-
-                            l_bitsDecoded += 1;
-
-                            queuedScan(i_core,
-                                       i_scom_op,
-                                       l_chipletId,
-                                       SCAN,
-                                       1, // Insert 1 bit
-                                       l_scomData);
-                        }
-                        else
-                        {
-                            l_bitsDecoded += 1;
-
-                            queuedScan(i_core,
-                                       i_scom_op,
-                                       l_chipletId,
-                                       ROTATE,
-                                       1, 0);
-                        }
-                    } // end of looper for bit-parsing a non-zero nibble
-                }
-                else // We are parsing RS4 for base rings
-                {
-                    // Parse the non-zero nibbles of the RS4 string and
-                    // scan them into the ring
-                    uint64_t l_scomData = rs4_get_verbatim(l_rs4Str,
-                                                           l_nibbleIndx,
-                                                           l_scanCount);
-                    l_nibbleIndx += l_scanCount;
-
-                    queuedScan(i_core,
-                               i_scom_op,
-                               l_chipletId,
-                               SCAN,
-                               (l_scanCount * 4),
-                               l_scomData);
-                }
+                // Parse the non-zero nibbles of the RS4 string and
+                // scan them into the ring
+                l_scomData = rs4_get_verbatim(l_rs4Str,
+                                              l_nibbleIndx,
+                                              l_scanCount);
+                l_nibbleIndx += l_scanCount;
+                l_opValue = SCAN;
+                l_scanData = l_scanCount * 4;
 
                 l_opType = ROTATE;
             } // end of - if(l_opType == SCAN)
+
+            if (l_scanData)
+            {
+                queuedScan(i_core,
+                           i_scom_op,
+                           l_opValue,
+                           l_scanData,
+                           l_scomData);
+            }
         }
         while(1);
 
@@ -536,7 +367,6 @@ int rs4DecompressionSvc(
 
                 queuedScan(i_core,
                            i_scom_op,
-                           l_chipletId,
                            SCAN,
                            (4 - l_padding_bits) , // scan 4 bits
                            l_scomData);
@@ -544,39 +374,22 @@ int rs4DecompressionSvc(
         } // end of if(l_nibble != 0)
 
         // Verify header
-        verifyHeader(i_core, i_scom_op, l_header, l_chipletId);
+        uint64_t l_readHeader = 0;
+        CME_GETSCOM(0x0003E000, i_core, i_scom_op, l_readHeader);
+
+        if(l_readHeader != 0xa5a5a5a5a5a5a5a5)
+        {
+            MY_TRACE_ERR ("Check word data mismatch");
+        }
+        else
+        {
+            PK_TRACE("CHECK WORD DATA MATCH Hurrayy !!!!!!");
+        }
 
         // Clean scan region and type data
-        cleanScanRegionandTypeData(i_core, l_chipletId);
+        CME_PUTSCOM(0x00030005, i_core, 0);
     }
     while(0);
 
     return 1;
 }
-
-
-/// @brief Function to clean up the scan region and type
-/// @param[in] i_core - core select value
-//  @param[in] chipletId data from RS4
-void cleanScanRegionandTypeData(
-    enum CME_CORE_MASKS i_core,
-    const uint8_t i_chipletId)
-{
-    uint32_t l_chiplet = i_chipletId << 24;
-
-    do
-    {
-        //////////////////////
-        //cleanup opcg_reg0
-        //////////////////////
-        uint32_t l_scomAddress = 0x00030005;
-
-        // Add the chiplet ID in the Scom Address
-        l_scomAddress |= l_chiplet;
-
-        CME_PUTSCOM(l_scomAddress, i_core, 0);
-
-    }
-    while(0);
-
-}
diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.h b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.h
index 7aa0f527..d56976c7 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.h
@@ -26,7 +26,8 @@
 /// @brief Headers and Constants used by rs4 decompression and
 /// ring SCAN/ROTATE functionality
 ///
-// *HWP HWP Owner: Bilicon Patil <bilpatil@in.ibm.com>
+// *HWP HWP Owner: Michael Floyd <mfloyd@us.ibm.com>
+// *HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com>
 // *HWP FW Owner: Prasad Ranganath <prasadbgr@in.ibm.com>
 // *HWP Team: PM
 // *HWP Level: 2
@@ -36,7 +37,7 @@
 #define _P9_PUTRINGUTILS_H_
 
 #include <cmehw_common.h>
-#include "p9_ringid_cme.h"
+#include "p9_ringid_cme_enums.h"
 
 
 //
@@ -55,9 +56,9 @@ uint64_t rs4_revle64(const uint64_t i_x);
 /// @param[out] o_numRotate No.of rotates decoded from the stop-code.
 /// @return The number of nibbles decoded.
 ///
-uint64_t stop_decode(const uint8_t* i_rs4Str,
+uint32_t stop_decode(const uint8_t* i_rs4Str,
                      uint32_t i_nibbleIndx,
-                     uint64_t* o_numRotate);
+                     uint32_t* o_numRotate);
 
 ///
 /// @brief Return a big-endian-indexed nibble from a byte string
@@ -140,14 +141,13 @@ typedef struct CompressedScanData
 
     /// 7-bit pervasive chiplet Id + Multicast bit
     uint8_t iv_chipletId;
+
+    uint32_t iv_reserved;
 } CompressedScanData_t;
 
 //
 // Function Definitions
 //
-void getRingProperties(const RingID i_ringId,
-                       uint32_t* o_torOffset,
-                       RINGTYPE* o_ringType);
 
 /// @brief Function to apply the Ring data using the queue method
 //  @param[in] i_core - core select value
@@ -159,29 +159,11 @@ void getRingProperties(const RingID i_ringId,
 void queuedScan(
     enum CME_CORE_MASKS i_core,
     enum CME_SCOM_CONTROLS i_scom_op,
-    const uint8_t i_chipletId,
     enum opType_t i_operation,
-    uint64_t i_opVal,
+    uint32_t i_opVal,
     uint64_t i_scanData);
 
 
-/// @brief Function to set the Scan Region
-//  @param[in] i_core - core select value
-/// @param[in] i_scanRegion Value to be set to select a Scan Region
-//  @param[in] i_chipletId data from RS4
-void setupScanRegion(enum CME_CORE_MASKS i_core,
-                     uint64_t i_scanRegion,
-                     const uint8_t i_chipletId);
-
-
-/// @brief Function to write the header data to the ring.
-//  @param[in] i_core - core select value
-/// @param[in] i_header The header data that is to be written.
-//  @param[in] i_chipletId data from RS4
-void writeHeader(enum CME_CORE_MASKS i_core,
-                 const uint64_t i_header,
-                 const uint8_t i_chipletId);
-
 /// @brief Function to reader the header data from the ring and verify it.
 //  @param[in] i_core - core select value
 //  @param[in] i_scom_op - scom control value like queue/non-queue
@@ -189,8 +171,7 @@ void writeHeader(enum CME_CORE_MASKS i_core,
 //  @param[in] i_chipletId data from RS4
 int verifyHeader(enum CME_CORE_MASKS i_core,
                  enum CME_SCOM_CONTROLS i_scom_op,
-                 const uint64_t i_header,
-                 const uint8_t i_chipletId);
+                 const uint64_t i_header);
 
 /// @brief Function to decompress the RS4 and apply the Ring data
 //  @param[in] i_core - core select value
@@ -199,14 +180,7 @@ int verifyHeader(enum CME_CORE_MASKS i_core,
 int rs4DecompressionSvc(
     enum CME_CORE_MASKS i_core,
     enum CME_SCOM_CONTROLS i_scom_op,
-    const uint8_t* i_rs4);
+    uint8_t* i_rs4);
 
 
-/// @brief Function to clean up the scan region and type
-/// @param[in] i_core - core select value
-//  @param[in] chipletId data from RS4
-void cleanScanRegionandTypeData(
-    enum CME_CORE_MASKS i_core,
-    const uint8_t i_chipletId);
-
 #endif
diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_ringid_cme.h b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_ringid_cme.h
index 673f45ce..e20e659f 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_ringid_cme.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_ringid_cme.h
@@ -27,6 +27,7 @@
 #define _P9_RINGID_CME_H_
 
 #include <stdint.h>
+#include "p9_ringid_cme_enums.h"
 
 typedef enum
 {
@@ -34,36 +35,6 @@ typedef enum
     INSTANCE_RING = 1
 } RINGTYPE;
 
-
-///
-/// @enum RingID
-/// @brief Enumeration of Ring ID values. These values are used to traverse
-///        an image having Ring Containers.
-// NOTE: Do not change the numbering, the sequence or add new constants to
-//       the below enum, unless you know the effect it has on the traversing
-//       of the image for Ring Containers.
-typedef enum
-{
-    //*****************************
-    // Rings needed for CME - Start
-    //*****************************
-    // Core Chiplet Rings
-    // Common - apply to all Core instances
-    ec_func = 1,
-    ec_gptr = 2,
-    ec_time = 3,
-    ec_mode = 4,
-
-    // Core Chiplet Rings
-    // EC0 - EC23 instance specific Ring
-    ec_repr = 5,
-    //***************************
-    // Rings needed for SBE - End
-    //***************************
-
-    P9_NUM_RINGS // This shoud always be the last constant
-} RingID; // end of enum RingID
-
 struct CHIPLET_DATA
 {
     // This is the chiplet-ID of the first instance of the Chiplet
@@ -97,28 +68,27 @@ typedef enum RingOffset
     EC_REPR = INSTANCE_RING_MARK | 0
 } ringOffset;
 
-static const struct CHIPLET_DATA g_ecData =
+const struct CHIPLET_DATA g_ecData =
 {
     32, // Core Chiplet ID range is 32-55. The base ID is 32.
     4,  // 4 common rings for Core chiplet
     1,  // 1 instance specific ring for each Core chiplet
-    2   //base and risk level variants supported
+    3   //base,CC and risk level variants supported
 };
 
-static const uint32_t INVALID_RING = 999;
 
 struct ringProperties_t
 {
     ringOffset iv_torOffSet;
 };
 
-static const struct ringProperties_t RING_PROPERTIES[P9_NUM_RINGS] =
+const struct ringProperties_t RING_PROPERTIES[P9_NUM_RINGS] =
 {
     // Core Ring
-    {EC_FUNC}, // 1
-    {EC_GPTR}, // 2
-    {EC_TIME}, // 3
-    {EC_MODE}, // 4
-    {EC_REPR}  // 5
+    {EC_FUNC}, // 0
+    {EC_GPTR}, // 1
+    {EC_TIME}, // 2
+    {EC_MODE}, // 3
+    {EC_REPR}  // 4
 };
 #endif
diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_ringid_cme_enums.h b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_ringid_cme_enums.h
new file mode 100644
index 00000000..e789ecf7
--- /dev/null
+++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_ringid_cme_enums.h
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe_closed/cme/utils/p9_ringid_cme_enums.h $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2016,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef _P9_RINGID_CME_ENUM_H_
+#define _P9_RINGID_CME_ENUM_H_
+#include <stdint.h>
+
+///
+/// @enum RingID
+/// @brief Enumeration of Ring ID values. These values are used to traverse
+///        an image having Ring Containers.
+// NOTE: Do not change the numbering, the sequence or add new constants to
+//       the below enum, unless you know the effect it has on the traversing
+//       of the image for Ring Containers.
+typedef enum
+{
+    //*****************************
+    // Rings needed for CME - Start
+    //*****************************
+    // Core Chiplet Rings
+    // Common - apply to all Core instances
+    ec_func = 0,
+    ec_gptr = 1,
+    ec_time = 2,
+    ec_mode = 3,
+
+    // Core Chiplet Rings
+    // EC0 - EC23 instance specific Ring
+    ec_repr = 4,
+    //***************************
+    // Rings needed for SBE - End
+    //***************************
+
+    P9_NUM_RINGS // This shoud always be the last constant
+} RingID; // end of enum RingID
+
+#endif
diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c b/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c
index 2c3554f4..f083131c 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c
@@ -25,10 +25,35 @@
 
 #include "plat_ring_traverse.h"
 #include "p9_hcode_image_defines.H"
+#include "pk.h"
+#include "p9_ringid_cme.h"
 
 
 
-#define CME_SRAM_BASE 0xFFFF8000
+const uint32_t CME_SRAM_BASE = 0xFFFF8000;
+
+void getRingProperties(const RingID i_ringId,
+                       uint32_t* o_torOffset,
+                       RINGTYPE* o_ringType)
+{
+    do
+    {
+        // Determine the TOR ID
+        *o_torOffset =
+            (INSTANCE_RING_MASK & (RING_PROPERTIES[i_ringId].iv_torOffSet));
+
+        // Determine Ring Type
+        if(INSTANCE_RING_MARK & (RING_PROPERTIES[i_ringId].iv_torOffSet))
+        {
+            *o_ringType = INSTANCE_RING;
+        }
+        else
+        {
+            *o_ringType = COMMON_RING;
+        }
+    }
+    while(0);
+}
 ///
 /// @brief This is a plat specific (CME) function that locates the
 ///        Ring Container in the image and calls the functin to decompress the
@@ -37,7 +62,7 @@
 //  @param[in] i_scom_op - scom control value like queue/non-queue
 /// @param i_ringID The Ring ID that identifies the ring to be applied.
 ///
-int findRS4InImageAndApply(
+int putRing(
     enum CME_CORE_MASKS i_core,
     enum CME_SCOM_CONTROLS i_scom_op,
     const RingID i_ringID)
@@ -49,21 +74,16 @@ int findRS4InImageAndApply(
         // Determine the Offset ID and Ring Type for the given Ring ID.
         uint32_t l_torOffset = 0;
         RINGTYPE l_ringType = COMMON_RING;
-        SectionTOR_t* l_sectionTOR;
         struct CHIPLET_DATA l_chipletData;
         l_chipletData.iv_base_chiplet_number = 0;
         l_chipletData.iv_num_common_rings = 0;
         l_chipletData.iv_num_instance_rings = 0;
         l_chipletData.iv_num_variants = 0;
-        uint32_t l_sectionOffset = 0;
         uint8_t l_chipletID = 0;
+        uint32_t* l_sectionAddr;
 
         getRingProperties(i_ringID, &l_torOffset, &l_ringType);
-
-        if(INVALID_RING == l_torOffset)
-        {
-            break;
-        }
+        PK_TRACE ("Inside putring ringId %d ringtype %d", i_ringID, l_ringType);
 
         CmeHcodeLayout_t* l_hcodeLayout = (CmeHcodeLayout_t*)(CME_SRAM_BASE);
 
@@ -75,55 +95,53 @@ int findRS4InImageAndApply(
 
         if(INSTANCE_RING == l_ringType)
         {
-            l_sectionTOR =
-                (SectionTOR_t*)(l_cmeHeader->g_cme_core_spec_ring_offset);
-            l_sectionOffset = l_sectionTOR->TOC_EC_INSTANCE_RING;
+            if (!(l_cmeHeader->g_cme_core_spec_ring_offset))
+            {
+                break;
+            }
+
+            l_sectionAddr =
+                (uint32_t*)(CME_SRAM_BASE + l_cmeHeader->g_cme_core_spec_ring_offset);
+
             l_chipletID = i_core + l_chipletData.iv_base_chiplet_number;
+            uint8_t l_chipletOffset =
+                (l_chipletID - l_chipletData.iv_base_chiplet_number);
+            l_sectionAddr += (l_chipletOffset *
+                              l_chipletData.iv_num_instance_rings);
         }
         else
         {
-            l_sectionTOR =
-                (SectionTOR_t*)(l_cmeHeader->g_cme_common_ring_offset);
-            l_sectionOffset = l_sectionTOR->TOC_EC_COMMON_RING;
-        }
-
-        // Determine the section TOR address for the ring
-        uint32_t* l_sectionAddr =
-            (uint32_t*)(CME_SRAM_BASE +
-                        l_cmeHeader->g_cme_common_ring_offset + l_sectionOffset);
-
-        if(INSTANCE_RING == l_ringType)
-        {
-            if ( l_chipletID > l_chipletData.iv_base_chiplet_number)
+            if (!(l_cmeHeader->g_cme_common_ring_offset))
             {
-                uint8_t l_chipletOffset =
-                    (l_chipletID - l_chipletData.iv_base_chiplet_number);
-                l_sectionAddr += (l_chipletOffset *
-                                  (l_chipletData.iv_num_instance_rings *
-                                   l_chipletData.iv_num_variants));
-            }
-            else
-            {
-                l_sectionAddr +=
-                    (l_chipletData.iv_num_instance_rings *
-                     l_chipletData.iv_num_variants);
+                break;
             }
+
+            l_sectionAddr =
+                (uint32_t*)(CME_SRAM_BASE + l_cmeHeader->g_cme_common_ring_offset);
         }
 
+
         // The ring variants in section TOR are expected to be in the sequence -
         // 1. Base
         // 2. Risk Level
 
+        PK_TRACE("l_sectionAddr %08x", (uint32_t)l_sectionAddr);
+
         // TOR records of Ring TOR are 2 bytes in size.
         uint16_t* l_ringTorAddr = (uint16_t*)(l_sectionAddr) +
                                   (l_torOffset * l_chipletData.iv_num_variants);
 
+
         if(*l_ringTorAddr != 0)
         {
             uint8_t* l_addr = (uint8_t*)(l_sectionAddr);
             uint8_t* l_rs4Address = (uint8_t*)(l_addr + *l_ringTorAddr);
             l_rc = rs4DecompressionSvc(i_core, i_scom_op, l_rs4Address);
         }
+        else
+        {
+            PK_TRACE("No data for this ringId %d", i_ringID);
+        }
     }
     while(0);
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.h b/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.h
index 00d3df82..eff535b6 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.h
@@ -28,51 +28,6 @@
 
 #include "p9_putringutils.h" // for RS4 decompression utilities
 
-/// @brief This structure represents the layout of the Section-TOR
-///        Section-TOR has the offsets to the different chiplet's
-///        Common Ring section and Instance Ring section
-typedef struct SectionTOR
-{
-    uint32_t TOC_PERV_COMMON_RING;   // Offset of Perv Common Ring section
-    uint32_t TOC_PERV_INSTANCE_RING; // Offset of Perv Instance Ring section
-
-    uint32_t TOC_N0_COMMON_RING;   // Offset of N0 Common Ring section
-    uint32_t TOC_N0_INSTANCE_RING; // Offset of N0 Instance Ring section
-
-    uint32_t TOC_N1_COMMON_RING;   // Offset of N1 Common Ring section
-    uint32_t TOC_N1_INSTANCE_RING; // Offset of N1 Instance Ring section
-
-    uint32_t TOC_N2_COMMON_RING;   // Offset of N2 Common Ring section
-    uint32_t TOC_N2_INSTANCE_RING; // Offset of N2 Instance Ring section
-
-    uint32_t TOC_N3_COMMON_RING;   // Offset of N3 Common Ring section
-    uint32_t TOC_N3_INSTANCE_RING; // Offset of N3 Instance Ring section
-
-    uint32_t TOC_XB_COMMON_RING;   // Offset of XB Common Ring section
-    uint32_t TOC_XB_INSTANCE_RING; // Offset of XB Instance Ring section
-
-    uint32_t TOC_MC_COMMON_RING;   // Offset of MC Common Ring section
-    uint32_t TOC_MC_INSTANCE_RING; // Offset of MC Instance Ring section
-
-    uint32_t TOC_OB_COMMON_RING;   // Offset of OB Common Ring section
-    uint32_t TOC_OB_INSTANCE_RING; // Offset of OB Instance Ring section
-
-    uint32_t TOC_PCI0_COMMON_RING;   // Offset of PCI0 Common Ring section
-    uint32_t TOC_PCI0_INSTANCE_RING; // Offset of PCI0 Instance Ring section
-
-    uint32_t TOC_PCI1_COMMON_RING;   // Offset of PCI1 Common Ring section
-    uint32_t TOC_PCI1_INSTANCE_RING; // Offset of PCI1 Instance Ring section
-
-    uint32_t TOC_PCI2_COMMON_RING;   // Offset of PCI2 Common Ring section
-    uint32_t TOC_PCI2_INSTANCE_RING; // Offset of PCI2 Instance Ring section
-
-    uint32_t TOC_EQ_COMMON_RING;   // Offset of Quad Common Ring section
-    uint32_t TOC_EQ_INSTANCE_RING; // Offset of Quad Instance Ring section
-
-    uint32_t TOC_EC_COMMON_RING;   // Offset of Core Common Ring section
-    uint32_t TOC_EC_INSTANCE_RING; // Offset of Core Instance Ring section
-} SectionTOR_t;
-
 
 ///
 /// @brief This is a plat specific (CME) function that locates the
@@ -82,7 +37,7 @@ typedef struct SectionTOR
 //  @param[in] i_scom_op - scom control value like queue/non-queue
 /// @param i_ringID The Ring ID that identifies the ring to be applied.
 ///
-int findRS4InImageAndApply(
+int putRing(
     enum CME_CORE_MASKS i_core,
     enum CME_SCOM_CONTROLS i_scom_op,
     const RingID i_ringID);
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_copier.S b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_copier.S
index 03ec735b..f22055f3 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_copier.S
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_copier.S
@@ -28,9 +28,9 @@
 #include <sgpe_boot_defines.H>
         .list
 
-	.section .loader_text, "ax", @progbits
+    .section .loader_text, "ax", @progbits
 
-	.global __vectors
+    .global __vectors
 __vectors:
 
     .org __vectors + 0x0000
@@ -44,68 +44,68 @@ __system_reset:
 
     .org __vectors + 0x0060
 __data_storage:
-	b .
+    b .
 
     .org __vectors + 0x0080
 __instruction_storage:
-	b .
+    b .
 
     .org __vectors + 0x00A0
 __external_interrupt_vector:
-	b .
+    b .
 
     .org __vectors + 0x00C0
 __alignment_exception:
-	b .
+    b .
 
     .org __vectors + 0x00E0
 __program_exception:
-	b .
+    b .
 
     .org __vectors + 0x0100
 __dec_interrupt:
-	b .
+    b .
 
     .org __vectors + 0x0120
 __fit_interrupt:
-	b .
+    b .
 
     .org __vectors + 0x0140
 __watchdog_interrupt:
-	b .
+    b .
 
 __bootCopier:
-	//load r3 with BASE_
-        _liw    %r3, HOMER_BOOT_LOADER_LENGTH_ADDR
+    //load r3 with BASE_
+    _liw    %r3, HOMER_BOOT_LOADER_LENGTH_ADDR
 
-	_liw    %r7, HOMER_BOOT_LOADER_OFFSET_ADDR
+    _liw    %r7, HOMER_BOOT_LOADER_OFFSET_ADDR
 
-	//load r4 with address where bootLoader will be loaded in SRAM e.g 0xFFFE8000 (Destination address)
-        _liw    %r4, SRAM_SGPE_BOOT_LOADER_ADDR # dest
+    //load r4 with address where bootLoader will be loaded in SRAM e.g 0xFFFE8000 (Destination address)
+    _liw    %r4, SRAM_SGPE_BOOT_LOADER_ADDR # dest
 
-	//load r9 with QPMR header address
-	_liw    %r9, QPMR_HEADER_ADDR
+    //load r9 with QPMR header address
+    _liw    %r9, HOMER_QPMR_HEADER_ADDR
 
-	//size of image in bytes
-	lwz    r5, 0(r3)
-        li    r6, 3
-        srw   r5, r5, r6    # r5 contains number of bytes, divide by 8 will give number of double words
-        addi r5, r5, 1
-        mtctr   r5          # set the counter for loop
+    //size of image in bytes
+    lwz     r5, 0(r3)
+    li      r6, 3
+    srw     r5, r5, r6    # r5 contains number of bytes, divide by 8 will give number of double words
+    addi    r5, r5, 1
+    mtctr   r5          # set the counter for loop
 
-	// calculating bootLoader image loaded address
-	lwz     r8, 0(r7)   # offset of bootLoader section  in Homer
-        adde    r8, r8, r9  # add base address to offset to get absolute bootLoader address in Homer
+    // calculating bootLoader image loaded address
+    lwz     r8, 0(r7)   # offset of bootLoader section  in Homer
+    adde    r8, r8, r9  # add base address to offset to get absolute bootLoader address in Homer
 
 copy_loop:
-        lvd    d28, 0(r8)  # Load Double word
-        stvd   d28, 0(r4)  # Destination address
-	addi   r8, r8, 8   # Increasing source address
-	addi   r4, r4, 8   # Increasing Dest address
-	bdnz   copy_loop   # Keep repeating the address.
-
-	## Using blr command:
-        _liw  %r6,   SRAM_SGPE_BOOT_LOADER_RESET_ADDR
-        mtlr  r6
-        blr
-        .epilogue __bootCopier
+    lvd    d28, 0(r8)  # Load Double word
+    stvd   d28, 0(r4)  # Destination address
+    addi   r8, r8, 8   # Increasing source address
+    addi   r4, r4, 8   # Increasing Dest address
+    bdnz   copy_loop   # Keep repeating the address.
+
+    ## Using blr command:
+    _liw  %r6,   SRAM_SGPE_BOOT_LOADER_RESET_ADDR
+    mtlr  r6
+    blr
+    .epilogue __bootCopier
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S
index be7e3ffd..26a2b04b 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S
@@ -30,116 +30,194 @@
     .global __vectors
 __vectors:
 
-    .org __vectors + 0x0000 
+    .org __vectors + 0x0000
 __machine_check:
-    b . 
+    b .
 
-    .org __vectors + 0x0040 
+    .org __vectors + 0x0040
     .global __system_reset
 __system_reset:
     b   __bootLoader
 
-    .org __vectors + 0x0060 
+    .org __vectors + 0x0060
 __data_storage:
-    b . 
-     
-    .org __vectors + 0x0080 
+    b .
+
+    .org __vectors + 0x0080
 __instruction_storage:
-    b . 
+    b .
 
-    .org __vectors + 0x00A0 
+    .org __vectors + 0x00A0
 __external_interrupt_vector:
     b .
 
-    .org __vectors + 0x00C0 
+    .org __vectors + 0x00C0
 __alignment_exception:
     b .
 
-    .org __vectors + 0x00E0 
+    .org __vectors + 0x00E0
 __program_exception:
     b .
 
-    .org __vectors + 0x0100 
+    .org __vectors + 0x0100
 __dec_interrupt:
     b .
 
-    .org __vectors + 0x0120 
+    .org __vectors + 0x0120
 __fit_interrupt:
     b .
 
-    .org __vectors + 0x0140 
+    .org __vectors + 0x0140
 __watchdog_interrupt:
     b .
-            
+
 __bootLoader:
-    
+
     ######################
     ## QPMR Header Copy
     ######################
-    ## cal source Address
-    _liw %r9, SRAM_SGPE_BASE_ADDR
-    nop
-    _liw %r8, SGPE_IVPR_OCI_ADDR
-    nop
-    nop
-    stw r9, 0(r8)
 
-    _liw %r10, SRAM_SGPE_HCODE_LENGTH_ADDR
-    _liw  %r3, QPMR_HEADER_ADDR
+    ## Setup the IVPR for the loader context
 
-    ## Cal Destination Address(in r4)
-    _liw %r4, SRAM_SGPE_QPMR_ADDR
+    _liw    %r9, SRAM_SGPE_BOOT_LOADER_ADDR
+    _liw    %r8, SGPE_IVPR_OCI_ADDR
+    stw     r9, 0(r8)
+    
+    ## Enable halt on trap
+    lis     %r3, 0x0100
+    li      %r3, 0
+    mtdbcr  %r3
+
+    ## cal source Address
+    _liw    %r3, HOMER_QPMR_HEADER_ADDR
+
+    ## Calculate Destination Address(in r4)
+    _liw    %r4, SRAM_QPMR_ADDR
 
     ## Find double words(in r5).
-    _liw %r5, QPMR_HEADER_SIZE
-    li r6, 3
-    srw r5,r5,r6
+    _liw    %r5, QPMR_HEADER_SIZE
+    li      r6, 3
+    srw     r5, r5, r6
 
     ## start copying
-    mtctr r5
+    mtctr   r5
 
 qpmr_header_copy_loop:
-    lvd d28,0(r3)
-    stvd d28,0(r4)
-    addi r3,r3,8
-    addi r4,r4,8
-    bdnz qpmr_header_copy_loop
+    lvd     d28, 0(r3)
+    stvd    d28, 0(r4)
+    addi    r3, r3, 8
+    addi    r4, r4, 8
+    bdnz    qpmr_header_copy_loop
 
     #########################
     ## Copy SGPE Header/Exe
     #########################
     ## Calculate Source address(in r8)
-        _liw %r6, SRAM_SGPE_HCODE_OFFSET_ADDR 
-    _liw %r9, QPMR_HEADER_ADDR 
-    lwz  r7, 0(r6)
-    adde r8,r9,r7
-    
+    _liw    %r6, SRAM_SGPE_HCODE_OFFSET_ADDR
+    lwz     r7, 0(r6)
+    _liw    %r9, HOMER_QPMR_HEADER_ADDR
+    adde    r8,r9,r7
+
     ## Calculate Destination address
-    _liw %r4, SRAM_SGPE_BASE_ADDR
-    
-    ##Find the double word counts
-    lwz r5, 0(r10)
+    _liw    %r4, SRAM_SGPE_BASE_ADDR
+
+    ## Calculate the double word count to copy and place in R5
+    ##
+    ## The copy is from the beginning of the SGPE Hcode until the last scan ring
+    ## section found that is found.  For each section, the copy amount will be
+    ## updated to the offset + length (eg the end) of that section.  Once the
+    ## Hcode, Common Rings, and Instance Rings entries in the QPMR are looked
+    ## at, then subtract the QPMR header size as all offsets are based on the
+    ## beginning of the QPMR
+    ##
+    ## R3 : ending QPMR offset to to determine count
+    ## R4 : destination SRAM address
+    ## R5 : final doubleword count
+    ## R6 : scratch
+    ## R7 : offset of the start of the HCode
+    ## R10: address for accessing the QPMR Header entries
+    ## R28: offset of the begining of a section
+    ## R29: length of a section
+    ## R31: scratch
+
+    ## Separate registers are used for debug as they will be blown away upon
+    ## branching to the HCODE anyway
+
+    ## Compute the ending offset of the Hcode section.  Note: the beginning is
+    ## R7
+    _liw    %r10, SRAM_SGPE_HCODE_LENGTH_ADDR
+    lwz     r29, 0(r10)
+    adde    r3, r7, r29
+    lis     r31, 0xB00F
+    ori     r31, r31, 0x0001
+    mtsprg0 r31
+
+    ## Compute the end of the common rings section.
+    ## If not present (eg Offset or length = 0), use the end of the Hcode section
+    _liw    %r10, SRAM_COMMON_RINGS_OFFSET_ADDR
+    lwz     r28, 0(r10)
+    bwz     r28, end_common_rings
+
+    _liw    %r10, SRAM_COMMON_RINGS_LENGTH_ADDR
+    lwz     r29, 0(r10)
+    bwz     r29, end_common_rings
+
+    adde    r3, r28, r29
+    lis     r31, 0xB00F
+    ori     r31, r31, 0x0002
+    mtsprg0 r31
+
+end_common_rings:
+
+    ## Compute the end of the specific rings section.
+    ## If not present (eg Offset or length = 0), use the end of the common section
+    _liw    %r10, SRAM_SPECIFIC_RINGS_OFFSET_ADDR
+    lwz     r28, 0(r10)
+    bwz     r28, end_specific_rings
+
+    _liw    %r10, SRAM_SPECIFIC_RINGS_LENGTH_ADDR
+    lwz     r29, 0(r10)
+    bwz     r29, end_specific_rings
+
+    adde    r3, r28, r29
+    lis     r31, 0xB00F
+    ori     r31, r31, 0x0003
+    mtsprg0 r31
+
+end_specific_rings:
+
+    ## Subtract the offset of the beginning of the Hcode
+    sub     r31, r3, r7
     nop
-    li r6, 3
-    srw r5,r5,r6
+    srwi    r5,r31,3  ## Divide by 8 for doublewords
 
     ## start copying
-    mtctr r5      
-
+    mtctr   r5
+    nop
     
 payload_copy_loop:
-    lvd d28,0(r8)
-    stvd d28,0(r4)
-    addi r8,r8,8
-    addi r4,r4,8
-    bdnz payload_copy_loop
+    lvd     d28, 0(r8)
+    stvd    d28, 0(r4)
+    addi    r8, r8, 8
+    addi    r4, r4, 8
+    bdnz    payload_copy_loop
 
     ########################
     ## branch to hcode
     ########################
-
-    _liw %r6, SRAM_GPE_HCODE_RESET_ADDR  
-        mtlr r6
+    lis     r31, 0xB00F
+    ori     r31, r31, 0x0004
+    mtsprg0 r31
+
+    ## Load the branch address
+    _liw    %r6, SRAM_GPE_HCODE_RESET_ADDR
+    mtlr    r6
+
+    ## Setup the IVPR for the Hcode
+    _liw    %r9, SRAM_SGPE_BASE_ADDR
+    _liw    %r8, SGPE_IVPR_OCI_ADDR
+    stw     r9, 0(r8)
+    
     blr
 
     .epilogue __bootLoader
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd
index ae182c14..113251ba 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd
@@ -93,12 +93,15 @@ SECTIONS
     // offsets.
 
     _SDA2_BASE_ = .;
-   .sdata2 . : { *(.sdata2) } > sram
-   .sbss2  . : { *(.sbss2) } > sram
+    .sdata2 . : { *(.sdata2) } > sram
+    .sbss2  . : { *(.sbss2) } > sram
 
-   // Other read-only data.
-
-   .rodata . : { *(.rodata*) *(.got2) } > sram
+    // Other read-only data.
+    . = ALIGN(8);
+    .rodata . : { ctor_start_address = .;
+                  *(.ctors) *(.ctors.*)
+                  ctor_end_address = .;
+                  *(rodata*) *(.got2) } > sram
 
     _RODATA_SECTION_SIZE = . - _RODATA_SECTION_BASE;
 
@@ -114,8 +117,10 @@ SECTIONS
     // offsets.
 
     _SDA_BASE_ = .;
-    .sdata  . : { *(.sdata)  } > sram
-    .sbss   . : { *(.sbss)   } > sram
+    .sdata  . : { *(.sdata*)  } > sram
+    _sbss_start = .;
+    .sbss   . : { *(.sbss*)   } > sram
+    _sbss_end = .;
 
     // Other read-write data
     // It's not clear why boot.S is generating empty .glink,.iplt
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_initf.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_initf.C
index b0c53e62..46324f52 100755
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_initf.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_initf.C
@@ -25,12 +25,41 @@
 
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
+#include "hw_access.H"
+#include "p9_ringid_sgpe.H"
+#include <fapi2.H>
 
 extern "C" int p9_hcd_cache_initf(uint32_t quad)
 {
     int rc = SGPE_STOP_SUCCESS;
+    fapi2::Target<fapi2::TARGET_TYPE_EQ> l_eqTarget
+    (
+        fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET)
+    );
+
+    FAPI_DBG("Scanning Cache FUNC Rings");
+    FAPI_INF(">>p9_hcd_cache_initf");
+
+    FAPI_DBG("Scan eq_fure ring");
+    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_fure));
+    FAPI_DBG("Scan eq_ana_func ring");
+    FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_func));
+
+    for (auto l_ex_target : l_eqTarget.getChildren<fapi2::TARGET_TYPE_EX>())
+    {
+        FAPI_DBG("Scan ex_l2_fure ring");
+        FAPI_TRY(fapi2::putRing(l_ex_target, ex_l2_fure));
+        FAPI_DBG("Scan ex_l2_mode ring");
+        FAPI_TRY(fapi2::putRing(l_ex_target, ex_l2_mode));
+        FAPI_DBG("Scan ex_l3_fure ring");
+        FAPI_TRY(fapi2::putRing(l_ex_target, ex_l3_fure));
+        FAPI_DBG("Scan ex_l3_refr_fure ring");
+        FAPI_TRY(fapi2::putRing(l_ex_target, ex_l3_refr_fure));
+    }
 
     // Markers needed for cache ininf
+fapi_try_exit:
+    FAPI_INF("<<p9_hcd_cache_initf");
 
     return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
index 8bcccf07..d7d0399f 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
@@ -222,9 +222,24 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
             // It is expected to be done during Hcode Image Build
             uint32_t l_hdrToSectionOffset = pCpmrHdrAddr->cmeImgOffset;  // Hcode Offset wrt CPMR Hdr start.
 
-            l_blockCopyLength = pCpmrHdrAddr->cmeImgLength;             // CME Image length
-            l_blockCopyLength += pCpmrHdrAddr->cmeCommonRingLength;     // adding common ring length
-            l_blockCopyLength += pCpmrHdrAddr->cmePstateLength;         // adding Pstate region length
+            if ( pCpmrHdrAddr->cmeImgLength != 0 )
+            {
+                l_blockCopyLength = pCpmrHdrAddr->cmeImgLength;         // CME Image length
+            }
+
+            if (  pCpmrHdrAddr->cmeCommonRingLength != 0 )
+            {
+                l_blockCopyLength = (pCpmrHdrAddr->cmeCommonRingOffset - (pCpmrHdrAddr->cmeImgOffset * 32)) +
+                                    pCpmrHdrAddr->cmeCommonRingLength;     // adding common ring length
+            }
+
+            if (  pCpmrHdrAddr->cmePstateLength != 0 )
+            {
+                l_blockCopyLength = (pCpmrHdrAddr->cmePstateOffset - (pCpmrHdrAddr->cmeImgOffset * 32)) +
+                                    pCpmrHdrAddr->cmePstateLength;         // adding Pstate region length
+            }
+
+            PK_TRACE("Block Copy Length: 0x%08x", l_blockCopyLength);
 
             //rounding off length to CME's read block size i.e. 32 bytes
             l_blockCopyLength = ((l_blockCopyLength + (CME_BLOCK_READ_SIZE - 1 )) / CME_BLOCK_READ_SIZE);
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c
index c4279a2e..54bb8c67 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c
@@ -76,13 +76,12 @@ int main(int narg, char* argv[])
         rewind(pMainImage);
         uint32_t QPMR_SGPE_HCODE_LEN_VAL = 0;
 
-
         // For ekb build it's desired to detect the image type w/o special
         // make rules. Better way?
-        printf("Size is: %d\n", size);
 
         if(size < 1024)
         {
+            printf("                    QPMR size: %d\n", size);
             imageType = QPMR_IMAGE;
             buildDatePos = QPMR_BUILD_DATE_POS;
             buildVerPos  = QPMR_BUILD_VER_POS;
@@ -102,18 +101,16 @@ int main(int narg, char* argv[])
 
         if(imageType == SGPE_IMAGE)
         {
-
+            printf("                    SGPE size: %d\n", size);
             //  populating SGPE Image Header
             //  populating RESET address
             fseek (pMainImage, SGPE_RESET_ADDR_POS, SEEK_SET);
             temp = SGPE_RESET_ADDRESS;
             temp = htonl(temp);
             fwrite(&(temp), sizeof(uint32_t), 1, pMainImage );
-            printf("Done 1\n");
         }
 
-
-        //build date
+        // build date
         fseek( pMainImage, buildDatePos, SEEK_SET );
         // date format same as in XIP Header YYYYMMDD
         temp = ((headerTime->tm_mday ) |
@@ -127,7 +124,6 @@ int main(int narg, char* argv[])
         fseek( pMainImage,  buildVerPos, SEEK_SET );
         temp = htonl(SGPE_BUILD_VER);
         fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
-        printf("Done 2");
 
         if (imageType == QPMR_IMAGE)
         {
@@ -144,7 +140,6 @@ int main(int narg, char* argv[])
             fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
         }
 
-        printf("Done 3");
         fclose(pMainImage);
         //fclose(pDependImage);
     }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C
new file mode 100644
index 00000000..99c41db5
--- /dev/null
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C
@@ -0,0 +1,185 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#include "p9_sgpe_stop.h"
+#include <fapi2.H>
+
+EXTERNAL_IRQ_TABLE_START
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_DEBUGGER
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_TRACE_TRIGGER
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_OCC_ERROR
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PBA_ERROR
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_SRT_ERROR
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_GPE0_HALT
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_GPE1_HALT
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_GPE2_HALT
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_GPE3_HALT
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PPC405_HALT
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_OCB_ERROR
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_SPIPSS_ERROR
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_CHECK_STOP_PPC405
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_CHECK_STOP_GPE0
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_CHECK_STOP_GPE1
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_CHECK_STOP_GPE2
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_CHECK_STOP_GPE3
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_OCC_MALF_ALERT
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_ADU_MALF_ALERT
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_EXTERNAL_TRAP
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IVRM_PVREF_ERROR
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_OCC_TIMER0
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_OCC_TIMER1
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_AVS_SLAVE0
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_AVS_SLAVE1
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IPI0_HI_PRIORITY
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IPI1_HI_PRIORITY
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IPI2_HI_PRIORITY
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IPI3_HI_PRIORITY
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IPI4_HI_PRIORITY
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_ADCFSM_ONGOING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_RESERVED_31
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PBAX_OCC_SEND
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PBAX_OCC_PUSH0
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PBAX_OCC_PUSH1
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PBA_BCDE_ATTN
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PBA_BCUE_ATTN
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM0_PULL
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM0_PUSH
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM1_PULL
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM1_PUSH
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM2_PULL
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM2_PUSH
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM3_PULL
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM3_PUSH
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE0_PENDING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE1_PENDING
+IRQ_HANDLER(p9_sgpe_stop_pig_handler, 0)
+//IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING
+IRQ_HANDLER(p9_sgpe_stop_pig_handler, 0)
+//IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE4_PENDING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING
+IRQ_HANDLER(p9_sgpe_stop_pig_handler, 0)
+//IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE6_PENDING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE7_PENDING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_O2S_0A_ONGOING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_O2S_0B_ONGOING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_O2S_1A_ONGOING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_O2S_1B_ONGOING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PSSBRIDGE_ONGOING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IPI0_LO_PRIORITY
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IPI1_LO_PRIORITY
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IPI2_LO_PRIORITY
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IPI3_LO_PRIORITY
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_IPI4_LO_PRIORITY
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_RESERVED_63
+EXTERNAL_IRQ_TABLE_END
+
+#define  KERNEL_STACK_SIZE  512
+#define  THREAD_STACK_SIZE  512
+
+#define  SGPE_THREAD_PRIORITY_STOP_EXIT   1
+#define  SGPE_THREAD_PRIORITY_STOP_ENTRY  2
+
+uint8_t  G_kernel_stack[KERNEL_STACK_SIZE];
+
+uint8_t  G_p9_sgpe_stop_enter_thread_stack[THREAD_STACK_SIZE];
+uint8_t  G_p9_sgpe_stop_exit_thread_stack[THREAD_STACK_SIZE];
+
+PkThread G_p9_sgpe_stop_enter_thread;
+PkThread G_p9_sgpe_stop_exit_thread;
+
+extern void (*ctor_start_address)() __attribute__ ((section (".rodata")));
+extern void (*ctor_end_address)() __attribute__ ((section (".rodata")));
+
+extern uint64_t _sbss_start __attribute__ ((section (".sbss")));
+extern uint64_t _sbss_end __attribute__ ((section (".sbss")));
+
+extern "C" {
+    void __eabi()
+    {
+
+        // Call global constructors
+        void(**ctors)() = &ctor_start_address;
+
+        while( ctors != &ctor_end_address)
+        {
+            (*ctors)();
+            ctors++;
+        }
+    }
+} // end extern "C"
+
+int
+main(int argc, char** argv)
+{
+    // Initializes kernel data (stack, threads, timebase, timers, etc.)
+    pk_initialize((PkAddress)G_kernel_stack,
+                  KERNEL_STACK_SIZE,
+                  0,
+                  PPE_TIMEBASE_HZ);
+
+    fapi2::ReturnCode fapiRc = fapi2::plat_TargetsInit();
+
+    if( fapiRc != fapi2::FAPI2_RC_SUCCESS )
+    {
+        PK_PANIC(PK_UNUSED_0d1f);  // @todo RTC XXXXXX for correct panic codes
+    }
+
+    // Initialize the thread control block for G_p9_sgpe_stop_enter_thread
+    pk_thread_create(&G_p9_sgpe_stop_enter_thread,
+                     (PkThreadRoutine)p9_sgpe_stop_enter_thread,
+                     (void*)NULL,
+                     (PkAddress)G_p9_sgpe_stop_enter_thread_stack,
+                     (size_t)THREAD_STACK_SIZE,
+                     (PkThreadPriority)SGPE_THREAD_PRIORITY_STOP_ENTRY);
+
+    PK_TRACE_BIN("G_p9_sgpe_stop_enter_thread",
+                 &G_p9_sgpe_stop_enter_thread,
+                 sizeof(G_p9_sgpe_stop_enter_thread));
+
+    // Initialize the thread control block for G_p9_sgpe_stop_exit_thread
+    pk_thread_create(&G_p9_sgpe_stop_exit_thread,
+                     (PkThreadRoutine)p9_sgpe_stop_exit_thread,
+                     (void*)NULL,
+                     (PkAddress)G_p9_sgpe_stop_exit_thread_stack,
+                     (size_t)THREAD_STACK_SIZE,
+                     (PkThreadPriority)SGPE_THREAD_PRIORITY_STOP_EXIT);
+
+    PK_TRACE_BIN("G_p9_sgpe_stop_exit_thread",
+                 &G_p9_sgpe_stop_exit_thread,
+                 sizeof(G_p9_sgpe_stop_exit_thread));
+
+    // Make G_p9_sgpe_stop_enter_thread runnable
+    pk_thread_resume(&G_p9_sgpe_stop_enter_thread);
+
+    // Make G_p9_sgpe_stop_exit_thread runnable
+    pk_thread_resume(&G_p9_sgpe_stop_exit_thread);
+
+    // Start running the highest priority thread.
+    // This function never returns
+    pk_start_threads();
+
+    return 0;
+}
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index 80dcfe9d..820f5de8 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -27,6 +27,10 @@
 /// \brief header of p9_cme_stop_enter_thread.c and p9_cme_stop_exit.c
 ///
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #include "pk.h"
 #include "ppe42.h"
 #include "ppe42_scom.h"
@@ -205,6 +209,7 @@ typedef struct
     PkSemaphore  sem[2];
 } SgpeStopRecord;
 
+
 /// SGPE STOP Entry and Exit Prototypes
 void p9_sgpe_stop_pig_handler(void*, PkIrqId);
 void p9_sgpe_stop_enter_thread(void*);
@@ -226,3 +231,7 @@ int  p9_hcd_cache_scominit(uint32_t);
 int  p9_hcd_cache_scomcust(uint32_t);
 int  p9_hcd_cache_ras_runtime_scom(uint32_t);
 int  p9_hcd_cache_occ_runtime_scom(uint32_t);
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h
index beaacbf5..17a2a82e 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h
@@ -34,12 +34,21 @@
 /// \brief Application specific overrides go here.
 ///
 
+#define SIMICS_TUNING 0
+#define USE_SIMICS_IO 0
+#define DEV_DEBUG     1
+
+#ifndef EPM_P9_TUNING
+    #define EPM_P9_TUNING 0
+#endif
+
 #define STOP_PRIME           0
 #define SKIP_L3_PURGE        0
 #define SKIP_L3_PURGE_ABORT  0
-#define ISTEP15_HACK         1
+#define ISTEP15_HACK         0
 
-#if !ISTEP15_HACK
+
+#if EPM_P9_TUNING
     #define SKIP_CME_BOOT_STOP11 1
     #define SKIP_CME_BOOT_IPL_HB 1
     #define SKIP_ARRAYINIT       1
@@ -50,14 +59,10 @@
     #define SKIP_ARRAYINIT       0
     #define SKIP_SCAN0           0
 #endif
-#define SKIP_INITF           0
+#define SKIP_INITF               0
 
 // --------------------
 
-#define EPM_P9_TUNING 1
-#define SIMICS_TUNING 0
-#define USE_SIMICS_IO 0
-#define DEV_DEBUG     1
 
 #if EPM_P9_TUNING
     #define PK_TRACE_BUFFER_WRAP_MARKER 1
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
index a7fd4919..30ac8113 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
@@ -108,6 +108,7 @@ $(IMAGE)_COMMONFLAGS+= -D__PK__=1
 $(IMAGE)_COMMONFLAGS+= -D__PPE_PLAT
 $(IMAGE)_COMMONFLAGS+= -D__PPE__
 $(IMAGE)_COMMONFLAGS+= -DFAPI2_NO_FFDC=1
+##$(IMAGE)_COMMONFLAGS+= -DFAPI_TRACE_LEVEL_DEF=3
 $($(IMAGE)_TARGET)_CXXFLAGS += -Wno-unused-label
 
 # add include paths
@@ -131,7 +132,8 @@ $(call ADD_PPEIMAGE_INCDIR,$(IMAGE),\
 	$(STD_INC) \
 	)
 
-$(IMAGE)_LDFLAGS=-e __system_reset -N -gc-sections -Bstatic
+#$(IMAGE)_LDFLAGS=-e __system_reset -N -gc-sections -Bstatic
+$(IMAGE)_LDFLAGS=-e __system_reset -N -Bstatic
 
 $(call BUILD_PPEIMAGE)
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk
index a50c85f4..621e1842 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk
@@ -22,8 +22,7 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-TOP-C-SOURCES = p9_sgpe_main.c \
-                p9_sgpe_stop_entry.c \
+TOP-C-SOURCES = p9_sgpe_stop_entry.c \
                 p9_sgpe_stop_exit.c \
                 p9_sgpe_stop_irq_handlers.c \
                 p9_sgpe_stop_enter_thread.c \
@@ -44,11 +43,13 @@ TOP-C-SOURCES = p9_sgpe_main.c \
                 p9_hcd_cache_ras_runtime_scom.c \
                 p9_hcd_sgpe_boot_cme.c
 
-UTILS-SRC  = utils/p9_putringutils.C \
-				   utils/plat_ring_traverse.C
+UTILS-SRC   = utils/p9_putringutils.C
+UTILS-SRC  += utils/plat_ring_traverse.C
 
 TOP-S-SOURCES =  p9_sgpe_image_header.S
-TOP-SRC = p9_hcd_cache_initf.C
+
+TOP-CPP-SOURCES  = p9_sgpe_main.C
+TOP-CPP-SOURCES += p9_hcd_cache_initf.C
 
 UTILS_OBJECTS  = $(UTILS-SRC:.C=.o)
-TOP_OBJECTS = $(TOP-C-SOURCES:.c=.o) $(TOP-S-SOURCES:.S=.o) $(TOP-SRC:.C=.o)
+TOP_OBJECTS = $(TOP-C-SOURCES:.c=.o) $(TOP-S-SOURCES:.S=.o) $(TOP-CPP-SOURCES:.C=.o)
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C
index f8438f36..81095581 100755
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C
@@ -88,7 +88,7 @@ uint64_t rs4_get_verbatim(const uint8_t* i_rs4Str,
 
     for(uint8_t i = 1; i <= i_nibbleCount; i++, l_index++)
     {
-        l_byte = i_rs4Str[l_index >> 2];
+        l_byte = i_rs4Str[l_index >> 1];
 
         if(l_index % 2)
         {
@@ -270,7 +270,7 @@ fapi2::ReturnCode standardScan(
 
                     // @TODO: 1 micro second is a number that works now.
                     //        Need to derive the real delay number.
-                    fapi2::delay(1000, 0);
+                    fapi2::delay(1000, 1000000);
 
                 }
 
@@ -337,6 +337,7 @@ fapi2::ReturnCode verifyHeader(const fapi2::Target<fapi2::TARGET_TYPE_ALL>&
             FAPI_ERR("Read header(%016x) data incorrect", uint64_t(l_readHeader));
             l_rc = fapi2::FAPI2_RC_PLAT_ERR_RING_HEADER_CHECK;
             break;
+            //PK_PANIC(0xFABD);
         }
     }
     while(0);
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C
index 3af70a85..e05289d3 100755
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C
@@ -47,6 +47,7 @@ fapi2::ReturnCode findRS4InImageAndApply(
 
     do
     {
+        FAPI_INF("findRS4InImageAndApply i_ringID %d", i_ringID);
         // Determine the Offset ID and Ring Type for the given Ring ID.
         uint32_t l_torOffset = 0;
         RINGTYPE l_ringType = COMMON_RING;
@@ -63,20 +64,29 @@ fapi2::ReturnCode findRS4InImageAndApply(
 
         l_chipletData = g_eqData;
 
+        if( l_hcodeLayout->g_sgpe_cmn_ring_occ_offset == 0)
+        {
+            FAPI_INF("No data COMMON ring section");
+            break;
+        }
+
         uint32_t l_chipletID = i_target.getChipletNumber();
         // Determine the section TOR address for the ring
         uint32_t* l_sectionAddr =
-            (uint32_t*)(SGPE_SRAM_BASE + SGPE_IMAGE_HEADER_OFFSET +
-                        l_hcodeLayout->g_sgpe_cmn_ring_occ_offset);
+            (uint32_t*)(SGPE_SRAM_BASE + l_hcodeLayout->g_sgpe_cmn_ring_occ_offset);
 
         if(INSTANCE_RING == l_ringType)
         {
+            if (l_hcodeLayout->g_sgpe_spec_ring_occ_offset == 0)
+            {
+                FAPI_INF("No data in Instance spec ring section");
+            }
+
             l_sectionAddr =
-                (uint32_t*)(SGPE_SRAM_BASE + SGPE_IMAGE_HEADER_OFFSET +
-                            l_hcodeLayout->g_sgpe_spec_ring_occ_offset);
+                (uint32_t*)(SGPE_SRAM_BASE + l_hcodeLayout->g_sgpe_spec_ring_occ_offset);
 
             l_sectionAddr += ((l_chipletID -
-                               l_chipletData.iv_base_chiplet_number) * l_chipletData.iv_num_variants);
+                               l_chipletData.iv_base_chiplet_number) * l_chipletData.iv_num_instance_rings);
         }
 
         // TOR records of Ring TOR are 2 bytes in size.
@@ -87,8 +97,13 @@ fapi2::ReturnCode findRS4InImageAndApply(
         {
             uint8_t* l_addr = (uint8_t*)(l_sectionAddr);
             uint8_t* l_rs4Address = (uint8_t*)(l_addr + *l_ringTorAddr);
+            FAPI_INF("l_rs4Address %08x", l_rs4Address);
             l_rc = rs4DecompressionSvc(i_target, l_rs4Address);
         }
+        else
+        {
+            FAPI_INF("No data for this ringId %d", i_ringID);
+        }
     }
     while(0);