PM Recv FFDC: Base changes for PPE State and OCC Plat

Change to
1. enable collection of PPE XIRS, SPRs, GPRs to respective
2. create and collect OCC plat traces for OCC, GPE0/1 & Shared

to respective regions in HOMER PM FFDC sections

Change-Id: I4ee1314450b72818e4b3ba44558e1359a1a2df08
RTC: 180382
RTC: 180553
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47120
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

2 files changed, 33 insertions, 4 deletions

diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index e470f728..678724f9 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -543,14 +543,13 @@ HCD_CONST(PGPE_IMAGE_RESERVE_SIZE,
 HCD_CONST(FFDC_CME_MAGIC_NUM,         (0x434d455f)) //"CME_"
 HCD_CONST(FFDC_SGPE_MAGIC_NUM,        (0x53475045)) //"SGPE"
 HCD_CONST(FFDC_PGPE_MAGIC_NUM,        (0x50475045)) //"PGPE"
+HCD_CONST(FFDC_OCC_MAGIC_NUM,         (0x4f43435f)) //"OCC_"
 
 //FFDC Region Layout
 HCD_CONST(FFDC_PPE_SCORE_BOARD_SIZE,    0x200)
 HCD_CONST(FFDC_PPE_IMG_HDR_SIZE,        0x80)
 HCD_CONST(FFDC_PPE_XIR_SIZE,            0x28)
 HCD_CONST(FFDC_PPE_SPR_SIZE,            0x80)
-HCD_CONST(FFDC_PPE_MAJOR_SPR_SIZE,      0x38)
-HCD_CONST(FFDC_PPE_MINOR_SPR_SIZE,      0x38)
 HCD_CONST(FFDC_PPE_GPR_SIZE,            0x80)
 HCD_CONST(FFDC_PPE_INTERNAL_REG_SIZE,   0x78)
 HCD_CONST(FFDC_PPE_TRACES_SIZE,         0x200)
@@ -563,8 +562,7 @@ HCD_CONST(FFDC_HOMER_TOP_HEADER ,       0x38)
 HCD_CONST(FFDC_QUAD_REGION_SIZE,        0x10E8)
 HCD_CONST(FFDC_SGPE_REGION_SIZE,        (FFDC_PPE_BLOCK_SIZE))
 HCD_CONST(FFDC_PGPE_REGION_SIZE,        (FFDC_PPE_BLOCK_SIZE))
-HCD_CONST(FFDC_OCC_REGION_SIZE,         0x8610)
-HCD_CONST(FFDC_OCC_REGION_HDR_SIZE,     0x10)
+HCD_CONST(FFDC_OCC_REGION_HDR_SIZE,     0x18)
 HCD_CONST(FFDC_TRACE_ERR_SIZE,          (8 * ONE_KB))
 HCD_CONST(FFDC_TRACE_IMP_SIZE,          (FFDC_TRACE_ERR_SIZE))
 HCD_CONST(FFDC_TRACE_INF_SIZE,          (FFDC_TRACE_ERR_SIZE))
@@ -572,6 +570,16 @@ HCD_CONST(FFDC_TRACE_SSX_SIZE ,         (FFDC_TRACE_ERR_SIZE))
 HCD_CONST(FFDC_TRACE_GPE0_SIZE,         0x200)
 HCD_CONST(FFDC_TRACE_GPE1_SIZE,         0x200)
 HCD_CONST(FFDC_SHARED_SRAM_SIZE,        0x200)
+HCD_CONST(FFDC_OCC_REGS_SIZE,           0x580)
+HCD_CONST(FFDC_OCC_REGION_SIZE,         (FFDC_OCC_REGION_HDR_SIZE +
+          FFDC_TRACE_ERR_SIZE +
+          FFDC_TRACE_IMP_SIZE +
+          FFDC_TRACE_INF_SIZE +
+          FFDC_TRACE_SSX_SIZE +
+          FFDC_TRACE_GPE0_SIZE +
+          FFDC_TRACE_GPE1_SIZE +
+          FFDC_SHARED_SRAM_SIZE +
+          FFDC_OCC_REGS_SIZE))
 HCD_CONST(FFDC_REGION_QPMR_BASE_OFFSET, 0xE0000)
 HCD_CONST(FFDC_REGION_HOMER_BASE_OFFSET,
           (QPMR_HOMER_OFFSET + FFDC_REGION_QPMR_BASE_OFFSET))
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
index 0bc24aa2..287ac99b 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
@@ -48,6 +48,27 @@
 /// OCC SRAM
 
 HCD_CONST(OCC_SRAM_BASE_ADDR,                   0xFFF00000)
+HCD_CONST(GPE0_SRAM_BASE_ADDR,                  0xFFF01000)
+HCD_CONST(GPE1_SRAM_BASE_ADDR,                  0xFFF10000)
+
+/// Base Addresses for various traces regions in OCC SRAM
+HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SSX_PTR,      0xFFF40824)
+HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_ERR,          0xFFFB4000)
+HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_INF,          0xFFFB6000)
+HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_IMP,          0xFFFB8000)
+// @TODO: HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SHARED,    0x0)
+HCD_CONST(GPE0_SRAM_TRACE_BUF_PTR,              GPE0_SRAM_BASE_ADDR + 0x184)
+HCD_CONST(GPE1_SRAM_TRACE_BUF_PTR,              GPE1_SRAM_BASE_ADDR + 0x184)
+
+// Size of various traces regions in OCC SRAM
+HCD_CONST(OCC_SRAM_TRACE_BUF_SSX_SIZE_PTR,      0xFFF40828)
+HCD_CONST(OCC_SRAM_TRACE_BUF_ERR_SIZE,          (8 * ONE_KB))
+HCD_CONST(OCC_SRAM_TRACE_BUF_INF_SIZE,          (8 * ONE_KB))
+HCD_CONST(OCC_SRAM_TRACE_BUF_IMP_SIZE,          (8 * ONE_KB))
+// @TODO: HCD_CONST(OCC_SRAM_TRACE_BUF_SHARED_SIZE, )
+HCD_CONST(GPE0_SRAM_TRACE_BUF_SIZE_PTR,         (GPE0_SRAM_BASE_ADDR + 0x188))
+HCD_CONST(GPE1_SRAM_TRACE_BUF_SIZE_PTR,         (GPE1_SRAM_BASE_ADDR + 0x188))
+
 HCD_CONST(OCC_SRAM_IPC_REGION_SIZE,             (4 * ONE_KB))
 HCD_CONST(OCC_SRAM_GPE0_REGION_SIZE,            (60 * ONE_KB))
 HCD_CONST(OCC_SRAM_GPE1_REGION_SIZE,            (64 * ONE_KB))