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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2017-09-20 08:43:22 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 19:32:44 -0500 |
| commit | d619f26c683c0f52e3d75512effd2fa4aff1aff5 (patch) | |
| tree | 89e89d387ba35548048b3dc5e2f1d10ea5f500df | |
| parent | 8a6431ef786bc3d1de6c014e190f9c624aebec69 (diff) | |
| download | talos-hcode-d619f26c683c0f52e3d75512effd2fa4aff1aff5.tar.gz talos-hcode-d619f26c683c0f52e3d75512effd2fa4aff1aff5.zip | |
STOP Recovery: Added support for FFDC collection of CME and SGPE.
Change-Id: Ie0ac19b81a44a72faedc860ea2337acc8e20c321
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46853
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
3 files changed, 46 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 6ed8f5eb..e470f728 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -67,6 +67,7 @@ HCD_CONST64(SGPE_MAGIC_NUMBER_BASE, ULL(0x534750455f302e30)) / HCD_CONST64(PPMR_MAGIC_NUMBER_BASE, ULL(0x50504d525f302e30)) // PPMR_0.0 HCD_CONST64(PGPE_MAGIC_NUMBER_BASE, ULL(0x504750455F302E30)) // PGPE_0.0 + /// Size constants HCD_CONST(HALF_KB, 512) @@ -538,4 +539,41 @@ HCD_CONST(WOF_TABLE_RESERVE, HCD_CONST(PGPE_IMAGE_RESERVE_SIZE, (OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET - PGPE_IMAGE_PPMR_OFFSET - PGPE_IMAGE_SIZE - PGPE_AUX_TASK_SIZE)) +//FFDC Magic Words +HCD_CONST(FFDC_CME_MAGIC_NUM, (0x434d455f)) //"CME_" +HCD_CONST(FFDC_SGPE_MAGIC_NUM, (0x53475045)) //"SGPE" +HCD_CONST(FFDC_PGPE_MAGIC_NUM, (0x50475045)) //"PGPE" + +//FFDC Region Layout +HCD_CONST(FFDC_PPE_SCORE_BOARD_SIZE, 0x200) +HCD_CONST(FFDC_PPE_IMG_HDR_SIZE, 0x80) +HCD_CONST(FFDC_PPE_XIR_SIZE, 0x28) +HCD_CONST(FFDC_PPE_SPR_SIZE, 0x80) +HCD_CONST(FFDC_PPE_MAJOR_SPR_SIZE, 0x38) +HCD_CONST(FFDC_PPE_MINOR_SPR_SIZE, 0x38) +HCD_CONST(FFDC_PPE_GPR_SIZE, 0x80) +HCD_CONST(FFDC_PPE_INTERNAL_REG_SIZE, 0x78) +HCD_CONST(FFDC_PPE_TRACES_SIZE, 0x200) +HCD_CONST(FFDC_PPE_HDR_SIZE , 0x18) +HCD_CONST(FFDC_QUAD_HDR_SIZE , 0x18) +HCD_CONST(FFDC_CPPM_REGISTERS_SIZE, 0x380) +HCD_CONST(FFDC_PPE_BLOCK_SIZE, 0x630) +HCD_CONST(FFDC_QPPM_REGISTERS_SIZE, 0xE8) +HCD_CONST(FFDC_HOMER_TOP_HEADER , 0x38) +HCD_CONST(FFDC_QUAD_REGION_SIZE, 0x10E8) +HCD_CONST(FFDC_SGPE_REGION_SIZE, (FFDC_PPE_BLOCK_SIZE)) +HCD_CONST(FFDC_PGPE_REGION_SIZE, (FFDC_PPE_BLOCK_SIZE)) +HCD_CONST(FFDC_OCC_REGION_SIZE, 0x8610) +HCD_CONST(FFDC_OCC_REGION_HDR_SIZE, 0x10) +HCD_CONST(FFDC_TRACE_ERR_SIZE, (8 * ONE_KB)) +HCD_CONST(FFDC_TRACE_IMP_SIZE, (FFDC_TRACE_ERR_SIZE)) +HCD_CONST(FFDC_TRACE_INF_SIZE, (FFDC_TRACE_ERR_SIZE)) +HCD_CONST(FFDC_TRACE_SSX_SIZE , (FFDC_TRACE_ERR_SIZE)) +HCD_CONST(FFDC_TRACE_GPE0_SIZE, 0x200) +HCD_CONST(FFDC_TRACE_GPE1_SIZE, 0x200) +HCD_CONST(FFDC_SHARED_SRAM_SIZE, 0x200) +HCD_CONST(FFDC_REGION_QPMR_BASE_OFFSET, 0xE0000) +HCD_CONST(FFDC_REGION_HOMER_BASE_OFFSET, + (QPMR_HOMER_OFFSET + FFDC_REGION_QPMR_BASE_OFFSET)) + #endif /* __HCD_MEMMAP_BASE_H__ */ diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H index 2e4bd09e..8f49172a 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H @@ -46,7 +46,10 @@ // ------------------------------------------------------------------- HCD_CONST(CME_SRAM_BASE_ADDR, 0xFFFF8000) +HCD_CONST(FFDC_PPE_IMG_HDR_START, (CME_INT_VECTOR_SIZE + CME_SRAM_BASE_ADDR)) HCD_CONST(CME_SRAM_HEADER_ADDR, (CME_SRAM_BASE_ADDR + CME_INT_VECTOR_SIZE)) +HCD_CONST(FFDC_CME_TRACE_START, (CME_SRAM_BASE_ADDR + CME_DEBUG_PTRS_OFFSET)) +HCD_CONST(FFDC_CME_DASH_BOARD_START, (FFDC_CME_TRACE_START + CME_DEBUG_PTRS_SIZE - 4 )) #endif /* __P9_HCD_MEMMAP_CME_SRAM_H__ */ diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H index fa9c539f..0bc24aa2 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H @@ -161,5 +161,10 @@ HCD_CONST(OCC_SRAM_QUAD_SPECIFIC_RINGS_LENGTH_ADDR, (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_QUAD_SPECIFIC_RINGS_LENGTH_BYTE)) +HCD_CONST(OCC_SRAM_SGPE_DASHBOARD_START, + ( OCC_SRAM_SGPE_HEADER_ADDR + SGPE_HEADER_SIZE + SGPE_DEBUG_PTRS_SIZE - 4 )); // For 8B alignment +HCD_CONST( OCC_SRAM_SGPE_DASHBOARD_SIZE, 0x134 ); +HCD_CONST( OCC_SRAM_SGPE_TRACE_START, + (OCC_SRAM_SGPE_HEADER_ADDR + SGPE_HEADER_SIZE)); #endif /* __P9_HCD_MEMMAP_OCC_SRAM_H__ */ |
