diff options
| author | Yue Du <daviddu@us.ibm.com> | 2017-03-15 12:53:46 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:19:06 -0500 |
| commit | b4d4d410ad596059fccd45cf79d4bfa3f4d0f974 (patch) | |
| tree | 3b208c2721836da03aae9be29d333e0141551949 | |
| parent | 455c286759455f04a77ec8847674fb676daa88b3 (diff) | |
| download | talos-hcode-b4d4d410ad596059fccd45cf79d4bfa3f4d0f974.tar.gz talos-hcode-b4d4d410ad596059fccd45cf79d4bfa3f4d0f974.zip | |
STOP: Recent Lab Fixes
1) fix pig type3 for stop8+
2) clean up the lpid fix traces
3) fix clean spwu after switch notify
4) clean up cme entry INF traces
5) clean up cme exit INF traces
6) fix halt cme before pb purge
7) clean up sgpe INF traces
8) fix phantom wakeup on wakeup_notify=0
9) fix epm_tunning compile
10)fix read OISR once on type2/3/6 status
Change-Id: I06838f24cf2f788825ee25621cc7336001cfd80a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37984
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
9 files changed, 223 insertions, 253 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index aa91de4b..4aaf008c 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -115,7 +115,7 @@ uint16_t ram_read_lpid( uint32_t core, uint32_t thread ) if (scom_data > 0xFFF ) { - PKTRACE("RAMMING ERROR Unexpected LPID core %d : 0x%lX 0xFFF", core, scom_data); + PK_TRACE("RAMMING ERROR Unexpected LPID core %d : 0x%lX 0xFFF", core, scom_data); PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } @@ -288,7 +288,7 @@ p9_cme_stop_entry() #endif // tlbie stop workaround //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- // First we need to determine which of the two STOP interrupts fired. @@ -416,7 +416,7 @@ p9_cme_stop_entry() #if HW386841_DD1_DSL_STOP1_FIX //---------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 1 ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 1 ENTRY +++++ +++++"); //---------------------------------------------------------------------- PK_TRACE("Pulse STOP entry acknowledgement to PC via SICR[0/1]"); @@ -447,7 +447,7 @@ p9_cme_stop_entry() } //---------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++"); //---------------------------------------------------------------------- p9_cme_acquire_pcbmux(core, 1); @@ -480,14 +480,16 @@ p9_cme_stop_entry() PK_TRACE("Update STOP history: in transition of entry"); // Set req_level_level to target_level of either both or just one core scom_data.words.lower = 0; - scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | (target_level << SHIFT32(7))); + scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | + (((uint32_t)target_level) << SHIFT32(7))); CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); // Set req_level_level to deeper_level for deeper core if (deeper_core) { scom_data.words.lower = 0; - scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | (deeper_level << SHIFT32(7))); + scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | + (((uint32_t)deeper_level) << SHIFT32(7))); CME_PUTSCOM(PPM_SSHSRC, deeper_core, scom_data.value); } @@ -504,13 +506,13 @@ p9_cme_stop_entry() if (core & CME_MASK_C0) { lpid_c0[thread] = ram_read_lpid(CME_MASK_C0, thread); - PKTRACE("c0lpid %X thread %X", (uint32_t) lpid_c0[thread], thread); + PK_TRACE("c0lpid %X thread %X", (uint32_t) lpid_c0[thread], thread); } if (core & CME_MASK_C1) { lpid_c1[thread] = ram_read_lpid(CME_MASK_C1, thread); - PKTRACE("c1lpid %X thread %X", (uint32_t) lpid_c1[thread], thread); + PK_TRACE("c1lpid %X thread %X", (uint32_t) lpid_c1[thread], thread); } } @@ -524,8 +526,8 @@ p9_cme_stop_entry() if (ram_read_lpid(CME_MASK_C0, thread) != POWMAN_RESERVED_LPID) { - PKTRACE("READ LPID not equal to expected value"); - asm("trap"); + PK_TRACE("READ LPID not equal to expected value"); + PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } #endif @@ -539,8 +541,8 @@ p9_cme_stop_entry() if (ram_read_lpid(CME_MASK_C1, thread) != POWMAN_RESERVED_LPID) { - PKTRACE("READ LPID not equal to expected value"); - asm("trap"); + PK_TRACE("READ LPID not equal to expected value"); + PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } #endif @@ -552,6 +554,8 @@ p9_cme_stop_entry() #endif // tlbie stop workaround + PK_TRACE_INF("SE.2A: Core[%d] PCB Mux Granted", core); + //============================= MARK_TRAP(SE_QUIESCE_CORE_INTF) //============================= @@ -579,7 +583,7 @@ p9_cme_stop_entry() // MF: verify generate FCB otherwise math is wrong. PPE_WAIT_CORE_CYCLES(512) - PK_TRACE_INF("SE2.B: Interfaces Quiesced"); + PK_TRACE_INF("SE.2B: Interfaces Quiesced"); #if HW402407_NDD1_TLBIE_STOP_WORKAROUND @@ -609,8 +613,8 @@ p9_cme_stop_entry() { if (ram_read_lpid(CME_MASK_C0, thread) != lpid_c0[thread]) { - PKTRACE("READ LPID not equal to expected value"); - asm("trap"); + PK_TRACE("READ LPID not equal to expected value"); + PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } } @@ -618,8 +622,8 @@ p9_cme_stop_entry() { if (ram_read_lpid(CME_MASK_C1, thread) != lpid_c1[thread]) { - PKTRACE("READ LPID not equal to expected value"); - asm("trap"); + PK_TRACE("READ LPID not equal to expected value"); + PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } } } @@ -693,7 +697,7 @@ p9_cme_stop_entry() // MF: verify compiler generate single rlwmni // MF: delay may be needed for stage latch to propagate thold - PK_TRACE_INF("SE2.C: Core Clock Stopped"); + PK_TRACE_INF("SE.2C: Core Clock Stopped"); //============================== MARK_TRAP(SE_STOP_CORE_GRID) @@ -750,7 +754,7 @@ p9_cme_stop_entry() G_cme_stop_record.act_level[1] = STOP_LEVEL_2; } - PK_TRACE_INF("SE2.D: Clock Sync Dropped"); + PK_TRACE_INF("SE.2D: Clock Sync Dropped"); //=========================== MARK_TAG(SE_STOP2_DONE, core) @@ -763,7 +767,8 @@ p9_cme_stop_entry() STOP_TRANS_COMPLETE : STOP_TRANS_ENTRY; scom_data.words.lower = 0; - scom_data.words.upper = (SSH_ACT_LV2_COMPLETE | (entry_ongoing << SHIFT32(3))); + scom_data.words.upper = (SSH_ACT_LV2_COMPLETE | + (((uint32_t)entry_ongoing) << SHIFT32(3))); CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); // If both cores targeting different levels @@ -904,7 +909,7 @@ p9_cme_stop_entry() core, deeper_core, target_level, deeper_level); //---------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 3 ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 3 ENTRY +++++ +++++"); //---------------------------------------------------------------------- if (target_level == 3) @@ -970,7 +975,7 @@ p9_cme_stop_entry() } //---------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 4 ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 4 ENTRY +++++ +++++"); //---------------------------------------------------------------------- //=============================== @@ -1022,7 +1027,7 @@ p9_cme_stop_entry() // vdd_pfet_force_state = 00 (Nop) CME_PUTSCOM(PPM_PFCS_CLR, core, BITS64(0, 2)); - PK_TRACE_INF("SE4.A: Core Powered Off"); + PK_TRACE_INF("SE.4A: Core[%d] Powered Off", core); } #endif @@ -1048,7 +1053,8 @@ p9_cme_stop_entry() STOP_TRANS_ENTRY; scom_data.words.lower = 0; - scom_data.words.upper = (SSH_ACT_LV4_COMPLETE | (entry_ongoing << SHIFT32(3))); + scom_data.words.upper = (SSH_ACT_LV4_COMPLETE | + (((uint32_t)entry_ongoing) << SHIFT32(3))); CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); // If both cores targeting different levels @@ -1117,7 +1123,7 @@ p9_cme_stop_entry() core, deeper_core, target_level, deeper_level); //---------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 5-7 ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 5-7 ENTRY +++++ +++++"); //---------------------------------------------------------------------- if ((G_cme_stop_record.req_level[0] >= STOP_LEVEL_8) && @@ -1163,7 +1169,7 @@ p9_cme_stop_entry() MARK_TAG(SE_PURGE_L2_ABORT, core_aborted) //======================================= - PK_TRACE_DBG("Abort: L2+NCU purge aborted by core[%d]", core_aborted); + PK_TRACE_INF("Abort: L2+NCU purge aborted by core[%d]", core_aborted); out32(CME_LCL_SICR_OR, BIT32(19) | BIT32(23)); } } @@ -1176,7 +1182,7 @@ p9_cme_stop_entry() PK_TRACE("Drop L2+NCU purges and their possible aborts via SICR[18,19,22,23]"); out32(CME_LCL_SICR_CLR, (BITS32(18, 2) | BITS32(22, 2))); - PK_TRACE_INF("SE5.A: L2 and NCU Purged"); + PK_TRACE_INF("SE.5A: L2 and NCU Purged"); //=================================================================== MARK_TAG(SE_PURGE_L2_DONE, core_aborted ? core_aborted : CME_MASK_BC) @@ -1220,7 +1226,7 @@ p9_cme_stop_entry() if ((scom_data.words.upper & BIT32(13))) { - PKTRACE("ERROR: C0 notify was already set?"); + PKTRACE("ERROR.A0: C0 notify was already set?"); pk_halt(); } @@ -1232,7 +1238,7 @@ p9_cme_stop_entry() if ((scom_data.words.upper & BIT32(13))) { - PKTRACE("ERROR: C1 notify was already set?"); + PKTRACE("ERROR.A1: C1 notify was already set?"); pk_halt(); } } @@ -1247,7 +1253,7 @@ p9_cme_stop_entry() { core_index = core_mask & 1; - if (G_cme_stop_record.req_level[core_index] < STOP_LEVEL_11) + if (G_cme_stop_record.req_level[core_index] >= STOP_LEVEL_8) { CME_PUTSCOM(CPPM_CPMMR_OR, core_mask, BIT64(10)); pig.fields.req_intr_type = PIG_TYPE3; @@ -1272,6 +1278,9 @@ p9_cme_stop_entry() #endif + PK_TRACE_DBG("Switch Core PPM wakeup to STOP-GPE via CPMMR[13]"); + CME_PUTSCOM(CPPM_CPMMR_OR, core, BIT64(13)); + #if DEBUG_RUNTIME_STATE_CHECK if (core & CME_MASK_C0) @@ -1280,7 +1289,7 @@ p9_cme_stop_entry() if (!(scom_data.words.upper & BIT32(13))) { - PKTRACE("ERROR: C0 notify fail to set"); + PKTRACE("ERROR.B0: C0 notify fail to set"); pk_halt(); } @@ -1292,23 +1301,23 @@ p9_cme_stop_entry() if (!(scom_data.words.upper & BIT32(13))) { - PKTRACE("ERROR: C1 notify fail to set"); + PKTRACE("ERROR.B1: C1 notify fail to set"); pk_halt(); } } #endif - PKTRACE("Switch Core%d PPM wakeup to STOP-GPE via CPMMR[13]", core); - CME_PUTSCOM(CPPM_CPMMR_OR, core, BIT64(13)); + PK_TRACE("Clear special wakeup after wakeup_notify = 1 since it is edge triggered"); + out32(CME_LCL_EISR_CLR, core << SHIFT32(15)); - PK_TRACE_INF("SE5.B: Handed off to SGPE"); + PK_TRACE_INF("SE.5B: Core[%d] Handed off to SGPE", core); } while(0); //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ END OF STOP ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ END OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- //============================ diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index 85d6a724..41a370b4 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -85,7 +85,7 @@ p9_cme_stop_exit_catchup(uint32_t* core, *spwu_stop |= (core_catchup) & (wakeup >> 2); - PK_TRACE_INF("Catch: core[%d] running[%d] \ + PK_TRACE_DBG("Catch: core[%d] running[%d] \ core_catchup[%d] catchup_level[%d]", *core, G_cme_stop_record.core_running, core_catchup, catchup_level); @@ -138,7 +138,7 @@ p9_cme_stop_exit() #endif //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ BEGIN OF STOP EXIT +++++ +++++"); + PK_TRACE("+++++ +++++ BEGIN OF STOP EXIT +++++ +++++"); //-------------------------------------------------------------------------- // extract wakeup signals, clear status, and mask wakeup interrupts @@ -182,12 +182,10 @@ p9_cme_stop_exit() if (spwu_wake) { // Process special wakeup on a core that is already running - PK_TRACE_DBG("Check: Core[%d] pm_exit=1/EISR=0/EIPR=0/spwu_done=1", spwu_wake); + PK_TRACE_INF("SP.WU: Core[%d] Assert PM_EXIT and SPWU_DONE via SICR[4/5, 16/17]", spwu_wake); out32(CME_LCL_SICR_OR, spwu_wake << SHIFT32(5)); // assert pm_exit out32(CME_LCL_EISR_CLR, spwu_wake << SHIFT32(15)); // clear spwu in EISR out32(CME_LCL_EIPR_CLR, spwu_wake << SHIFT32(15)); // flip EIPR to falling edge - - PK_TRACE_INF("SX0.A: Assert SPWU Done on Core via SICR[16/17]"); out32(CME_LCL_SICR_OR, spwu_wake << SHIFT32(17)); // assert spwu_done now G_cme_stop_record.core_in_spwu |= spwu_wake; @@ -224,7 +222,7 @@ p9_cme_stop_exit() } } - PK_TRACE_DBG("SX0.B: Core[%d] Requested Stop1 Exit", core_stop1); + PK_TRACE_INF("SX.1A: Core[%d] Requested Stop1 Exit", core_stop1); core = core & ~core_stop1; @@ -264,9 +262,6 @@ p9_cme_stop_exit() PK_TRACE_DBG("Check: core[%d] target_lv[%d], deeper_lv[%d], deeper_c[%d]", core, target_level, deeper_level, deeper_core); - - - PK_TRACE("Clear chtm purge done via ESIR[24/25]"); out32(CME_LCL_EISR_CLR, (core << SHIFT32(25))); @@ -282,7 +277,7 @@ p9_cme_stop_exit() { //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 4 EXIT +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 4 EXIT +++++ +++++"); //-------------------------------------------------------------------------- // if deeper_core is set, then core must be 0b11 @@ -297,29 +292,29 @@ p9_cme_stop_exit() #if !SKIP_BCE_SCOM_RESTORE - PK_TRACE_INF("SX4.A: BCE Runtime Kickoff to Copy Scom Restore"); + PK_TRACE_DBG("BCE Runtime Kickoff to Copy Scom Restore"); //right now a blocking call. Need to confirm this. instance_scom_restore(); #endif - PK_TRACE_DBG("Check: Core[%d] in Progress of SX4FH", core); // Can't do the read of cplt_stat after flipping the mux before the core is powered on // catchup to stop4 exit will acquire here + PK_TRACE_DBG("Core Acquire Pcb Mux"); p9_cme_acquire_pcbmux(core, 0); //======================== MARK_TAG(SX_POWERON, core) //======================== - PK_TRACE_INF("SX4.B: Core Poweron"); + PK_TRACE_INF("SX.4A: Core[%d] Poweron", core); p9_hcd_core_poweron(core); //========================= MARK_TRAP(SX_CHIPLET_RESET) //========================= - PK_TRACE_INF("SX4.C: Core Chiplet Reset"); + PK_TRACE_INF("SX.4B: Core Chiplet Reset"); p9_hcd_core_chiplet_reset(core); #if !STOP_PRIME @@ -352,19 +347,20 @@ p9_cme_stop_exit() MARK_TAG(SX_CHIPLET_INITS, core) //============================== + #if !SKIP_INITF - PK_TRACE_INF("SX4.D: Core GPTR Time Initf"); + PK_TRACE_INF("SX.4C: Core[%d] Gptr/Time Initf after catchup A", core); p9_hcd_core_gptr_time_initf(core); #endif - PK_TRACE_INF("SX4.E: Core Chiplet Init"); + PK_TRACE_DBG("Core Chiplet Inits"); p9_hcd_core_chiplet_init(core); #if !SKIP_INITF - PK_TRACE_INF("SX4.F: Core Repair Initf"); + PK_TRACE_INF("SX.4D: Core Repair Initf"); p9_hcd_core_repair_initf(core); #endif @@ -400,7 +396,7 @@ p9_cme_stop_exit() #if !SKIP_ARRAYINIT - PK_TRACE_INF("SX4.G: Core Array Init"); + PK_TRACE_INF("SX.4E: Core[%d] Array Init after catchup B", core); p9_hcd_core_arrayinit(core); #endif @@ -411,7 +407,7 @@ p9_cme_stop_exit() #if !SKIP_INITF - PK_TRACE_INF("SX4.H: Core Func Scan"); + PK_TRACE_INF("SX.4F: Core Func Scan"); p9_hcd_core_initf(core); #endif @@ -430,29 +426,24 @@ p9_cme_stop_exit() if (deeper_level == STOP_LEVEL_3 || target_level == STOP_LEVEL_3) { - //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 3 EXIT +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 3 EXIT +++++ +++++"); //-------------------------------------------------------------------------- - PK_TRACE_DBG("Check: Core[%d] Serviced by SX3", core); - //====================== MARK_TAG(SX_STOP3, core) //====================== - //Return to full voltage + PK_TRACE_DBG("SX.3A: Core[%d] Return to Full Voltage", core); //disable ivrm? } //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 2 EXIT +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 2 EXIT +++++ +++++"); //-------------------------------------------------------------------------- - PK_TRACE_INF("Check: Core[%d] Serviced by SX2", core); - //============================ MARK_TAG(SX_STARTCLOCKS, core) //============================ @@ -464,6 +455,7 @@ p9_cme_stop_exit() // do this after assert glsmux so glitch can have time to resolve // catchup to stop2 exit will acquire here + PK_TRACE_DBG("Core Ensure Pcb Mux"); p9_cme_acquire_pcbmux(core, 1); PK_TRACE_INF("SX2.A: Start Core Clock"); @@ -474,17 +466,15 @@ p9_cme_stop_exit() if (target_level < STOP_LEVEL_4) { - PK_TRACE("Drop chiplet fence via NC0INDIR[18]"); - if (deeper_core && deeper_level == STOP_LEVEL_4) { - PK_TRACE_DBG("Dropping fence in core%d with deeper_core%d", + PK_TRACE_DBG("Core[%d] Dropping Chiplet Fence via NC0INDIR[18] with deeper_core[%d]", (CME_MASK_BC - deeper_core), deeper_core); CME_PUTSCOM(CPPM_NC0INDIR_CLR, (CME_MASK_BC - deeper_core), BIT64(18)); } else { - PK_TRACE_DBG("Dropping fence in core%d", core); + PK_TRACE_DBG("Core[%d] Dropping Chiplet Fence via NC0INDIR[18]", core); CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(18)); } } @@ -495,7 +485,7 @@ p9_cme_stop_exit() { //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 4 EXIT CONTINUE +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 4 EXIT CONTINUE +++++ +++++"); //-------------------------------------------------------------------------- if (d2u4_flag) @@ -503,15 +493,13 @@ p9_cme_stop_exit() core = deeper_core; } - PK_TRACE_DBG("Check: Core[%d] Serviced by SX4SH", core); - #if !STOP_PRIME //=========================== MARK_TAG(SX_SCOM_INITS, core) //=========================== - PK_TRACE_INF("SX4.I: Image Hardcoded Scoms on Core", core); + PK_TRACE_INF("SX4.G: Core[%d] Scom Inits", core); p9_hcd_core_scominit(core); //========================== @@ -520,7 +508,7 @@ p9_cme_stop_exit() #if !SKIP_BCE_SCOM_RESTORE - PK_TRACE_INF("SX4.J: BCE Runtime Check Scom Restore Copy Completed"); + PK_TRACE_DBG("BCE Runtime Check Scom Restore Copy Completed"); if( BLOCK_COPY_SUCCESS != isScanRingCopyDone() ) { @@ -530,17 +518,17 @@ p9_cme_stop_exit() #endif - PK_TRACE_INF("SX4.K: XIP Customized Scoms on Core", core); + PK_TRACE("Core XIP Customized Scoms"); p9_hcd_core_scomcust(core); //============================== MARK_TAG(SX_RUNTIME_INITS, core) //============================== - PK_TRACE_INF("SX4.L: RAS Runtime Scom on Core", core); + PK_TRACE("RAS Runtime Scom on Core", core); p9_hcd_core_ras_runtime_scom(core); - PK_TRACE_INF("SX4.M: OCC Runtime Scom on Core", core); + PK_TRACE("OCC Runtime Scom on Core", core); p9_hcd_core_occ_runtime_scom(core); #endif @@ -549,14 +537,12 @@ p9_cme_stop_exit() MARK_TAG(SX_SELF_RESTORE, core) //============================= - PK_TRACE_INF("SX4.N: Core Self Restore"); - #if !SKIP_SELF_RESTORE PK_TRACE("Assert block interrupt to PC via SICR[2/3]"); out32(CME_LCL_SICR_OR, core << SHIFT32(3)); - PK_TRACE("Waking up the core(pm_exit=1) via SICR[4/5]"); + PK_TRACE_INF("SF.RS: Self Restore Prepare, Core Waking up(pm_exit=1) via SICR[4/5]"); out32(CME_LCL_SICR_OR, core << SHIFT32(5)); PK_TRACE("Polling for core wakeup(pm_active=0) via EINR[20/21]"); @@ -569,8 +555,6 @@ p9_cme_stop_exit() #if NIMBUS_DD_LEVEL == 1 #if !SKIP_RAM_HRMOR - PK_TRACE_INF("SX4.O: Core Wakes Up, Ramming HRMOR with HOMER address"); - PK_TRACE("Activate thread0 for RAM via THREAD_INFO[18]"); CME_PUTSCOM(THREAD_INFO, core, BIT64(18)); @@ -587,11 +571,11 @@ p9_cme_stop_exit() PK_TRACE_DBG("Set SPRC to scratch for core[%d] via SCOM_SPRC", core_mask); CME_PUTSCOM(SCOM_SPRC, core_mask, ((core_mask & 1) ? BIT64(60) : 0)); - PK_TRACE_DBG("Load SCRACTH with HOMER+2MB for core[%d]", core_mask); + PK_TRACE_DBG("Load SCRACTH with HOMER+2MB address %x", scom_data.value); #if EPM_P9_TUNING - CME_PUTSCOM((SCRACTH0 + (core_mask & 1)), core_mask, 0x200000); + CME_PUTSCOM((SCRACTH0 + (core_mask & 1)), core_mask, 0xA200000); #else @@ -631,14 +615,14 @@ p9_cme_stop_exit() // Nimbus DD2+ #else - PK_TRACE_INF("SX4.O: Core Wakes Up, Write HRMOR with HOMER address"); #if EPM_P9_TUNING - CME_PUTSCOM(HRMOR, core, 0x200000); + CME_PUTSCOM(HRMOR, core, 0xA200000); #else + PK_TRACE_DBG("Core Wakes Up, Write HRMOR with HOMER address %x", scom_data.value); CME_PUTSCOM(HRMOR, core, scom_data.value); #endif @@ -649,7 +633,7 @@ p9_cme_stop_exit() CME_GETSCOM(SPATTN_MASK, core, CME_SCOM_AND, scom_data.value); CME_PUTSCOM(SPATTN_MASK, core, BITS64(0, 64)); - PK_TRACE_INF("SX4.P: S-Reset All Core Threads to Run Self Restore Image"); + PK_TRACE_INF("SF.RS: Self Restore Kickoff, S-Reset All Core Threads"); CME_PUTSCOM(DIRECT_CONTROLS, core, BIT64(4) | BIT64(12) | BIT64(20) | BIT64(28)); sync(); @@ -677,7 +661,7 @@ p9_cme_stop_exit() } } - PK_TRACE_INF("SX4.Q: Self Restore Completed, Core is Stopped Again"); + PK_TRACE_INF("SF.RS: Self Restore Completed, Core Stopped Again(pm_exit=0/pm_active=1)"); PK_TRACE("Restore SPATTN after self-restore"); CME_PUTSCOM(SPATTN_MASK, core, scom_data.value); @@ -701,22 +685,21 @@ p9_cme_stop_exit() //========================= //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ END OF STOP EXIT +++++ +++++"); + PK_TRACE("+++++ +++++ END OF STOP EXIT +++++ +++++"); //-------------------------------------------------------------------------- + PK_TRACE_DBG("Restore PSSCR.PLS+SRR1 back to actual level"); + #if HW386841_DD1_DSL_STOP1_FIX STOP1_EXIT: core = core | core_stop1; - PK_TRACE_INF("SX0.D: Restore PSSCR.PLS+SRR1 back to actual level"); - for (core_mask = 2; core_mask; core_mask--) { if (core & core_mask) { - PK_TRACE_DBG("Set PLS+SRR1 for Core[%d]", core_mask); CME_GETSCOM(PPM_SSHSRC, core_mask, CME_SCOM_AND, scom_data.value); core_index = core_mask & 1; @@ -731,7 +714,7 @@ STOP1_EXIT: // address are 0x20 apart between threads and 0x80 apart between cores pscrs = in32((CME_LCL_PSCRS00 + (core_index << 7) + (thread << 5))); - PK_TRACE_DBG("Old dsl%d of Core%d Thread%d, current PSCRS%x", + PK_TRACE_DBG("Old DSL[%d] of Core[%d] Thread[%d], current PSCRS[%x]", G_dsl[core_index][thread], core_index, thread, pscrs); // Calculate new DSL @@ -764,7 +747,7 @@ STOP1_EXIT: G_dsl[core_index][thread] = MIN(temp_dsl, MAX(act_stop_level, G_dsl[core_index][thread])); - PK_TRACE_DBG("New dsl%d", G_dsl[core_index][thread]); + PK_TRACE_DBG("New DSL[%d]", G_dsl[core_index][thread]); // Calculate new SRR1 if (G_dsl[core_index][thread] >= STOP_LEVEL_8) @@ -780,7 +763,7 @@ STOP1_EXIT: srr1[thread] = temp_srr1; } - PK_TRACE_DBG("Srr1%d", srr1[thread]); + PK_TRACE_DBG("Srr1[%d]", srr1[thread]); // 36-39|44-47|52-55|60-63 scom_data.words.lower |= @@ -795,13 +778,10 @@ STOP1_EXIT: #else - PK_TRACE_INF("SX0.E: Restore PSSCR.PLS+SRR1 back to actual level"); - for (core_mask = 2; core_mask; core_mask--) { if (core & core_mask) { - PK_TRACE_DBG("Set PLS+SRR1 for Core[%d]", core_mask); CME_GETSCOM(PPM_SSHSRC, core_mask, CME_SCOM_AND, scom_data.value); act_stop_level = (scom_data.words.upper & BITS32(8, 4)) >> SHIFT32(11); @@ -854,12 +834,10 @@ STOP1_EXIT: #endif - PK_TRACE_DBG("Check: Core[%d] Serviced by SX0", core); - - PK_TRACE_INF("SX0.F: Now Wakeup the Core (pm_exit=1) via SICR[4/5]"); + PK_TRACE_INF("SX.0A: Core[%d] Waking up(pm_exit=1) via SICR[4/5]", core); out32(CME_LCL_SICR_OR, core << SHIFT32(5)); - PK_TRACE_INF("SX0.G: Polling for Core Waking up(pm_active=0) via EINR[20/21]"); + PK_TRACE_DBG("Polling for Core Waking up(pm_active=0) via EINR[20/21]"); while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); @@ -870,8 +848,9 @@ STOP1_EXIT: #endif - PK_TRACE_INF("SX0.H: Release PCB Mux back to Core via SICR[10/11]"); + PK_TRACE_INF("Core Release PCB Mux via SICR[10/11]"); p9_cme_release_pcbmux(core); + PK_TRACE("Update STOP history: STOP exit completed, core ready"); scom_data.words.lower = 0; scom_data.words.upper = SSH_EXIT_COMPLETE; @@ -889,15 +868,15 @@ STOP1_EXIT: G_cme_stop_record.core_running |= core; G_cme_stop_record.core_stopgpe &= ~core; - PK_TRACE("Drop halt STOP override disable via LMCR[14/15]"); + PK_TRACE_DBG("Drop halt STOP override disable via LMCR[14/15]"); out32(CME_LCL_LMCR_CLR, (core << SHIFT32(15))); #if SPWU_AUTO - PK_TRACE_INF("SX0.I: Drop auto spwu disable, enable auto spwu via LMCR[12/13]"); + PK_TRACE_DBG("Drop auto spwu disable, enable auto spwu via LMCR[12/13]"); out32(CME_LCL_LMCR_CLR, core << SHIFT32(13)); - PK_TRACE_INF("SX0.J: Drop pm_exit via SICR[4/5]"); + PK_TRACE_INF("SX.0B: Core Drop PM_EXIT via SICR[4/5]"); out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); #else @@ -907,19 +886,16 @@ STOP1_EXIT: // done = spwu + !pm_active + !core_chiplet_fence + !pcbmux_req + !pcbmux_grant // chiplet fence forces pm_active to zero // Note: pm_exit is asserted above for every core waking up including spwu - PK_TRACE_DBG("Check: Core[%d] EISR=0/EIPR=0/spwu_done=1", spwu_stop); + PK_TRACE_INF("SX.0B: Core[%d] Assert SPWU_DONE via SICR[16/17]", spwu_stop); out32(CME_LCL_EISR_CLR, spwu_stop << SHIFT32(15)); // clear spwu in EISR out32(CME_LCL_EIPR_CLR, spwu_stop << SHIFT32(15)); // flip EIPR to falling edge - - PK_TRACE_INF("SX0.K: Assert SPWU Done on Core via SICR[16/17]"); out32(CME_LCL_SICR_OR, spwu_stop << SHIFT32(17)); // assert spwu_done now G_cme_stop_record.core_in_spwu |= spwu_stop; } if ((core = (core & (~spwu_stop)))) { - PK_TRACE_DBG("Check: Core[%d] isnt SPWUed, Drop PM_EXIT", core); - PK_TRACE_INF("SX0.L: Drop PM_EXIT for NOT SPWU Core via SICR[4/5]"); + PK_TRACE_INF("SX.0C: Core[%d] isnt SPWUed, Drop PM_EXIT via SICR[4/5]", core); out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index 3e16a0d7..709489f9 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -42,7 +42,6 @@ p9_cme_stop_spwu_handler(void* arg, PkIrqId irq) { MARK_TRAP(STOP_SPWU_HANDLER) //PK_TRACE_INF("SPWU Handler"); - PK_TRACE_INF("SPWU Trigger %d", irq); PkMachineContext ctx; int sem_post = 0; @@ -51,6 +50,9 @@ p9_cme_stop_spwu_handler(void* arg, PkIrqId irq) uint32_t raw_spwu = (in32(CME_LCL_EISR) & BITS32(14, 2)) >> SHIFT32(15); uint64_t scom_data = 0; + PK_TRACE_INF("SPWU Trigger %d Level %x State %x", + irq, raw_spwu, G_cme_stop_record.core_in_spwu); + for(core_mask = 2; core_mask; core_mask--) { if (raw_spwu & core_mask) @@ -118,8 +120,8 @@ void p9_cme_stop_exit_handler(void* arg, PkIrqId irq) { MARK_TRAP(STOP_EXIT_HANDLER) - //PK_TRACE_INF("SX Handler"); - PK_TRACE_INF("SX Trigger %d", irq); + PK_TRACE_INF("SX Handler"); + PK_TRACE_DBG("SX Trigger %d", irq); out32(CME_LCL_EIMR_OR, BITS32(12, 6) | BITS32(20, 2)); pk_semaphore_post((PkSemaphore*)arg); } @@ -130,8 +132,8 @@ void p9_cme_stop_enter_handler(void* arg, PkIrqId irq) { MARK_TRAP(STOP_ENTER_HANDLER) - //PK_TRACE_INF("SE Handler"); - PK_TRACE_INF("SE Trigger %d", irq); + PK_TRACE_INF("SE Handler"); + PK_TRACE_DBG("SE Trigger %d", irq); out32(CME_LCL_EIMR_OR, BITS32(12, 6) | BITS32(20, 2)); pk_semaphore_post((PkSemaphore*)arg); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c index 38a60669..5cc11f26 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c @@ -33,10 +33,10 @@ p9_hcd_core_gptr_time_initf(uint32_t core) { int rc = CME_STOP_SUCCESS; - PK_TRACE_DBG("Scan ec_gptr ring core value %d", core); + PK_TRACE("Scan ec_gptr ring core value %d", core); putRing(core, CME_SCOM_EQ, ec_gptr); - PK_TRACE_DBG("Scan ec_time ring core value %d", core); + PK_TRACE("Scan ec_time ring core value %d", core); putRing(core, CME_SCOM_EQ, ec_time); return rc; diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c index d94b0768..3ea9f47f 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c +++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c @@ -451,7 +451,7 @@ int rs4DecompressionSvc( } else { - PK_TRACE_INF("OVERRIDE !!!!!!"); + PK_TRACE_DBG("OVERRIDE !!!!!!"); if(0x8 & l_nibble) // We are parsing RS4 for override rings { @@ -533,10 +533,9 @@ int rs4DecompressionSvc( getscom(0, CME_SCOM_ADDR(0x0003E000, i_core, l_scomOp), &l_readHeader); - PK_TRACE_DBG ("l_readHeader %08X %08X", l_readHeader >> 32, l_readHeader); - if(l_readHeader != 0xa5a5a5a5a5a5a5a5) { + PK_TRACE_INF("l_readHeader %08X %08X", l_readHeader >> 32, l_readHeader); //In EDR: ring Id (8b),core value(4b) and number of latches that went thru rotate //and scan. // In SPRG0: First 32 bits of header data read from the hw diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c index 223a9fed..39415c09 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c @@ -30,7 +30,8 @@ int p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_ex, int is_stop8) { - int rc = SGPE_STOP_SUCCESS; + int rc = SGPE_STOP_SUCCESS; + data64_t scom_data = {0}; #if !SKIP_HOMER_ACCESS @@ -39,7 +40,6 @@ p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_ex, int is_stop8) uint32_t qaddr = 0; uint64_t qdata = 0; uint32_t rid = 0; - data64_t scom_data = {0}; // doing this instead of multiply since there is no multiply instruction with ppe. for(i = 0; i < quad; i++) diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index 4c8d2d92..5ae7c1f7 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -69,7 +69,7 @@ p9_sgpe_stop_entry() #endif //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- //================================ @@ -290,10 +290,10 @@ p9_sgpe_stop_entry() } // ------------------------------------------------------------------------ - PK_TRACE_INF("+++++ +++++ EX STOP ENTRY [LEVEL 8-10] +++++ +++++"); + PK_TRACE("+++++ +++++ EX STOP ENTRY [LEVEL 8-10] +++++ +++++"); // ------------------------------------------------------------------------ - PK_TRACE_DBG("Check: q[%d]ex[%d] start ex entry", qloop, ex); + PK_TRACE_INF("SX.8A: Quad[%d] EX_L2[%d] Stopping L2 Clocks", qloop, ex); PK_TRACE("Acquire cache clock controller atomic lock"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CC_ATOMIC_LOCK, qloop), BITS64(0, 5)); @@ -301,8 +301,8 @@ p9_sgpe_stop_entry() if ((scom_data.words.upper & BITS32(0, 5)) != 0xC0000000) { - PKTRACE("ERROR: Failed to Obtain Cache %d Clk Ctrl Atomic Lock. Register Content: %x", - qloop, scom_data.words.upper); + PK_TRACE_INF("ERROR: Failed to Obtain Cache %d Clk Ctrl Atomic Lock. Register Content: %x", + qloop, scom_data.words.upper); PK_PANIC(SGPE_STOP_ENTRY_GET_CLK_LOCK_FAILED); } @@ -413,7 +413,7 @@ p9_sgpe_stop_entry() // MF: verify compiler generate single rlwmni // MF: delay may be needed for stage latch to propagate thold - PK_TRACE_INF("SE8.A: L2 Clock Stopped"); + PK_TRACE_INF("SE.8B: L2 Clock Stopped"); //======================== MARK_TRAP(SE_STOP_L2_GRID) @@ -489,7 +489,7 @@ p9_sgpe_stop_entry() ((qloop << 2) + cloop)); scom_data.words.lower = 0; scom_data.words.upper = (SSH_ACT_LV8_COMPLETE | - ((entry_ongoing[cloop >> 1]) << SHIFT32(3))); + (((uint32_t)entry_ongoing[cloop >> 1]) << SHIFT32(3))); GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, ((qloop << 2) + cloop), 0, scom_data.value); } @@ -498,7 +498,7 @@ p9_sgpe_stop_entry() out32(OCB_QSSR_CLR, BIT32(qloop + 20)); out32(OCB_QSSR_OR, (ex << SHIFT32((qloop << 1) + 1))); - PK_TRACE_INF("SE8.B: L2 Clock Sync Dropped"); + PK_TRACE_INF("SE.8C: L2 Clock Sync Dropped"); //================================================== MARK_TAG(SE_STOP8_DONE, ((ex << 6) | (32 >> qloop))) @@ -532,7 +532,7 @@ p9_sgpe_stop_entry() ex |= SND_EX_IN_QUAD; } - PK_TRACE_DBG("Check: q[%d]ex[%d] starts quad entry", qloop, ex); + PK_TRACE_INF("SX.11A: Quad[%d] EX_PG[%d] Shutting Cache Down", qloop, ex); PK_TRACE("Acquire cache PCB slave atomic lock"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), BITS64(0, 5)); @@ -540,8 +540,8 @@ p9_sgpe_stop_entry() if ((scom_data.words.upper & BITS32(0, 5)) != 0xC0000000) { - PKTRACE("ERROR: Failed to Obtain Cache %d PCB Slave Atomic Lock. Register Content: %x", - qloop, scom_data.words.upper); + PK_TRACE_INF("ERROR: Failed to Obtain Cache %d PCB Slave Atomic Lock. Register Content: %x", + qloop, scom_data.words.upper); PK_PANIC(SGPE_STOP_ENTRY_GET_SLV_LOCK_FAILED); } @@ -551,7 +551,7 @@ p9_sgpe_stop_entry() PK_TRACE("Update STOP history on quad[%d]: update request stop level", qloop); scom_data.words.lower = 0; scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | - (G_sgpe_stop_record.state[qloop].req_state_q << SHIFT32(7))); + ((uint32_t)G_sgpe_stop_record.state[qloop].req_state_q << SHIFT32(7))); GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value); //================================== @@ -618,7 +618,7 @@ p9_sgpe_stop_entry() (in32(OCB_OPIT3CN(((qloop << 2) + cloop))) & TYPE3_PAYLOAD_EXIT_EVENT)) { - PK_TRACE_INF("Abort: core wakeup detected"); + PK_TRACE_DBG("Abort: core wakeup detected"); l3_purge_aborted = 1; break; } @@ -628,7 +628,7 @@ p9_sgpe_stop_entry() if ((in32(OCB_OPIT6PRB) & BIT32(qloop)) && (in32(OCB_OPIT6QN(qloop)) & TYPE6_PAYLOAD_EXIT_EVENT)) { - PK_TRACE_INF("Abort: quad wakeup detected"); + PK_TRACE_DBG("Abort: quad wakeup detected"); l3_purge_aborted = 1; } @@ -639,7 +639,7 @@ p9_sgpe_stop_entry() MARK_TAG(SE_PURGE_L3_ABORT, (32 >> qloop)) //======================================== - PK_TRACE_INF("Abort: assert purge L3 abort"); + PK_TRACE_DBG("Abort: assert purge L3 abort"); if (ex & FST_EX_IN_QUAD) GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 0), @@ -649,7 +649,7 @@ p9_sgpe_stop_entry() GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 1), BIT64(2)); - PK_TRACE_INF("Abort: poll for abort done"); + PK_TRACE_DBG("Abort: poll for abort done"); if(ex & FST_EX_IN_QUAD) { @@ -675,7 +675,7 @@ p9_sgpe_stop_entry() MARK_TAG(SE_PURGE_L3_ABORT_DONE, (32 >> qloop)) //============================================= - PK_TRACE_INF("Abort: Drop LCO Disable"); + PK_TRACE("Abort: Drop LCO Disable"); if (ex & FST_EX_IN_QUAD) GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, @@ -713,7 +713,7 @@ p9_sgpe_stop_entry() continue; } - PK_TRACE_INF("SE11.A: L3 Purged"); + PK_TRACE_INF("SE.11B: L3 Purged"); #endif @@ -721,32 +721,7 @@ p9_sgpe_stop_entry() MARK_TAG(SE_PURGE_PB, (32 >> qloop)) //================================== - PK_TRACE("Assert powerbus purge via QCCR[30]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, qloop), BIT64(30)); - - PK_TRACE("Poll PowerBus purge done via QCCR[31]"); - - do - { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR, qloop), scom_data.value); - } - while(!(scom_data.words.upper & BIT32(31))); - - PK_TRACE("Drop powerbus purge via QCCR[30]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(30)); - - PK_TRACE_INF("SE11.B: PowerBus Purged"); - - //=========================================== - MARK_TAG(SE_WAIT_PGPE_SUSPEND, (32 >> qloop)) - //=========================================== - - /// @todo RTC166577 - /// IPC poll will move to here when multicast - - //====================================== - MARK_TAG(SE_QUIESCE_QUAD, (32 >> qloop)) - //====================================== + // Stopping CME first in case CME initiates Powerbus Traffic if (ex & FST_EX_IN_QUAD) { @@ -784,6 +759,36 @@ p9_sgpe_stop_entry() PK_TRACE("CME1 Halted"); } + PK_TRACE_DBG("CME Halted"); + + + PK_TRACE("Assert powerbus purge via QCCR[30]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, qloop), BIT64(30)); + + PK_TRACE("Poll PowerBus purge done via QCCR[31]"); + + do + { + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR, qloop), scom_data.value); + } + while(!(scom_data.words.upper & BIT32(31))); + + PK_TRACE("Drop powerbus purge via QCCR[30]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(30)); + + PK_TRACE_INF("SE.11C: PowerBus Purged"); + + //=========================================== + MARK_TAG(SE_WAIT_PGPE_SUSPEND, (32 >> qloop)) + //=========================================== + + /// @todo RTC166577 + /// IPC poll will move to here when multicast + + //====================================== + MARK_TAG(SE_QUIESCE_QUAD, (32 >> qloop)) + //====================================== + PK_TRACE("Assert refresh quiesce prior to L3 (refresh domain) stop clk via EX_DRAM_REF_REG[7]"); // Assert refresh quiesce prior to L3 (refresh domain) stop clk @@ -824,7 +829,7 @@ p9_sgpe_stop_entry() while(((~(scom_data.words.upper)) & BITS32(0, 4)) != BITS32(0, 4)); } - PK_TRACE_INF("SE11.C: NCU Status Clean"); + PK_TRACE_DBG("NCU Status Clean"); // In order to preserve state for PRD, // skip power off if host attn or local xstop present @@ -851,10 +856,7 @@ p9_sgpe_stop_entry() PK_TRACE("Stop cache clocks via CLK_REGION"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLK_REGION, qloop), - (CLK_STOP_CMD | CLK_THOLD_ALL | - CLK_REGION_ALL_BUT_EX | - ((uint64_t)ex << SHIFT64(7)) | - ((uint64_t)ex << SHIFT64(13)))); + (CLK_STOP_CMD | CLK_THOLD_ALL | CLK_REGION_ALL)); PK_TRACE("Poll for cache clocks stopped via CPLT_STAT0[8]"); @@ -864,12 +866,10 @@ p9_sgpe_stop_entry() } while(!(scom_data.words.upper & BIT32(8))); - PK_TRACE("Check core clock is stopped via CLOCK_STAT_SL[4-13]"); + PK_TRACE("Check cache clock is stopped via CLOCK_STAT_SL[4-13]"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_SL, qloop), scom_data.value); - if (((~scom_data.value) & (CLK_REGION_ALL_BUT_EX | - ((uint64_t)ex << SHIFT64(7)) | - ((uint64_t)ex << SHIFT64(13)))) != 0) + if (((~scom_data.value) & CLK_REGION_ALL) != 0) { PK_TRACE("ERROR: Cache clock stop failed. HALT SGPE!"); PK_PANIC(SGPE_STOP_ENTRY_EQ_STOPCLK_FAILED); @@ -881,11 +881,7 @@ p9_sgpe_stop_entry() PK_TRACE("Assert partial good regional fences via CPLT_CTRL1[4-14]"); // Must cover partial bad fences as well or powerbus error will raise // Note: Stop11 will lose all the fences so here needs to assert them - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop), - (CLK_REGION_ALL_BUT_EX | - ((uint64_t)ex << SHIFT64(7)) | - ((uint64_t)ex << SHIFT64(9)) | - ((uint64_t)ex << SHIFT64(13)))); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop), CLK_REGION_ALL); PK_TRACE("Drop CME_INTERPPM_DPLL_ENABLE after DPLL is stopped via QPMMR[26]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_CLR, qloop), BIT64(20) | BIT64(22) | BIT64(24) | BIT64(26)); @@ -894,7 +890,7 @@ p9_sgpe_stop_entry() PK_TRACE("Drop vdm enable via CPPM_VDMCR[0]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_CLR, qloop), BIT64(0)); - PK_TRACE_INF("SE11.D: Cache Clock Stopped"); + PK_TRACE_INF("SE.11D: Cache Clock Stopped"); #if HW405292_NDD1_PCBMUX_FENCE_FIX // Gate the PCBMux request so scanning doesn't cause random requests @@ -907,7 +903,7 @@ p9_sgpe_stop_entry() #if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX - PK_TRACE_INF("PBRW: Engage with PBIE Read/Write Pointer Scan Workaround"); + PK_TRACE_DBG("PBRW: Engage with PBIE Read/Write Pointer Scan Workaround"); // bit4,5,11 = perv/eqpb/pbieq, bit59 = inex PK_TRACE("PBRW: Setup scan register to select the ring"); @@ -1045,7 +1041,7 @@ p9_sgpe_stop_entry() // vcs_pfet_force_state = 00 (Nop) GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, qloop), BITS64(0, 4)); - PK_TRACE_INF("SE11.E: Cache Powered Off"); + PK_TRACE_INF("SE.11E: Cache Powered Off"); } #endif @@ -1086,7 +1082,7 @@ p9_sgpe_stop_entry() } //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ END OF STOP ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ END OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- //loop quad to clear qswu record diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c index 1556aed1..f277d070 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c @@ -50,6 +50,7 @@ extern SgpeStopRecord G_sgpe_stop_record; void p9_sgpe_set_slvcfg_pm_disable(uint32_t qloop) { + PK_TRACE_INF("Assert PM_DISABLE in SLAVE_CONFIG"); uint64_t l_scomData = 0; uint32_t l_scomAddr = 0; @@ -62,10 +63,11 @@ void p9_sgpe_set_slvcfg_pm_disable(uint32_t qloop) l_scomData |= SLAVE_CONFIG_PM_DISABLE | SLAVE_CONFIG_PM_MUX_DISABLE; GPE_PUTSCOM(l_scomAddr, l_scomData); } - } + void p9_sgpe_clear_slvcfg_pm_disable(uint32_t qloop) { + PK_TRACE_INF("Clear PM_DISABLE in SLAVE_CONFIG"); uint64_t l_scomData = 0; uint32_t l_scomAddr = 0; @@ -78,7 +80,6 @@ void p9_sgpe_clear_slvcfg_pm_disable(uint32_t qloop) l_scomData &= ~SLAVE_CONFIG_PM_DISABLE & ~SLAVE_CONFIG_PM_MUX_DISABLE; GPE_PUTSCOM(l_scomAddr, l_scomData); } - } #endif @@ -299,7 +300,7 @@ p9_sgpe_stop_exit() } //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ BEGIN OF STOP EXIT +++++ +++++"); + PK_TRACE("+++++ +++++ BEGIN OF STOP EXIT +++++ +++++"); //-------------------------------------------------------------------------- if (G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG] & BIT32(qloop)) @@ -350,12 +351,9 @@ p9_sgpe_stop_exit() { //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ QUAD STOP EXIT [LEVEL 11-15] +++++ +++++"); + PK_TRACE("+++++ +++++ QUAD STOP EXIT [LEVEL 11-15] +++++ +++++"); //-------------------------------------------------------------------------- - PK_TRACE_DBG("Check: quad[%d] m_l2[%d] m_pg[%d] Serviced by SX11FH", - qloop, m_l2, m_pg); - PK_TRACE("Update STOP history on quad[%d]: in transition of exit", qloop); scom_data.words.lower = 0; @@ -363,7 +361,6 @@ p9_sgpe_stop_exit() GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value); #if HW405292_NDD1_PCBMUX_FENCE_FIX - PK_TRACE_INF("Setting slvcfg %d", qloop); // Gate the PCBMux request so scanning doesn't cause random requests p9_sgpe_set_slvcfg_pm_disable(qloop); #endif @@ -373,19 +370,19 @@ p9_sgpe_stop_exit() //================================= // NOTE: it is required to serialize power on quad PFETs to prevent droop - PK_TRACE_INF("SX11.A: Cache Poweron"); + PK_TRACE_INF("SX.11A: Cache[%d] EX_PG[%d] Poweron", qloop, m_pg); p9_hcd_cache_poweron(qloop); //========================= MARK_TRAP(SX_CHIPLET_RESET) //========================= - PK_TRACE_INF("SX11.B: Cache Chiplet Reset"); + PK_TRACE_INF("SX.11B: Cache Chiplet Reset"); p9_hcd_cache_chiplet_reset(qloop, m_pg); #if !SKIP_INITF - PK_TRACE_INF("SX11.C: Cache Chiplet L3 DCC Setup"); + PK_TRACE_DBG("Cache Chiplet L3 DCC Setup"); p9_hcd_cache_chiplet_l3_dcc_setup(qloop); #endif @@ -394,7 +391,7 @@ p9_sgpe_stop_exit() #if !STOP_PRIME #if !SKIP_INITF - PK_TRACE_INF("SX11.D: Cache Gptr Time Initf"); + PK_TRACE_INF("SX.11C: Cache Gptr/Time Initf"); p9_hcd_cache_gptr_time_initf(qloop); #endif @@ -405,17 +402,17 @@ p9_sgpe_stop_exit() #if !SKIP_INITF - PK_TRACE_INF("SX11.E: Cache Dpll Initf"); + PK_TRACE_DBG("Cache Dpll Initf"); p9_hcd_cache_dpll_initf(qloop); #endif - PK_TRACE_INF("SX11.F: Cache Dpll Setup"); + PK_TRACE_INF("SX.11D: Cache Dpll Setup"); p9_hcd_cache_dpll_setup(qloop); #if !SKIP_INITF - PK_TRACE_INF("SX11.G: Cache DCC Skewadjust Setup"); + PK_TRACE_DBG("Cache DCC Skewadjust Setup"); p9_hcd_cache_dcc_skewadjust_setup(qloop); #endif @@ -437,12 +434,12 @@ p9_sgpe_stop_exit() MARK_TAG(SX_CHIPLET_INITS, (32 >> qloop)) //======================================= - PK_TRACE_INF("SX11.H: Cache Chiplet Init"); + PK_TRACE_DBG("Cache Chiplet Init"); p9_hcd_cache_chiplet_init(qloop); #if !SKIP_INITF - PK_TRACE_INF("SX11.I: Cache Repair Initf"); + PK_TRACE_INF("SX.11E: Cache Repair Initf"); p9_hcd_cache_repair_initf(qloop); #endif @@ -453,7 +450,7 @@ p9_sgpe_stop_exit() #if !SKIP_ARRAYINIT - PK_TRACE_INF("SX11.J: Cache Arrayinit"); + PK_TRACE_INF("SX.11F: Cache Arrayinit"); p9_hcd_cache_arrayinit(qloop, m_pg); #endif @@ -471,7 +468,7 @@ p9_sgpe_stop_exit() if (pCpmrHdrAddr->fusedModeStatus == 0xBB) { - PK_TRACE_INF("FUSED_CORE_MODE Flag is set in CPMR Header"); + PK_TRACE_INF("WARNING: FUSED_CORE_MODE Flag is Set in CPMR Header"); for(cloop = 0; cloop < CORES_PER_QUAD; cloop++) { @@ -486,7 +483,7 @@ p9_sgpe_stop_exit() #if FUSED_CORE_MODE_SCAN_FIX - PK_TRACE_INF("FCMS: Engage with Fused Mode Scan Workaround"); + PK_TRACE_DBG("FCMS: Engage with Fused Mode Scan Workaround"); if (m_pg & FST_EX_IN_QUAD) { @@ -507,7 +504,7 @@ p9_sgpe_stop_exit() #if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX - PK_TRACE_INF("FCMS: Engage with PBIE Read/Write Pointer Scan Workaround"); + PK_TRACE_DBG("PBRW: Engage with PBIE Read/Write Pointer Scan Workaround"); // bit4,5,11 = perv/eqpb/pbieq, bit59 = inex PK_TRACE("PBRW: Setup scan register to select the ring"); @@ -581,7 +578,7 @@ p9_sgpe_stop_exit() #if !SKIP_INITF - PK_TRACE_INF("SX11.K: Cache Func Scan"); + PK_TRACE_INF("SX.11G: Cache Func Scan"); p9_hcd_cache_initf(qloop); #endif @@ -591,7 +588,7 @@ p9_sgpe_stop_exit() MARK_TAG(SX_CACHE_STARTCLOCKS, (32 >> qloop)) //=========================================== - PK_TRACE_INF("SX11.L: Cache Startclocks"); + PK_TRACE_INF("SX.11H: Cache Startclocks"); p9_hcd_cache_startclocks(qloop, m_pg); } @@ -600,12 +597,9 @@ p9_sgpe_stop_exit() { //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ EX STOP EXIT [LEVEL 8-10] +++++ +++++"); + PK_TRACE("+++++ +++++ EX STOP EXIT [LEVEL 8-10] +++++ +++++"); //-------------------------------------------------------------------------- - PK_TRACE_DBG("Check: quad[%d] m_l2[%d] m_pg[%d] Serviced by SX8", - qloop, m_l2, m_pg); - //======================================================== MARK_TAG(SX_L2_STARTCLOCKS, ((m_l2 << 6) | (32 >> qloop))) //======================================================== @@ -614,16 +608,17 @@ p9_sgpe_stop_exit() PK_TRACE("Switch L2 glsmux select to DPLL output via EXCGCR[34,35]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_OR, qloop), BITS64(34, 2)); - PK_TRACE_INF("SX8.A: Cache L2 Startclocks"); + PK_TRACE_INF("SX.8A: Cache[%d] EX_PG[%d] Start L2[%d] Clocks", + qloop, m_pg, m_l2); p9_hcd_cache_l2_startclocks(qloop, m_l2, m_pg); // for l2 scom init and restore that cannot be done via stop11 // as if that certain l2 wasnt exiting(thus lack of clock for scom) - PK_TRACE_INF("SX8.B: Cache L2 Scominit"); + PK_TRACE_INF("SX.8B: Cache L2 Scominit"); p9_hcd_cache_scominit(qloop, m_l2, 1); - PK_TRACE_INF("SX8.C: Cache L2 Scomcust"); + PK_TRACE_DBG("Cache L2 Scomcust"); p9_hcd_cache_scomcust(qloop, m_l2, 1); // reset ex actual state if ex is exited. @@ -646,8 +641,8 @@ p9_sgpe_stop_exit() if (scom_data.words.upper & BIT32(0)) { - PKTRACE("ERROR: Failed to Release Cache %d Clk Ctrl Atomic Lock. Register Content: %x", - qloop, scom_data.words.upper); + PK_TRACE_INF("ERROR: Failed to Release Cache %d Clk Ctrl Atomic Lock. Register Content: %x", + qloop, scom_data.words.upper); PK_PANIC(SGPE_STOP_EXIT_DROP_CLK_LOCK_FAILED); } } @@ -660,12 +655,9 @@ p9_sgpe_stop_exit() { //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ QUAD STOP EXIT CONTINUE +++++ +++++"); + PK_TRACE("+++++ +++++ QUAD STOP EXIT CONTINUE +++++ +++++"); //-------------------------------------------------------------------------- - PK_TRACE_DBG("Check: quad[%d] m_l2[%d] m_pg[%d] Serviced by SX11SH", - qloop, m_l2, m_pg); - for (ec_index = 0; ec_index < CORES_PER_QUAD; ec_index += 2) { @@ -701,15 +693,14 @@ p9_sgpe_stop_exit() MARK_TAG(SX_SCOM_INITS, (32 >> qloop)) //==================================== - PK_TRACE_INF("SX11.M: Cache Scom Init"); + PK_TRACE_INF("SX.11I: Cache Scom Init"); p9_hcd_cache_scominit(qloop, m_pg, 0); - PK_TRACE_INF("SX11.N: Cache Scom Cust"); + PK_TRACE_DBG("Cache Scom Cust"); p9_hcd_cache_scomcust(qloop, m_pg, 0); #if HW405292_NDD1_PCBMUX_FENCE_FIX - PK_TRACE_INF("Clearing SLVCNFG %d", qloop); // Allow the CME to access the PCB Slave NET_CTRL registers p9_sgpe_clear_slvcfg_pm_disable(qloop); #endif @@ -732,7 +723,6 @@ p9_sgpe_stop_exit() // workaround has to use base address as read on OR/CLR leads to error p9_dd1_db_unicast_wr(GPE_SCOM_ADDR_CORE(CPPM_CMEDB1, ((qloop << 2) + cloop)), BIT64(7)); - PK_TRACE_INF("SX11.O: Core DB1 to CME"); } // Setting up cme_flags @@ -899,9 +889,8 @@ p9_sgpe_stop_exit() #if !SKIP_CME_BOOT_STOP11 uint16_t cmeBootList = (m_pg << SHIFT16(((qloop << 1) + 1))); - PK_TRACE_DBG("Check: CmeBootList[%x]", cmeBootList); + PK_TRACE_INF("SX.CME: Booting Cme[%x]", cmeBootList); boot_cme( cmeBootList ); - PK_TRACE_INF("SX11.P: Cmes booted"); #endif @@ -909,10 +898,10 @@ p9_sgpe_stop_exit() MARK_TAG(SX_RUNTIME_INITS, (32 >> qloop)) //======================================= - PK_TRACE_INF("SX11.Q: Cache RAS Runtime Scom"); + PK_TRACE_DBG("Cache RAS Runtime Scom"); p9_hcd_cache_ras_runtime_scom(qloop); - PK_TRACE_INF("SX11.R: Cache OCC Runtime Scom"); + PK_TRACE_DBG("Cache OCC Runtime Scom"); p9_hcd_cache_occ_runtime_scom(qloop); //========================= @@ -927,8 +916,8 @@ p9_sgpe_stop_exit() if (scom_data.words.upper & BIT32(0)) { - PKTRACE("ERROR: Failed to Release Cache %d PCB Slave Atomic Lock. Register Content: %x", - qloop, scom_data.words.upper); + PK_TRACE_INF("ERROR: Failed to Release Cache %d PCB Slave Atomic Lock. Register Content: %x", + qloop, scom_data.words.upper); PK_PANIC(SGPE_STOP_EXIT_DROP_SLV_LOCK_FAILED); } @@ -945,17 +934,15 @@ p9_sgpe_stop_exit() } //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ END OF STOP EXIT +++++ +++++"); + PK_TRACE("+++++ +++++ END OF STOP EXIT +++++ +++++"); //-------------------------------------------------------------------------- if (qspwu & BIT32(0)) { - PK_TRACE_DBG("Check: Quad[%d] will assert SPWU Done", qloop); + PK_TRACE_INF("SP.WU: Quad[%d] Assert SPWU_DONE", qloop); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_OR, qloop), BIT64(0)); - G_sgpe_stop_record.group.qswu[VECTOR_CONFIG] |= BIT32(qloop); G_sgpe_stop_record.group.qswu[VECTOR_EXIT] &= ~BIT32(qloop); - PK_TRACE_INF("SX0.A: Assert Quad SPWU Done"); } // process core portion of core request @@ -975,7 +962,7 @@ p9_sgpe_stop_exit() if (!(scom_data.value & BIT64(13))) { - PKTRACE("ERROR.Q: core[%d] was not set before release", + PKTRACE("ERROR.A: core[%d] was not set before release", ((qloop << 2) + cloop)); pk_halt(); } @@ -995,13 +982,12 @@ p9_sgpe_stop_exit() #endif - PK_TRACE_DBG("Check: Core[%d] will clear wakeup_notify_select", + PK_TRACE_INF("SX.CME: Core[%d] Switch CorePPM Wakeup Back to CME via CPMMR[13]", ((qloop << 2) + cloop)); p9_dd1_cppm_unicast_wr( GPE_SCOM_ADDR_CORE(CPPM_CPMMR, ((qloop << 2) + cloop)), GPE_SCOM_ADDR_CORE(CPPM_CPMMR_CLR, ((qloop << 2) + cloop)), BIT64(13), CLR_OP); - PK_TRACE_INF("SX0.B: Switch CorePPM Wakeup back to CME via CPMMR[13] qloop[%d] cloop[%d]", qloop, cloop); } PK_TRACE("Update QSSR: drop stop_exit_ongoing"); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c index 866993d9..7f9aed83 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c @@ -106,8 +106,9 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) // Disable type2/3/6 interrupt out32(OCB_OIMR1_OR, (BITS32(15, 2) | BIT32(19))); // Read type2/3/6 interrupt status - cirq = (in32(OCB_OISR1) & BITS32(15, 2)); - qirq = (in32(OCB_OISR1) & BIT32(19)); + qirq = in32(OCB_OISR1); + cirq = qirq & BITS32(15, 2); + qirq = qirq & BIT32(19); // Clear type2/3/6 interrupt status out32(OCB_OISR1_CLR, (cirq | qirq)); @@ -117,14 +118,14 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) { cpending_t2 = in32(OCB_OPITNPRA(2)); out32(OCB_OPITNPRA_CLR(2), cpending_t2); - PKTRACE("Type2: %x", cpending_t2); + PK_TRACE("Type2: %x", cpending_t2); } if (cirq & BIT32(16)) { cpending_t3 = in32(OCB_OPITNPRA(3)); out32(OCB_OPITNPRA_CLR(3), cpending_t3); - PKTRACE("Type3: %x", cpending_t3); + PK_TRACE("Type3: %x", cpending_t3); } if (qirq) @@ -155,15 +156,15 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) // read payload on quad has interrupt pending qpayload_t6 = in32(OCB_OPIT6QN(qloop)); - PK_TRACE_DBG("Q[%d] Payload [%x]", qloop, qpayload_t6); + PK_TRACE_DBG("Quad[%d] Payload [%x]", qloop, qpayload_t6); if (qpayload_t6 & TYPE6_PAYLOAD_EXIT_EVENT) { - PK_TRACE_DBG("Q[%d] Request Special Wakeup", qloop); + PK_TRACE_DBG("Quad Request Special Wakeup"); if (G_sgpe_stop_record.group.qswu[VECTOR_CONFIG] & BIT32(qloop)) { - PK_TRACE_DBG("Q[%d] Already in Special Wakeup", qloop); + PK_TRACE_DBG("Quad Already in Special Wakeup"); } else { @@ -177,7 +178,7 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) } else { - PK_TRACE_DBG("Q[%d] Drop Special Wakeup, Clearing Done", qloop); + PK_TRACE_DBG("Quad Drop Special Wakeup, Clearing Done"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_CLR, qloop), BIT64(0)); G_sgpe_stop_record.group.qswu[VECTOR_ENTRY] |= BIT32(qloop); @@ -192,7 +193,7 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) continue; } - PK_TRACE_DBG("Q[%d] Has Core Request:", qloop); + PK_TRACE_DBG("Quad[%d] Has Core Request:", qloop); PK_TRACE_DBG("Now clv[%d][%d][%d][%d]", G_sgpe_stop_record.level[qloop][0], G_sgpe_stop_record.level[qloop][1], @@ -223,7 +224,7 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) cpayload_t3 = in32(OCB_OPIT3CN(((qloop << 2) + cloop))); } - PK_TRACE_INF("C[%d] Type2 Payload [%x] Type3 Payload [%x]", + PK_TRACE_INF("Core[%d] Type2 Payload [%x] Type3 Payload [%x]", cloop, cpayload_t2, cpayload_t3); GPE_GETSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR, @@ -269,14 +270,13 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) // if t2 entry (t3 exit or empty) else if (cpayload_t2 && (!(cpayload_t2 & TYPE2_PAYLOAD_EXIT_EVENT))) { - if (!(scom_data & BIT64(13))) { PK_TRACE_INF("ERROR: Received Type2 Entry PIG When Wakeup_notify_select = 0"); PK_PANIC(SGPE_PIG_TYPE2_ENTRY_WNS_CME); } - PK_TRACE_INF("C[%d] Request Entry via Type2", cloop); + PK_TRACE_INF("Core[%d] Request Entry via Type2", cloop); G_sgpe_stop_record.level[qloop][cloop] = (cpayload_t2 & TYPE2_PAYLOAD_STOP_LEVEL); G_sgpe_stop_record.group.core[VECTOR_ENTRY] |= @@ -291,7 +291,7 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) PK_PANIC(SGPE_PIG_TYPE3_ENTRY_WNS_CME); } - PK_TRACE_INF("C[%d] Request Entry via Type3", cloop); + PK_TRACE_INF("Core[%d] Request Entry via Type3", cloop); G_sgpe_stop_record.level[qloop][cloop] = (cpayload_t3 & TYPE2_PAYLOAD_STOP_LEVEL); G_sgpe_stop_record.group.core[VECTOR_ENTRY] |= @@ -308,10 +308,14 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) PK_TRACE_INF("ERROR: Received Both Types of Exit PIG When Wakeup_notify_select = 0"); PK_PANIC(SGPE_PIG_TYPE23_EXIT_WNS_CME); } + else + { + PK_TRACE_INF("WARNING: Received Phantom Exit PIG When Wakeup_notify_select = 0"); + } } else { - PK_TRACE_INF("C[%d] Request Exit", cloop); + PK_TRACE_INF("Core[%d] Request Exit", cloop); if (cloop < CORES_PER_EX) { @@ -336,7 +340,7 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) } } - PK_TRACE_DBG("New clv[%d][%d][%d][%d]", + PK_TRACE_DBG("New Core Levels[%d][%d][%d][%d]", G_sgpe_stop_record.level[qloop][0], G_sgpe_stop_record.level[qloop][1], G_sgpe_stop_record.level[qloop][2], @@ -381,7 +385,5 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) PK_TRACE_INF("Unblock Entry"); pk_semaphore_post(&(G_sgpe_stop_record.sem[0])); } - - PK_TRACE_INF("RFI"); } } |
