STOP: SGPE uses unified interrupt handler

Change-Id: Id64b5b06ab4286e84092b9a10c3ada1a8785bd76
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32790
Dev-Ready: ADAM S. HALE <ashale@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: ADAM S. HALE <ashale@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

8 files changed, 341 insertions, 15 deletions

diff --git a/import/chips/p9/common/pmlib/include/occhw_irq_config.h b/import/chips/p9/common/pmlib/include/occhw_irq_config.h
index 69ad6d36..f4f2f6d2 100644
--- a/import/chips/p9/common/pmlib/include/occhw_irq_config.h
+++ b/import/chips/p9/common/pmlib/include/occhw_irq_config.h
@@ -77,11 +77,11 @@
     OCCHW_IRQ_OCC_ERROR                     OCCHW_IRQ_TARGET_ID_NONE \
     OCCHW_IRQ_PBA_ERROR                     OCCHW_IRQ_TARGET_ID_NONE \
     OCCHW_IRQ_SRT_ERROR                     OCCHW_IRQ_TARGET_ID_NONE \
-    OCCHW_IRQ_GPE0_HALT                     OCCHW_IRQ_TARGET_ID_NONE \
-    OCCHW_IRQ_GPE1_HALT                     OCCHW_IRQ_TARGET_ID_NONE \
-    OCCHW_IRQ_GPE2_HALT                     OCCHW_IRQ_TARGET_ID_NONE \
-    OCCHW_IRQ_GPE3_HALT                     OCCHW_IRQ_TARGET_ID_NONE \
-    OCCHW_IRQ_PPC405_HALT                   OCCHW_IRQ_TARGET_ID_NONE \
+    OCCHW_IRQ_GPE0_HALT                     OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_GPE1_HALT                     OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+    OCCHW_IRQ_GPE2_HALT                     OCCHW_IRQ_TARGET_ID_GPE3 \
+    OCCHW_IRQ_GPE3_HALT                     OCCHW_IRQ_TARGET_ID_GPE2 \
+    OCCHW_IRQ_PPC405_HALT                   OCCHW_IRQ_TARGET_ID_405_NONCRIT \
     OCCHW_IRQ_OCB_ERROR                     OCCHW_IRQ_TARGET_ID_NONE \
     OCCHW_IRQ_SPIPSS_ERROR                  OCCHW_IRQ_TARGET_ID_NONE \
     OCCHW_IRQ_CHECK_STOP_PPC405             OCCHW_IRQ_TARGET_ID_405_NONCRIT \
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
index b2a5bb44..c6e5b84a 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
@@ -93,6 +93,7 @@
 /// IRQ#, TYPE, POLARITY, ENABLE
 ///
 #define APPCFG_EXT_IRQS_CONFIG \
+    OCCHW_IRQ_GPE3_HALT                   OCCHW_IRQ_TYPE_EDGE  OCCHW_IRQ_POLARITY_RISING  OCCHW_IRQ_MASKED \
     OCCHW_IRQ_CHECK_STOP_GPE2             OCCHW_IRQ_TYPE_EDGE  OCCHW_IRQ_POLARITY_RISING  OCCHW_IRQ_MASKED \
     OCCHW_IRQ_IPI2_HI_PRIORITY            OCCHW_IRQ_TYPE_EDGE  OCCHW_IRQ_POLARITY_RISING  OCCHW_IRQ_MASKED \
     OCCHW_IRQ_IPI2_LO_PRIORITY            OCCHW_IRQ_TYPE_EDGE  OCCHW_IRQ_POLARITY_RISING  OCCHW_IRQ_MASKED \
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c
new file mode 100644
index 00000000..ca51cf54
--- /dev/null
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c
@@ -0,0 +1,177 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file   p9_sgpe_irq.c
+/// \brief  Shared and global file for SGPE H-codes.
+/// \owner  Michael Olsen   Email: cmolsen@us.ibm.com
+/// \owner  David Du        Email: daviddu@us.ibm.com
+///
+
+#include "pk.h"
+#include "p9_sgpe_irq.h"
+
+//-------------------------------------------------------------------//
+//            DO NOT modify this file unless you're the owner        //
+//-------------------------------------------------------------------//
+
+// Notes:
+//   The following two lists,
+//     ext_irq_vectors_sgpe[][] and IDX_PRTY_LVL_<task_abbr>, must match.
+//   IDX_PRTY_LVL_<task_abbr> is the tasks priority level and serves
+//   as the index into the ext_irq_vectors_sgpe[][] table.
+
+const uint64_t ext_irq_vectors_sgpe[NUM_EXT_IRQ_PRTY_LEVELS][2] =
+{
+    /* 0: IDX_PRTY_VEC    1: IDX_MASK_VEC */
+    {
+        IRQ_VEC_PRTY0_SGPE, /* 0: IDX_PRTY_LVL_HIPRTY */
+        IRQ_VEC_PRTY4_SGPE |
+        IRQ_VEC_PRTY3_SGPE |
+        IRQ_VEC_PRTY2_SGPE |
+        IRQ_VEC_PRTY1_SGPE |
+        IRQ_VEC_PRTY0_SGPE
+    },
+    {
+        IRQ_VEC_PRTY1_SGPE, /* 1: IDX_PRTY_LVL_IPI3_HIGH */
+        IRQ_VEC_PRTY4_SGPE |
+        IRQ_VEC_PRTY3_SGPE |
+        IRQ_VEC_PRTY2_SGPE |
+        IRQ_VEC_PRTY1_SGPE
+    },
+    {
+        IRQ_VEC_PRTY2_SGPE, /* 2: IDX_PRTY_LVL_PIG_TYPE */
+        IRQ_VEC_PRTY4_SGPE |
+        IRQ_VEC_PRTY3_SGPE |
+        IRQ_VEC_PRTY2_SGPE
+    },
+    {
+        IRQ_VEC_PRTY3_SGPE, /* 3: IDX_PRTY_LVL_IPI3_LOW */
+        IRQ_VEC_PRTY4_SGPE |
+        IRQ_VEC_PRTY3_SGPE
+    },
+    {
+        IRQ_VEC_PRTY4_SGPE, /* 4: IDX_PRTY_LVL_DISABLED */
+        IRQ_VEC_PRTY4_SGPE
+    }
+};
+
+uint8_t       g_current_prty_level = NUM_EXT_IRQ_PRTY_LEVELS - 1;
+uint8_t       g_oimr_stack[NUM_EXT_IRQ_PRTY_LEVELS];
+int           g_oimr_stack_ctr = -1;
+uint64_t      g_oimr_override_stack[NUM_EXT_IRQ_PRTY_LEVELS];
+uint64_t      g_oimr_override = 0x0000000000000000;
+
+// Unified IRQ priority and masking handler.
+// - Locates the highest priority IRQ task vector that has at least one of its
+//   interrupts in the current external PK interrupt vector.
+void pk_unified_irq_prty_mask_handler(void)
+{
+    uint8_t   iPrtyLvl, bFound;
+    uint64_t  ext_irq_vector_pk;
+
+    // 1. Identify the priority level of the interrupt.
+    ext_irq_vector_pk = ((uint64_t)in32(OCB_G0ISR0 + APPCFG_OCC_INSTANCE_ID * 8)) << 32 |
+                        (uint64_t)in32(OCB_G0ISR1 + APPCFG_OCC_INSTANCE_ID * 8);
+    bFound = FALSE;
+    iPrtyLvl = 0;
+
+    do
+    {
+        if (ext_irq_vectors_sgpe[iPrtyLvl][IDX_PRTY_VEC] & ext_irq_vector_pk)
+        {
+            bFound = TRUE;
+            break;
+        }
+    }
+    while(++iPrtyLvl < (NUM_EXT_IRQ_PRTY_LEVELS - 1)); //No need to check DISABLED.
+
+    // Only manipulate EIMR masks for task level prty levels.
+    // Let shared non-task IRQs (iPrtyLvl=0) be processed by
+    // the PK kernel in usual fashion.
+    if (bFound)
+    {
+        // 2. Save current mask (assume current prty level).
+        //    Note, reading EIMR is NOT safe because overrides may already have
+        //      happened to the EIMR. And we always want to restore
+        //      the EIMR to a known value when we exit our thread.
+        if (++g_oimr_stack_ctr < NUM_EXT_IRQ_PRTY_LEVELS)
+        {
+            // Make a note of present prty level and
+            // then update tracker to new prty level.
+            g_oimr_stack[g_oimr_stack_ctr] = g_current_prty_level;
+            g_current_prty_level = iPrtyLvl; // Update prty level tracker.
+            g_oimr_override_stack[g_oimr_stack_ctr] = g_oimr_override;
+        }
+        else
+        {
+            MY_TRACE_ERR("Code bug: EIMR S/R stack counter=%d  >=  max=%d.",
+                         g_oimr_stack_ctr, NUM_EXT_IRQ_PRTY_LEVELS);
+            pk_halt();
+        }
+
+        // 3. Write the new mask for this priority level.
+
+        // First, clear all those IRQs that could possibly interrupt this instance.
+        //  This includes all those IRQs which belong to this instance as well as
+        //  those high-prty IRQs shared with the other instances.
+        out32(OCB_OIMR0_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS >> 32));
+        out32(OCB_OIMR1_CLR, (uint32_t)IRQ_VEC_ALL_OUR_IRQS);
+
+        // Second, mask IRQs belonging to this task and lower prty tasks.
+        // Note, that we do not modify the permanently disabled IRQs, such as the
+        //  _RESERVED_ ones. Nor do we touch other instances' IRQs. Iow, the
+        //  IDX_PRTY_LVL_DISABLED mask is  NOT  part of the mask we apply below.
+        out32(OCB_OIMR0_OR, (uint32_t)((ext_irq_vectors_sgpe[iPrtyLvl][IDX_MASK_VEC] |
+                                        g_oimr_override) >> 32) );
+        out32(OCB_OIMR1_OR, (uint32_t)(ext_irq_vectors_sgpe[iPrtyLvl][IDX_MASK_VEC] |
+                                       g_oimr_override) );
+
+    }
+    else
+    {
+        MY_TRACE_ERR("A disabled IRQ fired");
+        MY_TRACE_ERR("ext_irq_vector_pk=0x%08x%08x", ext_irq_vector_pk);
+#if !EPM_P9_TUNING
+        pk_halt();
+#endif
+    }
+
+
+    // 4. Return the priority vector in d5 and let hwmacro_get_ext_irq do the
+    //    rest, i.e. route first found IRQ in the returned priority vector
+    //    to the registered [unified] interrupt handler.
+    uint32_t  register l_vecH asm("r5");
+    //uint32_t  register l_vecL asm("r6");
+
+    //l_vecL = 0;
+    asm volatile ("lvd %[data], 0(%[addr]) \n" \
+                  : [data]"=r"(l_vecH) \
+                  : [addr]"r"(&(ext_irq_vectors_sgpe[iPrtyLvl][IDX_PRTY_VEC])) );
+}
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h
new file mode 100644
index 00000000..6b14ae09
--- /dev/null
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h
@@ -0,0 +1,140 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file   p9_sgpe_irq.h
+/// \brief  Shared and global definitions for SGPE H-codes.
+/// \owner  Michael Olsen   Email: cmolsen@us.ibm.com
+/// \owner  David Du        Email: daviddu@us.ibm.com
+
+//-------------------------------------------------------------------//
+//            DO NOT modify this file unless you're the owner        //
+//-------------------------------------------------------------------//
+
+// Notes:
+// - The only define names that should be changed/added/removed
+//   in this file are:
+//   - IRQ_VEC_PRTY(n>0)_SGPE(x)
+//   - IDX_PRTY_LVL_(task_abbr) and reflect in relevant H-code as well
+//   - All other define names are used in H-codes
+// - The variable names and actions in this file must perfectly match associated
+//   definitions in p9_sgpe_irq.c
+
+// We define four levels of TRACE outputs:
+// _INF:  Trace level used for main informational events.
+// _DBG:  Trace level used for expanded debugging.
+// _WARN: Trace level used when suspecious event happens.
+// _ERR:  Trace level at time of an error that leads to a halt.
+#define MY_TRACE_INF(...)   PK_TRACE("INF: "__VA_ARGS__);
+#ifdef DEV_DEBUG
+    #define MY_TRACE_DBG(...)   PK_TRACE("DBG: "__VA_ARGS__);
+#else
+    #define MY_TRACE_DBG(...)
+#endif
+#define MY_TRACE_WARN(...)  PK_TRACE("WARN: "__VA_ARGS__);
+#define MY_TRACE_ERR(...)   PK_TRACE("ERR: "__VA_ARGS__);
+
+#define TRUE  1
+#define FALSE 0
+
+// Priority Levels
+#define IDX_PRTY_LVL_HIPRTY         0
+#define IDX_PRTY_LVL_IPI3_HIGH      1
+#define IDX_PRTY_LVL_PIG_TYPE       2
+#define IDX_PRTY_LVL_IPI3_LOW       3
+#define IDX_PRTY_LVL_DISABLED       4
+#define IDX_PRTY_VEC                0
+#define IDX_MASK_VEC                1
+#define NUM_EXT_IRQ_PRTY_LEVELS  (uint8_t)(5)
+extern const uint64_t ext_irq_vectors_sgpe[NUM_EXT_IRQ_PRTY_LEVELS][2];
+
+// Group0: Non-task hi-prty IRQs (gpe3_error/checkstop)
+#define IRQ_VEC_PRTY0_SGPE   (uint64_t)(0x0080800000000000)
+// Group1: ipi3_high
+#define IRQ_VEC_PRTY1_SGPE   (uint64_t)(0x0000000800000000)
+// Group2: pig_type
+#define IRQ_VEC_PRTY2_SGPE   (uint64_t)(0x0000000000019000)
+// Group3: ipi3_low
+#define IRQ_VEC_PRTY3_SGPE   (uint64_t)(0x0000000000000004)
+// Group4: We should never detect these
+#define IRQ_VEC_PRTY4_SGPE   (uint64_t)(0x0000000000000000)
+//#define IRQ_VEC_PRTY4_SGPE   (uint64_t)(0xFF7F7FF7FFFE6FFB)
+
+#define IRQ_VEC_ALL_OUR_IRQS  ( IRQ_VEC_PRTY0_SGPE | \
+                                IRQ_VEC_PRTY1_SGPE | \
+                                IRQ_VEC_PRTY2_SGPE | \
+                                IRQ_VEC_PRTY3_SGPE )      // Note, we do not incl PRTY4 here!
+
+// This should be 0xFFFFFFFFFFFFFFFF
+#define IRQ_VEC_PRTY_CHECK  ( IRQ_VEC_PRTY0_SGPE | \
+                              IRQ_VEC_PRTY1_SGPE | \
+                              IRQ_VEC_PRTY2_SGPE | \
+                              IRQ_VEC_PRTY3_SGPE | \
+                              IRQ_VEC_PRTY4_SGPE )
+
+extern uint8_t       g_current_prty_level;
+extern uint8_t       g_oimr_stack[NUM_EXT_IRQ_PRTY_LEVELS];
+extern int           g_oimr_stack_ctr;
+extern uint64_t      g_oimr_override_stack[NUM_EXT_IRQ_PRTY_LEVELS];
+extern uint64_t      g_oimr_override;
+
+/// Restore a vector of interrupts by overwriting EIMR.
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_vec_restore(PkMachineContext* context)
+{
+    pk_critical_section_enter(context);
+
+    if (g_oimr_stack_ctr >= 0)
+    {
+
+        out32(OCB_OIMR0_CLR, (uint32_t)((IRQ_VEC_ALL_OUR_IRQS |
+                                         g_oimr_override_stack[g_oimr_stack_ctr]) >> 32));
+        out32(OCB_OIMR1_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS |
+                                        g_oimr_override_stack[g_oimr_stack_ctr]));
+        out32(OCB_OIMR0_OR,
+              (uint32_t)((ext_irq_vectors_sgpe[g_oimr_stack[g_oimr_stack_ctr]][IDX_MASK_VEC] |
+                          g_oimr_override) >> 32));
+        out32(OCB_OIMR1_OR,
+              (uint32_t)(ext_irq_vectors_sgpe[g_oimr_stack[g_oimr_stack_ctr]][IDX_MASK_VEC] |
+                         g_oimr_override));
+
+        // Restore the prty level tracker to the task that was interrupted, if any.
+        g_current_prty_level = g_oimr_stack[g_oimr_stack_ctr];
+        g_oimr_stack_ctr--;
+    }
+    else
+    {
+        PK_TRACE("Code bug: Messed up EIMR book keeping: g_oimr_stack_ctr=%d",
+                 g_oimr_stack_ctr);
+        pk_halt();
+    }
+
+    //pk_critical_section_exit(context);
+}
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c
index 3d7de3ff..b089e417 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c
@@ -25,6 +25,7 @@
 
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_enter_marks.h"
+#include "p9_sgpe_irq.h"
 
 SgpeStopRecord G_sgpe_stop_record =
 {
@@ -82,15 +83,16 @@ SgpeStopRecord G_sgpe_stop_record =
 void
 p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq)
 {
-    uint32_t cirq;
-    uint32_t qirq;
-    uint32_t cloop;
-    uint32_t qloop;
-    uint32_t cpending_t2 = 0;
-    uint32_t cpending_t3 = 0;
-    uint32_t qpending_t6 = 0;
-    uint32_t payload     = 0;
-    uint64_t scom_data;
+    PkMachineContext  ctx;
+    uint32_t          cirq;
+    uint32_t          qirq;
+    uint32_t          cloop;
+    uint32_t          qloop;
+    uint32_t          cpending_t2 = 0;
+    uint32_t          cpending_t3 = 0;
+    uint32_t          qpending_t6 = 0;
+    uint32_t          payload     = 0;
+    uint64_t          scom_data;
 
     //=========================
     MARK_TRAP(STOP_PIG_HANDLER)
@@ -297,6 +299,7 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq)
     {
         PK_TRACE_INF("Nothing to do, Clear Masks");
         out32(OCB_OIMR1_CLR, (BITS32(15, 2) | BIT32(19)));
+        pk_irq_vec_restore(&ctx);
     }
     else
     {
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h
index 62fe53cc..099829e2 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h
@@ -119,6 +119,7 @@
 /// IRQ#, TYPE, POLARITY, ENABLE
 ///
 #define APPCFG_EXT_IRQS_CONFIG \
+    OCCHW_IRQ_GPE2_HALT                   OCCHW_IRQ_TYPE_EDGE  OCCHW_IRQ_POLARITY_RISING  OCCHW_IRQ_MASKED \
     OCCHW_IRQ_CHECK_STOP_GPE3             OCCHW_IRQ_TYPE_EDGE  OCCHW_IRQ_POLARITY_RISING  OCCHW_IRQ_MASKED \
     OCCHW_IRQ_IPI3_HI_PRIORITY            OCCHW_IRQ_TYPE_EDGE  OCCHW_IRQ_POLARITY_RISING  OCCHW_IRQ_MASKED \
     OCCHW_IRQ_IPI3_LO_PRIORITY            OCCHW_IRQ_TYPE_EDGE  OCCHW_IRQ_POLARITY_RISING  OCCHW_IRQ_MASKED \
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
index 71e63f11..f2aad7fe 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
@@ -145,6 +145,9 @@ $(IMAGE)_COMMONFLAGS+= -DAPPCFG_OCC_INSTANCE_ID=3
 # (Change this to #4 for the 405 when we pull that in.)
 $(IMAGE)_COMMONFLAGS+= -DOCCHW_IRQ_ROUTE_OWNER=3
 
+# Force SGPE tasks to use the unified interrupt handler.
+$(IMAGE)_COMMONFLAGS+= -DUNIFIED_IRQ_HANDLER_GPE
+
 # This application will statically initialize 
 # it's external interrupt table using 
 # the table defined in p9_sgpe_main.c.
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk
index 8c44c7dc..30ad7e2e 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk
@@ -39,7 +39,8 @@ TOP-C-SOURCES = p9_sgpe_stop_entry.c \
                 p9_hcd_cache_scomcust.c \
                 p9_hcd_cache_occ_runtime_scom.c \
                 p9_hcd_cache_ras_runtime_scom.c \
-                p9_hcd_sgpe_boot_cme.c
+                p9_hcd_sgpe_boot_cme.c \
+                p9_sgpe_irq.c
 
 UTILS-SRC   = utils/p9_putringutils.C
 UTILS-SRC  += utils/plat_ring_traverse.C