STOP: Reduce CME Size

Change-Id: I327cad85f6b2cbfc89b712e4f20e51475dda5749
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38634
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

7 files changed, 92 insertions, 184 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c
index 4f127ae5..0cbd3676 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c
@@ -39,13 +39,13 @@ enum
 
 void instance_scan_init( )
 {
-    uint32_t l_cmePir = 0;
-
-    uint32_t l_bcLength = 0;
+    uint32_t     l_cmePir   = 0;
+    uint32_t     l_bcLength = 0;
     cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR);
+
     //Setting Mbase with start address of CME Inst rings in HOMER
-    uint32_t l_bceMbase = CME_IMAGE_CPMR_OFFSET + (pCmeImgHdr->g_cme_core_spec_ring_offset << 5);
-    uint32_t l_exId = ((in32(CME_LCL_FLAGS) & BITS32(CME_FLAG_EX_ID_BIT, 1)) >> EX_ID_SHIFT_POS);
+    uint32_t     l_bceMbase = CME_IMAGE_CPMR_OFFSET + (pCmeImgHdr->g_cme_core_spec_ring_offset << 5);
+    uint32_t     l_exId     = ((in32(CME_LCL_FLAGS) & BITS32(CME_FLAG_EX_ID_BIT, 1)) >> EX_ID_SHIFT_POS);
 
     asm volatile ( "mfspr %0, %1 \n\t" : "=r" (l_cmePir) : "i" (SPR_NUM_PIR));
 
@@ -53,11 +53,11 @@ void instance_scan_init( )
     //(1). Read CME PIR's CME instance bit field (bit 27 -bit 31)
     //(2). Bitwise shift left by one bit position.
     //(3). OR to LSB of CME PIR (bit 31), bit 26 of CME Flag Register
-
-    l_cmePir = ((( l_cmePir << 1 ) & CME_INST_ID_MASK) | l_exId);     // get CME instance number
+    l_cmePir = (((l_cmePir << 1) & CME_INST_ID_MASK) | l_exId); // get CME instance number
 
     //calculate start address of block copy and length of block copy
     l_bcLength = pCmeImgHdr->g_cme_max_spec_ring_length; // integral multiple of 32.
+
     //let us find out HOMER address where core specific scan rings reside.
     l_bceMbase = l_bceMbase + (( l_cmePir * l_bcLength ) << 5 );
     l_bceMbase = (l_bceMbase >> 5 );
@@ -67,42 +67,43 @@ void instance_scan_init( )
     // multiple of 32 and is populated by Hcode Image build while
     // building HOMER.
     uint32_t cmeSbase = pCmeImgHdr->g_cme_core_spec_ring_offset;
+
     PK_TRACE( "Start second block copy MBASE 0x%08x SBSE 0x%08x Len 0x%08x  CME Ist %d",
               l_bceMbase, cmeSbase, l_bcLength, l_cmePir );
 
-    startCmeBlockCopy( cmeSbase, l_bcLength, l_cmePir, PLAT_CME, BAR_INDEX_1, l_bceMbase );
+    startCmeBlockCopy( cmeSbase, l_bcLength, l_cmePir, BAR_INDEX_1, l_bceMbase );
 
-    PK_TRACE(" Done startCmeBlockCopy(instance_scan_init).");
+    PK_TRACE("Done startCmeBlockCopy(instance_scan_init).");
 }
 
 
 BceReturnCode_t isScanRingCopyDone( )
 {
     BceReturnCode_t l_rc;
-    uint32_t l_cmePir = 0;
-    uint32_t l_exId = ((in32(CME_LCL_FLAGS) & BITS32(CME_FLAG_EX_ID_BIT, 1)) >> EX_ID_SHIFT_POS);
+    uint32_t        l_cmePir = 0;
+    uint32_t        l_exId   = ((in32(CME_LCL_FLAGS) & BITS32(CME_FLAG_EX_ID_BIT, 1)) >> EX_ID_SHIFT_POS);
+
     asm volatile ( "mfspr %0, %1 \n\t" : "=r" (l_cmePir) : "i" (SPR_NUM_PIR));
 
     //CME's PIR gives only quad id. To determine the correct CME instance, follow the steps below:
     //(1). Read CME PIR's CME instance bit field (bit 27 -bit 31)
     //(2). Bitwise shift left by one bit position.
     //(3). OR to LSB of CME PIR (bit 31), bit 26 of CME Flag Register
-
-    l_cmePir = ((( l_cmePir << 1 ) & CME_INST_ID_MASK) | l_exId);     // get CME instance number
+    l_cmePir = ((( l_cmePir << 1 ) & CME_INST_ID_MASK) | l_exId); // get CME instance number
 
     while(1)
     {
-        l_rc = checkCmeBlockCopyStatus( l_cmePir, PLAT_CME );
+        l_rc = checkCmeBlockCopyStatus(l_cmePir);
 
-        if( BLOCK_COPY_SUCCESS == l_rc )
+        if(BLOCK_COPY_SUCCESS == l_rc)
         {
             break;
         }
 
-        if( BLOCK_COPY_FAILED == l_rc )
+        if(BLOCK_COPY_FAILED == l_rc)
         {
-            PK_TRACE( "failed to copy instance specific scan ring on cme %d",
-                      l_cmePir );
+            PK_TRACE("failed to copy instance specific scan ring on cme %d",
+                     l_cmePir);
             break;
         }
     }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
index 41a370b4..fb5a828a 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
@@ -458,7 +458,7 @@ p9_cme_stop_exit()
     PK_TRACE_DBG("Core Ensure Pcb Mux");
     p9_cme_acquire_pcbmux(core, 1);
 
-    PK_TRACE_INF("SX2.A: Start Core Clock");
+    PK_TRACE_INF("SX.2A: Core[%d] Start Clock", core);
     p9_hcd_core_startclocks(core);
 
     PK_TRACE("Clear CPPM PECE shadow via PECES");
@@ -848,7 +848,7 @@ STOP1_EXIT:
 
 #endif
 
-    PK_TRACE_INF("Core Release PCB Mux via SICR[10/11]");
+    PK_TRACE_DBG("Core Release PCB Mux via SICR[10/11]");
     p9_cme_release_pcbmux(core);
 
     PK_TRACE("Update STOP history: STOP exit completed, core ready");
diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
index 3ea9f47f..62c75b5f 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
@@ -233,7 +233,7 @@ void queuedScan(enum CME_CORE_MASKS i_core,
                     l_scomAddress = 0x00038000 | l_rotateCount;
                 }
 
-                getscom(0, CME_SCOM_ADDR(l_scomAddress, i_core, i_scom_op), &i_scanData);
+                CME_GETSCOM(l_scomAddress, i_core, i_scom_op, i_scanData);
             }// end of for loop
         }
         else if(SCAN == i_operation)
@@ -244,7 +244,7 @@ void queuedScan(enum CME_CORE_MASKS i_core,
             // Set the scan count to the actual value
             l_scomAddress |= i_opVal;
 
-            putscom(0, CME_SCOM_ADDR(l_scomAddress, i_core, i_scom_op), i_scanData);
+            CME_PUTSCOM(l_scomAddress, i_core, i_scanData);
         } // end of if(SCAN == i_operation)
     }
     while(0);
@@ -284,10 +284,10 @@ int rs4DecompressionSvc(
         }
 
         // Set up the scan region for the ring.
-        putscom(0, CME_SCOM_ADDR(0x00030005, i_core, i_scom_op), l_scanRegion);
+        CME_PUTSCOM(0x00030005, i_core, l_scanRegion);
 
         // Write a 64 bit value for header.
-        putscom(0, CME_SCOM_ADDR(0x0003E000, i_core, i_scom_op), 0xa5a5a5a5a5a5a5a5);
+        CME_PUTSCOM(0x0003E000, i_core, 0xa5a5a5a5a5a5a5a5);
 
 
         // Decompress the RS4 string and scan
@@ -531,7 +531,7 @@ int rs4DecompressionSvc(
             l_scomOp = CME_SCOM_NOP;
         }
 
-        getscom(0, CME_SCOM_ADDR(0x0003E000, i_core, l_scomOp), &l_readHeader);
+        CME_GETSCOM(0x0003E000, i_core, l_scomOp, l_readHeader);
 
         if(l_readHeader != 0xa5a5a5a5a5a5a5a5)
         {
@@ -547,7 +547,7 @@ int rs4DecompressionSvc(
         }
 
         // Clean scan region and type data
-        putscom(0, CME_SCOM_ADDR(0x00030005, i_core, l_scomOp), 0);
+        CME_PUTSCOM(0x00030005, i_core, 0);
     }
     while(0);
 
diff --git a/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.c b/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.c
index c0488d63..f66ecd39 100644
--- a/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.c
+++ b/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.c
@@ -42,92 +42,62 @@
 #include "p9_hcd_block_copy.h"
 #include "cme_register_addresses.h"
 
-enum
-{
-    CME_PER_QUAD    = 0x0002,
-};
-
-//------------------------------------------------------------------------------------
-
-void initCmeBceBarAddr( uint8_t i_barIndex, uint64_t i_barRegData, uint8_t i_cmePos )
-{
-    uint32_t l_bceBarAddr = (i_barIndex == 0 ) ? SCOM_ADDR_BCEBAR0 : SCOM_ADDR_BCEBAR1;
-    uint64_t l_bceBarData = 0;
-    int rc = 0;
-
-    uint8_t l_quadId = i_cmePos >> 1;
 
-    l_bceBarAddr = SGPE_SCOM_ADDR( l_bceBarAddr, l_quadId, (i_cmePos % 2) );
-
-    l_bceBarData = ( i_barRegData & 0x00FFFFFFFFF00000); //To extract bitss 8:43 from the i_barRegData
-    l_bceBarData |= (ENABLE_WR_SCOPE | ENABLE_RD_SCOPE | BLOCK_COPY_SIZE_1MB );
-    PPE_PUTSCOM(l_bceBarAddr, l_bceBarData);        // set the source address for block copy
-
-}
 
 //------------------------------------------------------------------------------------
 
 void startCmeBlockCopy( uint64_t i_cmeStartBlk, uint32_t i_blockLength, uint32_t i_cmePos,
-                        InitiatorPlat_t i_plat, uint8_t i_barIndex, uint32_t i_mbaseVal )
+                        uint8_t i_barIndex, uint32_t i_mbaseVal )
 {
-    int rc = 0;
+
+#if defined(__PPE_CME) || defined(__PPE_SGPE)
 
     uint64_t l_bceStatusData = ((START_BLOCK_COPY)       |   // starts block copy operation
                                 (RD_FROM_HOMER_TO_SRAM)  |   // sets direction of copy HOMER to CME SRAM
-                                ((i_barIndex == 0) ? SEL_BCEBAR0 : SEL_BCEBAR1) | // BAR register to be used for accessing main memory base
+                                // BAR register to be used for accessing main memory base
+                                ((i_barIndex == 0) ? SEL_BCEBAR0 : SEL_BCEBAR1) |
                                 (SET_RD_PRIORITY_0)      |   // No priority set
                                 ((i_cmeStartBlk & 0x0000FFF ) << SBASE_SHIFT_POS) |  //copy page to this SRAM Block.
-                                (((uint64_t) i_blockLength & 0x00007FF) << NUM_BLK_SHIFT_POS ) | // number of blocks to be copied
+                                // number of blocks to be copied
+                                (((uint64_t) i_blockLength & 0x00007FF) << NUM_BLK_SHIFT_POS ) |
                                 (((uint64_t) i_mbaseVal & 0x00000000003FFFFF) ));
 
-    if( PLAT_CME == i_plat )
-    {
-        // for CME platform use local address for register BCECSR.
-        // using BCECSR SCOM address will not work as it is meant
-        // for entities external to CME.
-        uint32_t l_cmeBceAddr = CME_LCL_BCECSR;
-        out64( l_cmeBceAddr, l_bceStatusData );
-    }
-    else if( PLAT_SGPE == i_plat )
-    {
-        //getting quad id by dividing cme pos with 2
-        uint8_t l_quadId = i_cmePos >> 1;
+#endif
 
-        uint32_t l_sgpeBceAddr = SGPE_SCOM_ADDR( SCOM_ADDR_BCEBCSR, l_quadId,
-                                 (i_cmePos % 2) );
+#ifdef __PPE_CME
+    // for CME platform use local address for register BCECSR.
+    // using BCECSR SCOM address will not work as it is meant
+    // for entities external to CME.
+    out64(CME_LCL_BCECSR, l_bceStatusData);
+#endif
 
-        PPE_PUTSCOM(l_sgpeBceAddr, l_bceStatusData );
-    }
+#ifdef __PPE_SGPE
+    //getting quad id by dividing cme pos with 2
+    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_BCECSR, (i_cmePos >> 1), (i_cmePos % 2)), l_bceStatusData);
+#endif
 }
 
 //------------------------------------------------------------------------------------
 
-BceReturnCode_t checkCmeBlockCopyStatus( uint32_t i_cmePos, InitiatorPlat_t i_plat )
+BceReturnCode_t checkCmeBlockCopyStatus( uint32_t i_cmePos)
 {
     BceReturnCode_t l_bcRetCode = BLOCK_COPY_IN_PROGRESS;
 
     do
     {
         uint64_t l_bceStatusData = 0;
-        int rc = 0;
 
-        if( PLAT_CME == i_plat )
-        {
-            // for CME platform use local address for register BCECSR.
-            // using BCECSR SCOM address will not work as it is meant
-            // for entities external to CME.
-            uint32_t l_cmeBcelAddr = CME_LCL_BCECSR;
-            l_bceStatusData = in64(l_cmeBcelAddr);
-        }
-        else if( PLAT_SGPE == i_plat )
-        {
-            // getting quad id by dividing cme pos with 2
-            uint8_t l_quadId = i_cmePos >> 1;
+#ifdef __PPE_CME
+        // for CME platform use local address for register BCECSR.
+        // using BCECSR SCOM address will not work as it is meant
+        // for entities external to CME.
+        l_bceStatusData = in64(CME_LCL_BCECSR);
+#endif
 
-            uint32_t l_sgpeBceAddr = SGPE_SCOM_ADDR( SCOM_ADDR_BCEBCSR, l_quadId, (i_cmePos % 2) );
-            // SGPE reading block copy engine status of CME
-            PPE_GETSCOM(l_sgpeBceAddr, l_bceStatusData);
-        }
+#ifdef __PPE_SGPE
+        // SGPE reading block copy engine status of CME
+        GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_BCECSR, (i_cmePos >> 1), (i_cmePos % 2)), l_bceStatusData);
+#endif
 
         if( CHECK_ERROR & l_bceStatusData )     // checking if block copy engine reported an error.
         {
diff --git a/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.h b/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.h
index c61caa8c..cf78689e 100644
--- a/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.h
+++ b/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.h
@@ -55,23 +55,6 @@ typedef enum
     BLOCK_COPY_IN_PROGRESS  = 4,
 } BceReturnCode_t;
 
-//Platforms that can request block copy transfer.
-typedef enum
-{
-    PLAT_NA     =   0,
-    PLAT_CME    =   1,
-    PLAT_SGPE   =   2,
-} InitiatorPlat_t;
-
-// SCOM addresses associated with a CME BCE.
-typedef enum
-{
-    SCOM_ADDR_BCEBAR0   =   0x10012030,
-    SCOM_ADDR_BCEBAR1   =   0x10012031,
-    SCOM_ADDR_BCEBCSR   =   0x1001200F,
-    SCOM_ADDR_PBABAR0   =   0x05012B00,
-} ScomAddrList_t;
-
 // Bit shifts needed for various fields of CME's BCESCR register
 enum
 {
@@ -81,23 +64,6 @@ enum
     CME_BASE_ADDRESS    =   0x10012000,
 };
 
-#define SGPE_SCOM_ADDR(addr, quad, ex) ( addr | CME_BASE_ADDRESS | (quad << 24) | (ex << 10) )
-
-#define PPE_GETSCOM(addr, data)                                        \
-    rc = getscom(0, addr, &data);                                      \
-    if (rc) {                                                          \
-        PK_TRACE("getscom@%d failed w/rc=0x%08x",                      \
-                 addr, rc);                                            \
-        pk_halt();                                                     \
-    }
-
-#define PPE_PUTSCOM(addr, data)                                        \
-    rc = putscom(0, addr, data);                                       \
-    if (rc) {                                                          \
-        PK_TRACE("putscom@%d failed w/rc=0x%08x",                      \
-                 addr, rc);         \
-        pk_halt();                                                     \
-    }
 /// @brief accomplishes block copy from mainstore to CME SRAM.
 /// @param [in]  i_cmeStartBlk   Block no associated with CME SRAM( a block is 32B )
 /// @param [in]  i_blockLength   number of block to be transferred.
@@ -107,8 +73,7 @@ enum
 /// @note  It is a non blocking function. It doesn't poll the status and error bits.
 ///        It is expected to be called by CME and SGPE only.
 void startCmeBlockCopy( uint64_t i_cmeStartBlk, uint32_t i_blockLength,
-                        uint32_t i_cmePos, InitiatorPlat_t i_plat, uint8_t i_barIndex,
-                        uint32_t i_mbaseVal );
+                        uint32_t i_cmePos, uint8_t i_barIndex, uint32_t i_mbaseVal );
 
 /// @brief accomplishes block copy from mainstore to CME SRAM.
 /// @param [in]  i_cmePos        Position of CME in the P9 chip.
@@ -116,14 +81,6 @@ void startCmeBlockCopy( uint64_t i_cmeStartBlk, uint32_t i_blockLength,
 /// @retVal BLOCK_COPY_SUCCESS is block succeeds, return code otherwise.
 /// @note  It is a non blocking function. It doesn't poll the status and error bits.
 ///        It is expected to be called by CME and SGPE only.
-BceReturnCode_t checkCmeBlockCopyStatus( uint32_t i_cmePos, InitiatorPlat_t i_plat );
+BceReturnCode_t checkCmeBlockCopyStatus( uint32_t i_cmePos);
 
-/// @brief initializes the BCENARn register.
-/// @param [in]  i_plat     platform calling CME's block copy engine.
-/// @param [in]  i_barIndex 0 for BCEBAR0 and 1 for BCEBAR1
-/// @param [in]  i_barRegData address to be written to BCEBARn
-/// @param [in]  i_cmePos     position of CME.
-/// @note  No PPE other than SGPE is expected to call this function. It is expected to
-///        be called by SGPE only.
-void initCmeBceBarAddr( uint8_t i_barIndex, uint64_t i_barRegData, uint8_t i_cmePos );
 #endif
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
index c710920e..f7ec46c7 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
@@ -36,16 +36,11 @@
 enum
 {
     ZERO                        =   0,
-    MAX_CME_PER_CHIP            =   MAX_EXES,
     CHECK_BIT                   =   0x8000, // input vector is big endian
-    SCOM_ADDR_CME_FLAGS         =   0x10012020,
-    SCOM_ADDR_CME_FLAGS_CLR     =   SCOM_ADDR_CME_FLAGS + 1,
-    SCOM_ADDR_CME_FLAGS_SET     =   SCOM_ADDR_CME_FLAGS + 2,
     CPMR_POSITION               =   0x00200000,
     CME_IMG_HDR_OFFSET_POS      =   0x20,
     CME_HCODE_LEN_POS           =   0x24,
     CME_FLAG_SHIFT_POS          =   (63 - 31), // @bug: was 0x1E
-    SCOM_ADDR_CME_XCR           =   0x10012010,
     RESUME_PPE_OPERATION        =   0x2000000000000000ll,   // Resume PPE
     HARD_RESET_PPE              =   0x6000000000000000ll,   // Hard Reset PPE
     SBASE_FIRST_BLOCK_COPY      =   0,  // corresponds to address 0xFFFF8000
@@ -53,21 +48,14 @@ enum
     EVEN_CORE_ACTIVE            =   0x02,
     ODD_CORE_ACTIVE             =   0x01,
     BOTH_CORE_ACTIVE            =   0x03,
-    BCEBAR0                     =   0,
-    BCEBAR1                     =   1,
     SCOM_ADDR_CCSR              =   0x0006C090,
     CHECK_BIT_DWORD             =   0x8000000000000000ll,
     SET_ADDR_MSB                =   0x80000000,
     CME_STOP_READY              =   0x8000000000000000ll,
-    SCOM_ADDR_CORE_CPMMR        =   0x200F0106,
-    SCOM_ADDR_CORE_CPMMR_CLR    =   SCOM_ADDR_CORE_CPMMR + 1,
-    SCOM_ADDR_CORE_CPMMR_OR     =   SCOM_ADDR_CORE_CPMMR + 2,
     WKUP_NOTIFY_SELECT          =   0x0004000000000000,
     CME_BOOT_TIMEOUT            =   0x32,
     CME_BCE_TIMEOUT             =   0xB0,
     WRITE_CLR_ALL               =   0xFFFFFFFFF,
-    SCOM_ADDR_CME_FWMODE_CLR    =   0x1001203B,
-    SCOM_ADDR_CME_FWMODE_OR     =   0x1001203C,
     BCESCR_OVERRIDE_ENABLE      =   0x1000000000000000,
     CME_BLOCK_READ_SIZE         =   0x20,
 };
@@ -101,19 +89,16 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
 
     do
     {
-        int rc = 0;
         uint64_t l_dataReg = 0;
         uint64_t l_dataCCSR = 0;
-        PPE_GETSCOM(SCOM_ADDR_CCSR, l_dataCCSR);
+        GPE_GETSCOM(SCOM_ADDR_CCSR, l_dataCCSR);
 
         uint8_t l_corePos = 0;
         uint8_t l_cmeIndex = 0;
-        uint8_t activeCmeList[MAX_CME_PER_CHIP] = {ZERO};
+        uint8_t activeCmeList[MAX_CMES_PER_CHIP] = {ZERO};
         uint8_t activeCmeCnt = 0;
-        uint8_t quadId = 0;
-        uint32_t l_scomAddr = 0;
 
-        for( l_cmeIndex = 0; l_cmeIndex < MAX_CME_PER_CHIP; l_cmeIndex++ )
+        for( l_cmeIndex = 0; l_cmeIndex < MAX_CMES_PER_CHIP; l_cmeIndex++ )
         {
             // Step 1. Screen Valid CME for boot
 
@@ -153,16 +138,13 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
                 continue;
             }
 
-            quadId = l_cmeIndex >> 1;
             activeCmeList[l_cmeIndex] = coreCnt;
 
             // core is available and CME can attempt to boot it.
             // From SGPE platform, let us first get control of Block copy engine.
-            l_scomAddr = SGPE_SCOM_ADDR( SCOM_ADDR_CME_FWMODE_OR, //FWMODE -> LMCR
-                                         quadId,
-                                         (l_cmeIndex % 2));
-
-            PPE_PUTSCOM( l_scomAddr, BCESCR_OVERRIDE_ENABLE ); //Disables BCE access via CME's Local register.
+            // Disables BCE access via CME's Local register.
+            GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR,
+                                          (l_cmeIndex >> 1), (l_cmeIndex % 2)), BCESCR_OVERRIDE_ENABLE);
 
 
             // -----------------------------------------------------------------
@@ -178,15 +160,16 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
             //of chip' HOMER. This offset is updated in a specific field of
             //CPMR Header area of chip's HOMER. Let us read that field and
             //find out the offset.
-            PK_TRACE("SCOM addr Pbabar0: 0x%x", SCOM_ADDR_PBABAR0);
             uint64_t l_cpmrAddr = 0;
-            PPE_GETSCOM(SCOM_ADDR_PBABAR0, l_cpmrAddr); // get start of HOMER for the chip.
+            GPE_GETSCOM(PBA_BAR0, l_cpmrAddr); // get start of HOMER for the chip.
             l_cpmrAddr += CPMR_POSITION; // offset to CPMR
 
             //Reading CPMR header to determine :
             //1. start of CME Image
             //2. Length of first block copy
-            HomerImgDesc_t* pCpmrHdrAddr = (HomerImgDesc_t*)(CPMR_POSITION | SET_ADDR_MSB);   // Set MSB to point OCI to PBA
+            //Set MSB to point OCI to PBA
+            HomerImgDesc_t* pCpmrHdrAddr = (HomerImgDesc_t*)(CPMR_POSITION | SET_ADDR_MSB);
+
             PK_TRACE("Magic Number [ 0:31]: 0x%08x", ((pCpmrHdrAddr->cpmrMagicWord & 0xffffffff00000000) >> 32));
             PK_TRACE("Magic Number [32:63]: 0x%08x", ((pCpmrHdrAddr->cpmrMagicWord & 0x00000000ffffffff)));
 
@@ -226,7 +209,9 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
             // update BCEBAR0 with start of CME hcode region
             // update BCEBAR1 with start of CME's instance specific ring region
 
-            initCmeBceBarAddr( BCEBAR0, l_cpmrAddr, l_cmeIndex );
+            GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_BCEBAR0, (l_cmeIndex >> 1), (l_cmeIndex % 2)),
+                        ((l_cpmrAddr & 0x00FFFFFFFFF00000) |
+                         (ENABLE_WR_SCOPE | ENABLE_RD_SCOPE | BLOCK_COPY_SIZE_1MB)));
 
             // -----------------------------------------------------------------
             // -----------------------------------------------------------------
@@ -234,7 +219,9 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
             // -----------------------------------------------------------------
             // -----------------------------------------------------------------
 
-            initCmeBceBarAddr( BCEBAR1, l_cpmrAddr , l_cmeIndex );
+            GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_BCEBAR1, (l_cmeIndex >> 1), (l_cmeIndex % 2)),
+                        ((l_cpmrAddr & 0x00FFFFFFFFF00000) |
+                         (ENABLE_WR_SCOPE | ENABLE_RD_SCOPE | BLOCK_COPY_SIZE_1MB)));
 
             // -----------------------------------------------------------------
             // -----------------------------------------------------------------
@@ -244,8 +231,8 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
             PK_TRACE("Before startCmeBlockCopy l_blockCopyLength in bytes 0x%08x l_cmeIndex: %d l_hdrToSectionOffset 0x%x",
                      l_blockCopyLength, l_cmeIndex, l_hdrToSectionOffset);
 
-            startCmeBlockCopy( SBASE_FIRST_BLOCK_COPY, l_blockCopyLength, l_cmeIndex,
-                               PLAT_SGPE, 0, l_hdrToSectionOffset  );
+            startCmeBlockCopy(SBASE_FIRST_BLOCK_COPY, l_blockCopyLength,
+                              l_cmeIndex, BAR_INDEX_0, l_hdrToSectionOffset);
 
             activeCmeCnt++;
             PK_TRACE("activeCmeCnt: %d", activeCmeCnt);
@@ -268,7 +255,7 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
         while(cmeInitSuccessCnt != activeCmeCnt)
         {
             // we have started first block copy for every functional CME. Let us check if block copy is done or not.
-            for( l_cmeIndex = 0; l_cmeIndex < MAX_CME_PER_CHIP; l_cmeIndex++ )
+            for( l_cmeIndex = 0; l_cmeIndex < MAX_CMES_PER_CHIP; l_cmeIndex++ )
             {
                 // check if block copy was started on this CME.
                 if( INACTIVE_CORE == activeCmeList[l_cmeIndex] )
@@ -285,7 +272,7 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
                     continue;
                 }
 
-                l_copyStatus = checkCmeBlockCopyStatus( l_cmeIndex, PLAT_SGPE );
+                l_copyStatus = checkCmeBlockCopyStatus( l_cmeIndex );
 
                 if(BLOCK_COPY_IN_PROGRESS == l_copyStatus )
                 {
@@ -303,7 +290,6 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
                 }
 
                 l_retCode = BLOCK_COPY_SUCCESS; // atleast one CME's block copy engine was success.
-                quadId = (l_cmeIndex >> 1);
 
                 // -----------------------------------------------------------------
                 // -----------------------------------------------------------------
@@ -320,23 +306,20 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
                 // SGPE now should release the control of block copy engine.
                 // Once it kicks off CME, during its initialization, CME will try to block
                 // copy its instance specific scan rings. For that to succeed, SGPE must clear
-                // BCECSR_OVERRIDE_EN bit in CME_FWMODE register.
+                // BCECSR_OVERRIDE_EN bit in CME_LMCR register.
 
-                l_scomAddr = SGPE_SCOM_ADDR( SCOM_ADDR_CME_FWMODE_CLR,
-                                             quadId,
-                                             (l_cmeIndex % 2));
-                PPE_PUTSCOM( l_scomAddr, BCESCR_OVERRIDE_ENABLE ); // release control back to local CME BCECSR
+                // release control back to local CME BCECSR
+                GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_CLR,
+                                              (l_cmeIndex >> 1), (l_cmeIndex % 2)), BCESCR_OVERRIDE_ENABLE);
 
                 //Writing to CME's XCR to Hard Reset it
-                l_scomAddr = SGPE_SCOM_ADDR(SCOM_ADDR_CME_XCR,
-                                            quadId,
-                                            (l_cmeIndex % 2));
-
-                PPE_PUTSCOM( l_scomAddr, HARD_RESET_PPE );
+                GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIXCR,
+                                              (l_cmeIndex >> 1), (l_cmeIndex % 2)), HARD_RESET_PPE);
 
                 // Kick off CME by giving resume command through PPE External Control Register
                 // Writing to XCR to resume PPE operation
-                PPE_PUTSCOM( l_scomAddr, RESUME_PPE_OPERATION );
+                GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIXCR,
+                                              (l_cmeIndex >> 1), (l_cmeIndex % 2)), RESUME_PPE_OPERATION);
                 cmeInitSuccessCnt++;
                 cmeBootedList = cmeBootedList | l_cmeBootedBit;
 
@@ -345,11 +328,11 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
             PPE_WAIT_CORE_CYCLES(256);
         } //while(l_bceCnt != activeCmeCnt)
 
-        PK_TRACE("BCE done and resume scom_addr: 0x%08x", l_scomAddr);
+        PK_TRACE("BCE Done");
 
         // -----------------------------------------------------------------
         // -----------------------------------------------------------------
-        // Step 7, 8,9 is accomplished on CME platform
+        // Step 7, 8, 9 is accomplished on CME platform
         // -----------------------------------------------------------------
         // -----------------------------------------------------------------
 
@@ -367,7 +350,7 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
 
             while(l_cmeRdyCnt != activeCmeCnt)
             {
-                for( l_cmeIndex = 0; l_cmeIndex < MAX_CME_PER_CHIP; l_cmeIndex++ )
+                for( l_cmeIndex = 0; l_cmeIndex < MAX_CMES_PER_CHIP; l_cmeIndex++ )
                 {
                     if( INACTIVE_CORE == activeCmeList[l_cmeIndex] )
                     {
@@ -383,12 +366,8 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
                     }
 
                     //Read CME Flag register to check STOP RDY
-                    quadId = (l_cmeIndex >> 1);
-                    l_scomAddr = SGPE_SCOM_ADDR( SCOM_ADDR_CME_FLAGS,
-                                                 quadId,
-                                                 (l_cmeIndex % 2) );
-
-                    PPE_GETSCOM( l_scomAddr, l_dataReg );
+                    GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS,
+                                                  (l_cmeIndex >> 1), (l_cmeIndex % 2)), l_dataReg);
 
                     if (!(l_dataReg & CME_STOP_READY))
                     {
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
index 6561d55f..3ef5ab9f 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/stop_gpe.mk
@@ -169,6 +169,7 @@ $(IMAGE)_COMMONFLAGS+= -DPK_TRACE_SUPPORT=1
 $(IMAGE)_COMMONFLAGS+= -DUSE_PK_APP_CFG_H=1
 $(IMAGE)_COMMONFLAGS+= -D__PK__=1
 $(IMAGE)_COMMONFLAGS+= -D__PPE_PLAT
+$(IMAGE)_COMMONFLAGS+= -D__PPE_SGPE
 $(IMAGE)_COMMONFLAGS+= -D__PPE__
 
 # Options for FAPI2