STOP/PState: SGPE/PGPE Error Handling Support

Upon PGPE Halt
1) SGPE performs STOP Recovery Trigger to set
a malfunction alert and removes PGPE IPCs
from wake-up decisions.
2) CME is interrupted by QPPM OCC Heartbeat
Lost that PGPE stopped updating

Upon SGPE Halt
1) PGPE moves to Psafe
2) PGPE performs STOP Recovery Trigger to set
a malfunction alert.

This commit also includes SGPE Panic Code
Cleanup such as debug halt support.
However PGPE Panic Code Cleanup is dealt in
a different commit

Key_Cronus_Test=PM_REGRESS

Change-Id: Iffedd872b3e417ad0bbe937bcb130801ec119d92
Original-Change-Id: I893aa1ef21d2f684722b8c10dbbeb92b9505c1c4
CQ: SW410252
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49275
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

6 files changed, 83 insertions, 31 deletions

diff --git a/import/chips/p9/common/pmlib/include/registers/ocb_register_addresses.h b/import/chips/p9/common/pmlib/include/registers/ocb_register_addresses.h
index 8b236d36..4542786b 100644
--- a/import/chips/p9/common/pmlib/include/registers/ocb_register_addresses.h
+++ b/import/chips/p9/common/pmlib/include/registers/ocb_register_addresses.h
@@ -104,10 +104,10 @@
 #define OCB_OCCFLG 0xc0060450
 #define OCB_OCCFLG_CLR 0xc0060458
 #define OCB_OCCFLG_OR 0xc0060460
+#define OCB_OCCFLG2 0xC0060C50
+#define OCB_OCCFLG2_CLR 0xC0060C58
+#define OCB_OCCFLG2_OR 0xC0060C60
 #define OCB_OCCHBR 0xc0060478
-#define OCB_OCCFLG2         0xc0060c50
-#define OCB_OCCFLG2_CLR     0xc0060c58
-#define OCB_OCCFLG2_OR      0xc0060c60
 #define OCB_CCSR 0xc0060480
 #define OCB_CCSR_CLR 0xc0060488
 #define OCB_CCSR_OR 0xc0060490
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h b/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h
index 9d44826a..753b956d 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h
@@ -50,12 +50,12 @@ CME_UIH_PHANTOM_INTERRUPT           = 0x1c04,
 CME_STOP_NO_PARTIAL_GOOD_CORE       = 0x1c05,
 CME_STOP_PUTRING_HEADER_ERROR       = 0x1c06,
 CME_STOP_BCE_CORE_RING_FAILED       = 0x1c07,
-//_UNUSED_1c08                      = 0x1c08,
-//_UNUSED_1c09                      = 0x1c09,
-//_UNUSED_1c0a                      = 0x1c0a,
-//_UNUSED_1c0d                      = 0x1c0d,
-//_UNUSED_1c1c                      = 0x1c1c,
-//_UNUSED_1c1d                      = 0x1c1d,
+CME_DEBUGGER_DETECTED               = 0x1c08,
+CME_DEBUG_TRIGGER_DETECTED          = 0x1c09,
+CME_QUAD_CHECKSTOP_DETECTED         = 0x1c0a,
+CME_PVREF_FAIL_DETECTED             = 0x1c0d,
+CME_OCC_HEARTBEAT_LOST_DETECTED     = 0x1c1c,
+CME_CORE_CHECKSTOP_DETECTED         = 0x1c1d,
 CME_BAD_DD_LEVEL                    = 0x1c1e,
 //_UNUSED_1c1f                      = 0x1c1f,
 //
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
index d1a12e6e..8346c9e0 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
@@ -30,6 +30,7 @@
 #include "ppe42_cache.h"
 #include "p9_pgpe_gppb.h"
 #include "p9_pgpe_optrace.h"
+#include "p9_stop_recovery_trigger.h"
 
 extern TraceData_t G_pgpe_optrace_data;
 //
@@ -97,13 +98,21 @@ void p9_pgpe_irq_handler_occ_error(void* arg, PkIrqId irq)
 //
 //SGPE Halt Interrupt Handler
 //
-//\TODO: RTC 164107
-//Implement this handler. Implement Safe Mode
 void p9_pgpe_irq_handler_sgpe_halt(void* arg, PkIrqId irq)
 {
     PK_TRACE_DBG("SGPE Halt: Enter");
     PkMachineContext  ctx;
 
+    out32(OCB_OISR0_CLR, BIT32(8));
+    //\TODO: RTC 164107
+    //Implement Safe Mode
+    //p9_pgpe_pstate_safe_mode();
+
+    if (in32(OCB_OCCFLG2) & BIT32(STOP_RECOVERY_TRIGGER_ENABLE))
+    {
+        p9_stop_recovery_trigger();
+    }
+
     pk_irq_vec_restore(&ctx);//Restore interrupts
     PK_TRACE_DBG("SGPE Halt: Exit");
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index 2c94e0e9..1560375f 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -39,7 +39,6 @@ extern SgpeStopRecord G_sgpe_stop_record;
 void
 p9_sgpe_stop_entry()
 {
-    uint32_t     entry_ongoing[2]  = {0, 0};
     uint32_t     l3_purge_aborted  = 0;
     uint32_t     ex                = 0;
     uint32_t     ex_mask           = 0;
@@ -372,6 +371,40 @@ p9_sgpe_stop_entry()
         PK_TRACE("+++++ +++++ EX STOP ENTRY [LEVEL 8-10] +++++ +++++");
         // ------------------------------------------------------------------------
 
+        if (ex & FST_EX_IN_QUAD)
+        {
+            cloop = 0;
+        }
+        else
+        {
+            cloop = CORES_PER_EX;
+        }
+
+        if (ex & SND_EX_IN_QUAD)
+        {
+            climit = CORES_PER_QUAD;
+        }
+        else
+        {
+            climit = CORES_PER_EX;
+        }
+
+        for(; cloop < climit; cloop++)
+        {
+            cindex = (qloop << 2) + cloop;
+
+            // Check partial good core
+            if (!(G_sgpe_stop_record.group.core[VECTOR_CONFIG] & BIT32(cindex)))
+            {
+                continue;
+            }
+
+            PK_TRACE("Update STOP history on core[%d]: continue on entering", cindex);
+            scom_data.words.lower = 0;
+            scom_data.words.upper = SSH_ENTRY_IN_SESSION;
+            GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, cindex, 0, scom_data.value);
+        }
+
         PK_TRACE_INF("SE.8A: Quad[%d] EX_L2[%d] Stopping L2 Clocks", qloop, ex);
 
         PK_TRACE("Acquire cache clock controller atomic lock");
@@ -489,9 +522,6 @@ p9_sgpe_stop_entry()
         {
             cloop = 0;
             G_sgpe_stop_record.state[qloop].act_state_x0 = STOP_LEVEL_8;
-            entry_ongoing[0] =
-                G_sgpe_stop_record.state[qloop].req_state_x0 < STOP_LEVEL_11 ?
-                STOP_TRANS_COMPLETE : STOP_TRANS_ENTRY;
         }
         else
         {
@@ -502,9 +532,6 @@ p9_sgpe_stop_entry()
         {
             climit = CORES_PER_QUAD;
             G_sgpe_stop_record.state[qloop].act_state_x1 = STOP_LEVEL_8;
-            entry_ongoing[1] =
-                G_sgpe_stop_record.state[qloop].req_state_x1 < STOP_LEVEL_11 ?
-                STOP_TRANS_COMPLETE : STOP_TRANS_ENTRY;
         }
         else
         {
@@ -521,12 +548,9 @@ p9_sgpe_stop_entry()
                 continue;
             }
 
-            // request levle already set by CME
-            // shift by 2 == times 4, which is cores per quad
             PK_TRACE("Update STOP history on core[%d]: in stop level 8", cindex);
             scom_data.words.lower = 0;
-            scom_data.words.upper = (SSH_ACT_LV8_COMPLETE |
-                                     (((uint32_t)entry_ongoing[cloop >> 1]) << SHIFT32(3)));
+            scom_data.words.upper = SSH_ACT_LV8_COMPLETE;
 
 #if !DISABLE_STOP8
 
@@ -571,16 +595,27 @@ p9_sgpe_stop_entry()
             continue;
         }
 
-        ex = G_sgpe_stop_record.group.expg[qloop];
-
         // ------------------------------------------------------------------------
         PK_TRACE("+++++ +++++ QUAD STOP ENTRY [LEVEL 11-15, L3 PURGE] +++++ +++++");
         // ------------------------------------------------------------------------
 
-        PK_TRACE_INF("SE.11A: Quad[%d] EX_PG[%d] Shutting Cache Down", qloop, ex);
+        ex = G_sgpe_stop_record.group.expg[qloop];
 
-        PK_TRACE("Update QSSR: stop_entry_ongoing");
-        out32(OCB_QSSR_OR, BIT32(qloop + 20));
+        for(cloop = 0; cloop < CORES_PER_QUAD; cloop++)
+        {
+            cindex = (qloop << 2) + cloop;
+
+            // Check partial good core
+            if (!(G_sgpe_stop_record.group.core[VECTOR_CONFIG] & BIT32(cindex)))
+            {
+                continue;
+            }
+
+            PK_TRACE("Update STOP history on core[%d]: continue entering", cindex);
+            scom_data.words.lower = 0;
+            scom_data.words.upper = SSH_ENTRY_IN_SESSION;
+            GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, cindex, 0, scom_data.value);
+        }
 
         PK_TRACE("Update STOP history on quad[%d]: update request stop level", qloop);
         scom_data.words.lower = 0;
@@ -588,6 +623,11 @@ p9_sgpe_stop_entry()
                                  ((uint32_t)G_sgpe_stop_record.state[qloop].req_state_q << SHIFT32(7)));
         GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value);
 
+        PK_TRACE("Update QSSR: stop_entry_ongoing");
+        out32(OCB_QSSR_OR, BIT32(qloop + 20));
+
+        PK_TRACE_INF("SE.11A: Quad[%d] EX_PG[%d] Shutting Cache Down", qloop, ex);
+
         //==================================
         MARK_TAG(SE_PURGE_L3, (32 >> qloop))
         //==================================
@@ -851,6 +891,7 @@ p9_sgpe_stop_entry()
 
         if ((!ipc_quad_entry) &&
             (in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
+            G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED &&
             G_sgpe_stop_record.group.quad[VECTOR_ENTRY]) // entry into STOP11
         {
             //============================
@@ -1300,6 +1341,7 @@ p9_sgpe_stop_entry()
     /// @todo RTC166577
     /// this block can be done as early as after stop cache clocks
     if ((in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
+        G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED &&
         G_sgpe_stop_record.group.quad[VECTOR_ENTRY])
     {
         // Note: if all quads aborted on l3 purge, the quad list will be 0s;
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
index 9afa7f57..fcc7dd57 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
@@ -449,6 +449,7 @@ p9_sgpe_stop_exit()
     //   will write the QPPM_DPLL_FREQ register before responding.
 
     if ((in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
+        G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED &&
         G_sgpe_stop_record.group.quad[VECTOR_EXIT])
     {
         ipc_exit_quad = 1;
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/sgpe_panic_codes.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/sgpe_panic_codes.h
index 4fb7825c..a6f46875 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/sgpe_panic_codes.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/sgpe_panic_codes.h
@@ -87,10 +87,10 @@ SGPE_STOP_ENTRY_STOP11_RESCLK_ON    = 0x1e06,
 //_UNUSED_1e08                      = 0x1e08,
 //_UNUSED_1e09                      = 0x1e09,
 SGPE_IPC_UPDATE_ACTIVE_QUAD_BAD_LIST = 0x1e0a,
-//_UNUSED_1e0d                      = 0x1e0d,
-//_UNUSED_1e1c                      = 0x1e1c,
-//_UNUSED_1e1d                      = 0x1e1d,
-//_UNUSED_1e1e                      = 0x1e1e,
+SGPE_PGPE_HALT_DETECTED             = 0x1e0d,
+SGPE_SYSTEM_CHECKSTOP_DETECTED      = 0x1e1c,
+SGPE_PIG_TYPE5_PAYLOAD_INVALID      = 0x1e1d,
+SGPE_PIG_TYPE5_CME_ERROR            = 0x1e1e,
 SGPE_STOP_ENTRY_TRAP_INJECT         = 0x1e1f,
 
 SGPE_STOP_EXIT_VCS_STOPCLK_FAILED   = 0x1f00, // NDD1