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| author | Sudheendra K Srivathsa <sudheendraks@in.ibm.com> | 2017-01-31 18:24:49 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:28:47 -0500 |
| commit | 5c2a5facbe7d2649333a2255eac80fc549ce4bfc (patch) | |
| tree | 8b17893fca76d3d83332649f0119c77e803055b0 | |
| parent | 47a91e1bb2425b14f9d7738f578c8bcd977579b4 (diff) | |
| download | talos-hcode-5c2a5facbe7d2649333a2255eac80fc549ce4bfc.tar.gz talos-hcode-5c2a5facbe7d2649333a2255eac80fc549ce4bfc.zip | |
Core Chiplet Scan0 Mode changes
Change-Id: I8eee413034e3d030e7ab9d5d43c090d7a8714ef7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35735
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c index 9ee7436f..62ad66df 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c @@ -68,9 +68,28 @@ p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type) scom_data &= ~BIT64(0); CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data); - PK_TRACE("trigger Scan0"); + PK_TRACE("Setting SCAN0 Mode"); CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_AND, scom_data); - scom_data |= BIT64(2); + scom_data |= BIT64(3); + CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data); + + // Setting Scan length count + // Longest (lbisted) stump in the core for DD1: 2410 latches + // Longest (lbisted) stump in the core for DD2: 1020 latches + + PK_TRACE("Setting scan length count"); + + // Set bits 59:63 to 24 for the NSL_FILL_COUNT +#if NIMBUS_DD_LEVEL == 1 + scom_data = ((uint64_t)2410 << SHIFT64(11)) | 24; +#else + scom_data = ((uint64_t)1024 << SHIFT64(11)) | 24; +#endif + CME_PUTSCOM(PERV_OPCG_REG1, core, scom_data); + + PK_TRACE("Trigger OPCG GO"); + CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_AND, scom_data); + scom_data |= BIT64(1); CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data); PK_TRACE("Poll OPCG done bit to check for run-N completeness"); @@ -81,6 +100,16 @@ p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type) } while(!(scom_data & BIT64(8))); + PK_TRACE("Clearing SCAN0 Mode"); + CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_AND, scom_data); + scom_data &= ~BIT64(3); + CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data); + + PK_TRACE("Clearing scan length count"); + CME_GETSCOM(PERV_OPCG_REG1, core, CME_SCOM_AND, scom_data); + scom_data &= ~BITS64(0, 12); + CME_PUTSCOM(PERV_OPCG_REG1, core, scom_data); + PK_TRACE("clear all clock REGIONS and type"); CME_PUTSCOM(PERV_CLK_REGION, core, 0); |
