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| author | Michael Floyd <mfloyd@us.ibm.com> | 2017-05-16 17:40:00 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-08-22 17:54:51 -0500 |
| commit | 51a2d2a6114756f21a2c651844e84a4cd9ea93e9 (patch) | |
| tree | f7a88448e8880a8bdafc68588e65f3e26233e38e | |
| parent | dbc5a4d2778995b0a29827915dab7deac3e6e3b8 (diff) | |
| download | talos-hcode-51a2d2a6114756f21a2c651844e84a4cd9ea93e9.tar.gz talos-hcode-51a2d2a6114756f21a2c651844e84a4cd9ea93e9.zip | |
STOP: Fix STOP1 correctly for DD1 Workaround
Change-Id: I9802c5fc79c5d651df3f15f8df82e46506c0cc85
Original-Change-Id: I8e10199208db098f5e73b9b3c66cb64a097f73e6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40603
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
| -rwxr-xr-x | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index 02530e7d..ee9965a1 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -390,11 +390,6 @@ p9_cme_stop_entry() core = core & ~core_stop1; - if (!core) - { - break; - } - #else // Nap should be done by hardware when auto_stop1 is enabled @@ -406,10 +401,6 @@ p9_cme_stop_entry() } - //---------------------------------------------------------------------- - PK_TRACE("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++"); - //---------------------------------------------------------------------- - #if HW405292_NDD1_PCBMUX_SAVIOR p9_cme_pcbmux_savior_prologue(core); @@ -430,6 +421,20 @@ p9_cme_stop_entry() #endif +#if HW386841_NDD1_DSL_STOP1_FIX + + // exit after getting PCBMUX for Stop1 Workaround + if (!core) + { + break; + } + +#endif + + //---------------------------------------------------------------------- + PK_TRACE("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++"); + //---------------------------------------------------------------------- + // set target_level from pm_state for both cores or just one core target_level = (core == CME_MASK_C0) ? G_cme_stop_record.req_level[0] : G_cme_stop_record.req_level[1]; |

