STOP: Clear up todo items in STOP and mark them with RTC

1) add RTC marks for VDM/Xstop/CME Halt
2) add epm_p9_tunning for scan ratio
3) fix checking anep clock starts
4) fix large system default assuming header works now
5) poll for pfet sense line for power on/off
6) finalize panic upon fapi2 init fail in sgpe_main.c

Change-Id: I064136b1b7a6c5ab4648663bc4774f4e2c82390c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34618
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

13 files changed, 38 insertions, 48 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 88f77136..464bc3e6 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -421,7 +421,7 @@ p9_cme_stop_entry()
         PK_TRACE("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
         CME_PUTSCOM(C_CPLT_CONF0_CLEAR, core, BIT64(34));
 
-        /// @todo add VDM_ENABLE attribute control
+        /// @todo RTC166918 add VDM_ENABLE attribute control
         PK_TRACE("Drop vdm enable via CPPM_VDMCR[0]");
         CME_PUTSCOM(PPM_VDMCR_CLR, core, BIT64(0));
 
@@ -719,13 +719,13 @@ p9_cme_stop_entry()
             // vdd_pfet_force_state = 01 (Force Voff)
             CME_PUTSCOM(PPM_PFCS_OR, core, BIT64(1));
 
-            PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle) via PFCS[42]");
+            PK_TRACE("Poll for vdd_pfets_disabled_sense via PFSNS[1]");
 
             do
             {
-                CME_GETSCOM(PPM_PFCS, core, CME_SCOM_AND, scom_data);
+                CME_GETSCOM(PPM_PFSNS, core, CME_SCOM_AND, scom_data);
             }
-            while(!(scom_data & BIT64(42)));
+            while(!(scom_data & BIT64(1)));
 
             PK_TRACE("Turn off force voff via PFCS[0-1]");
             // vdd_pfet_force_state = 00 (Nop)
@@ -852,8 +852,6 @@ p9_cme_stop_entry()
             out32(CME_LCL_SICR_OR, BIT32(18) | BIT32(21));
             out32(CME_LCL_SICR_OR, BIT32(22));
 
-            // todo: poll for tlbie quiesce done?
-
             PK_TRACE("Poll for purged done via EISR[22,23]");
 
             do
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
index 7c98f92e..0a1f7f61 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
@@ -91,7 +91,9 @@ p9_hcd_core_chiplet_reset(uint32_t core)
     PK_TRACE("Set scan ratio to 2:1 in non-bypass mode via OPCG_ALIGN[47-51]");
     CME_GETSCOM(C_OPCG_ALIGN, core, CME_SCOM_AND, scom_data.value);
     scom_data.words.lower &= ~BITS32(15, 5);
+#if !EPM_P9_TUNING
     scom_data.words.lower |= BIT32(19);
+#endif
     CME_PUTSCOM(C_OPCG_ALIGN, core, scom_data.value);
 
     // Marker for scan0
@@ -101,7 +103,7 @@ p9_hcd_core_chiplet_reset(uint32_t core)
     p9_hcd_core_scan0(core, SCAN0_REGION_ALL, SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME);
 #endif
 
-    /// @todo add VDM_ENABLE attribute control
+    /// @todo RTC166918 add VDM_ENABLE attribute control
     PK_TRACE("Assert vdm enable via CPPM_VDMCR[0]");
     CME_PUTSCOM(PPM_VDMCR_OR, core, BIT64(0));
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
index 4a091106..17551f50 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
@@ -58,10 +58,10 @@ p9_hcd_core_poweron(uint32_t core)
     if (core & CME_MASK_C0)
     {
         // vdd_pfet_force_state = 11 (Force Von)
-        PK_TRACE("Power Off Core VDD");
+        PK_TRACE("Power On Core VDD");
         CME_PUTSCOM(PPM_PFCS_OR, CME_MASK_C0, BITS64(0, 2));
 
-        PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle)");
+        PK_TRACE("Poll for vdd_pfets_enabled_sense");
 
         do
         {
@@ -73,16 +73,16 @@ p9_hcd_core_poweron(uint32_t core)
     if (core & CME_MASK_C1)
     {
         // vdd_pfet_force_state = 11 (Force Von)
-        PK_TRACE("Power Off Core VDD");
+        PK_TRACE("Power On Core VDD");
         CME_PUTSCOM(PPM_PFCS_OR, CME_MASK_C1, BITS64(0, 2));
 
-        PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle)");
+        PK_TRACE("Poll for vdd_pfets_enabled_sense");
 
         do
         {
-            CME_GETSCOM(PPM_PFCS, CME_MASK_C1, CME_SCOM_AND, scom_data);
+            CME_GETSCOM(PPM_PFSNS, CME_MASK_C1, CME_SCOM_AND, scom_data);
         }
-        while(!(scom_data & BIT64(42)));
+        while(!(scom_data & BIT64(0)));
     }
 
     // vdd_pfet_force_state = 00 (Nop)
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
index a60e11ac..7cb51fc8 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
@@ -140,16 +140,14 @@ p9_hcd_core_startclocks(uint32_t core)
     PK_TRACE("Core clock is now running");
     MARK_TRAP(SX_STARTCLOCKS_DONE)
 
-    /// @todo add attr_pg control
     PK_TRACE("Drop chiplet fence via NC0INDIR[18]");
     CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(18));
 
-    /// @todo xstop check
+    /// @todo RTC166917 Check the Global Checkstop FIR
 
     PK_TRACE("Drop flushmode_inhibit via CPLT_CTRL0[2]");
     CME_PUTSCOM(C_CPLT_CTRL0_CLEAR, core, BIT64(2));
 
-    /// @todo add ipl mode attr control
     PK_TRACE("Drop Core-L2/CC/TLBIE Quiesces via CME_LCL_SICR[6,8]/[7,9][21]");
     out32(CME_LCL_SICR_CLR, ((core << SHIFT32(7)) | (core << SHIFT32(9)) | BIT32(21)));
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C
index 22c858bc..9e321895 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C
@@ -60,6 +60,7 @@ extern "C" int p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t quad)
     FAPI_DBG("Drop L3 DCC bypass");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL1_WAND, quad), ~BIT64(1));
 
+    /// @todo RTC166918 add VDM_ENABLE attribute control
     FAPI_DBG("Check if VDMs are to be enabled. If so, power them on");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_OR, quad), BIT64(0));
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c
index 21cf6082..6893cab9 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c
@@ -220,9 +220,9 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex)
 
     do
     {
-        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS, quad), scom_data);
+        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFSNS, quad), scom_data);
     }
-    while(!(scom_data & BIT64(50)));
+    while(!(scom_data & BIT64(2)));
 
     // vdd_pfet_force_state = 00 (Nop)
     // vcs_pfet_force_state = 00 (Nop)
@@ -275,13 +275,5 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex)
     p9_hcd_cache_scan0(quad, regions, SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME);
 #endif
 
-    /// content of p9_hcd_cache_chiplet_l3_dcc_setup below:
-    /// @todo scan_with_setpulse_module(l3 dcc)
-    //PK_TRACE("Drop L3 DCC bypass via NET_CTRL1[1]");
-    //GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL1_WAND, quad), ~BIT64(1));
-    /// @todo add VDM_ENABLE attribute control
-    //PK_TRACE("Assert vdm enable via CPPM_VDMCR[0]");
-    //GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_OR, quad), BIT64(0));
-
     return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c
index 7c6c11c8..babd87e1 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c
@@ -94,7 +94,9 @@ p9_hcd_cache_dpll_setup(uint32_t quad)
     PK_TRACE("Set scan ratio to 4:1 in bypass mode via OPCG_ALIGN[47-51]");
     GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_OPCG_ALIGN, quad), scom_data);
     scom_data &= ~BITS64(47, 5);
+#if !EPM_P9_TUNING
     scom_data |=  BITS64(50, 2);
+#endif
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_OPCG_ALIGN, quad), scom_data);
 
     PK_TRACE("Drop skew/duty cycle adjust func_clksel via NET_CTRL0[22]");
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
index d4866061..7b40a426 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
@@ -117,7 +117,7 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg)
     // Cleaning up
     // -------------------------------
 
-    /// @todo Check the Global Checkstop FIR of dedicated EX chiplet
+    /// @todo RTC166917 Check the Global Checkstop FIR
 
 #if NIMBUS_DD_LEVEL != 1
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c
index 889827b5..fa3ece23 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c
@@ -63,26 +63,26 @@ p9_hcd_cache_poweron(uint32_t quad)
     PK_TRACE("Power On Cache VDD");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, quad), BITS64(0, 2));
 
-    PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle)");
+    PK_TRACE("Poll for vdd_pfets_enabled_sense");
 
     do
     {
-        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS, quad), scom_data);
+        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFSNS, quad), scom_data);
     }
-    while(!(scom_data & BIT64(42)));
+    while(!(scom_data & BIT64(0)));
 
 #if !HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX
     // vcs_pfet_force_state = 11 (Force Von)
     PK_TRACE("Power On Cache VCS");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, quad), BITS64(2, 2));
 
-    PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle)");
+    PK_TRACE("Poll for vcs_pfets_enabled_sense");
 
     do
     {
-        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS, quad), scom_data);
+        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFSNS, quad), scom_data);
     }
-    while(!(scom_data & BIT64(50)));
+    while(!(scom_data & BIT64(2)));
 
     // vdd_pfet_force_state = 00 (Nop)
     // vcs_pfet_force_state = 00 (Nop)
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
index 5d1e5d75..3fc48b37 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
@@ -33,8 +33,7 @@ int
 p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8)
 {
     int rc = SGPE_STOP_SUCCESS;
-    /// @todo change this back to 0, when flag bit is ready via image build
-    int attr_proc_fabric_addr_bar_mode_small_system = 1; // default small
+    int attr_proc_fabric_addr_bar_mode_small_system = 0; // default large
     int attr_proc_fabric_dump_mode_chip_is_node     = 0; // default group
     data64_t scom_data;
     sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(SGPE_IMAGE_SRAM_BASE + SGPE_HEADER_IMAGE_OFFSET);
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
index 02ddfc16..73ab9482 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
@@ -176,7 +176,7 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex)
     PK_TRACE("Check cache clock running via CLOCK_STAT_SL[4-14]");
     GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_SL, quad), scom_data.value);
 
-    if (scom_data.value & (CLK_REGION_ALL_BUT_EX_ANEP_DPLL |
+    if (scom_data.value & (CLK_REGION_ALL_BUT_EX_DPLL      |
                            ((uint64_t)ex << SHIFT64(7))    |
                            ((uint64_t)ex << SHIFT64(13))))
     {
@@ -284,11 +284,10 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex)
         }
     }
 
-    /// @todo add ipl mode attr control
     PK_TRACE("Drop chiplet fence via NET_CTRL0[18]");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), ~BIT64(18));
 
-    /// @todo Check the Global Checkstop FIR of dedicated EX chiplet
+    /// @todo RTC166917 Check the Global Checkstop FIR
 
 #if NIMBUS_DD_LEVEL != 1
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C
index f69b53b4..53e60beb 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C
@@ -152,7 +152,8 @@ main(int argc, char** argv)
 
     if( fapiRc != fapi2::FAPI2_RC_SUCCESS )
     {
-        PK_PANIC(PK_UNUSED_0d1f);  // @todo RTC XXXXXX for correct panic codes
+        PK_TRACE_INF("ERROR: FAPI2 Init Failed. HALT SGPE!");
+        pk_halt();
     }
 
     // Initialize the thread control block for G_p9_sgpe_stop_enter_thread
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index 72063887..88207022 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -864,7 +864,7 @@ p9_sgpe_stop_entry()
         PK_TRACE("Drop CME_INTERPPM_DPLL_ENABLE after DPLL is stopped via QPMMR[26]");
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_CLR, qloop), BIT64(20) | BIT64(22) | BIT64(24) | BIT64(26));
 
-        /// @todo add VDM_ENABLE attribute control
+        /// @todo RTC166918 add VDM_ENABLE attribute control
         PK_TRACE("Drop vdm enable via CPPM_VDMCR[0]");
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_CLR, qloop), BIT64(0));
 
@@ -994,27 +994,25 @@ p9_sgpe_stop_entry()
             // vcs_pfet_force_state = 01 (Force Voff)
             GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, qloop), BIT64(3));
 
-            PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle) via PFCS[50]");
-            // todo: poll the sense line instead
+            PK_TRACE("Poll for vcs_pfets_disabled_sense via PFSNS[3]");
 
             do
             {
-                GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS, qloop), scom_data);
+                GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFSNS, qloop), scom_data);
             }
-            while(!(scom_data & BIT64(50)));
+            while(!(scom_data & BIT64(3)));
 
             PK_TRACE("Power off VDD via PFCS[0-1]");
             // vdd_pfet_force_state = 01 (Force Voff)
             GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, qloop), BIT64(1));
 
-            PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle) via PFCS[42]");
-            // todo: poll the sense line instead
+            PK_TRACE("Poll for vdd_pfets_disabled_sense via PFSNS[1]");
 
             do
             {
-                GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS, qloop), scom_data);
+                GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFSNS, qloop), scom_data);
             }
-            while(!(scom_data & BIT64(42)));
+            while(!(scom_data & BIT64(1)));
 
             PK_TRACE("Turn off force voff via PFCS[0-3]");
             // vdd_pfet_force_state = 00 (Nop)