STOP: prevent ppe wait cycle being compiled out by compiler

Change-Id: Ib9472733f828b557d4799ddb9fb00975ce004d9e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34378
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

9 files changed, 30 insertions, 33 deletions

diff --git a/import/chips/p9/common/pmlib/include/ppehw_common.h b/import/chips/p9/common/pmlib/include/ppehw_common.h
index 2f7e4ccc..7b8c96df 100644
--- a/import/chips/p9/common/pmlib/include/ppehw_common.h
+++ b/import/chips/p9/common/pmlib/include/ppehw_common.h
@@ -94,11 +94,11 @@ typedef union
 #define PPE_FOR_LOOP_CYCLES        4 // fused compare branch(3), addition(1)
 #define PPE_CORE_CYCLE_DIVIDER     (PPE_CORE_CYCLE_RATIO*PPE_FOR_LOOP_CYCLES)
 #ifdef USE_PPE_IMPRECISE_MODE
-#define PPE_WAIT_CORE_CYCLES(l,cc) \
-    for(l=0;l<cc/PPE_CORE_CYCLE_DIVIDER;l++);asm volatile ("sync");
+#define PPE_WAIT_CORE_CYCLES(cc) \
+    {volatile uint32_t l;for(l=0;l<cc/PPE_CORE_CYCLE_DIVIDER;l++);asm volatile ("sync");}
 #else
-#define PPE_WAIT_CORE_CYCLES(l,cc) \
-    for(l=0;l<cc/PPE_CORE_CYCLE_DIVIDER;l++);
+#define PPE_WAIT_CORE_CYCLES(cc) \
+    {volatile uint32_t l;for(l=0;l<cc/PPE_CORE_CYCLE_DIVIDER;l++);}
 #endif
 
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 74323a96..88f77136 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -63,7 +63,6 @@ p9_cme_stop_entry()
     uint32_t        core_stop1          = 0;
     uint32_t        core_raw            = 0;
     uint32_t        core;
-    uint32_t        loop;
     uint32_t        pm_states;
     uint32_t        lclr_data;
     uint64_t        scom_data;
@@ -352,7 +351,7 @@ p9_cme_stop_entry()
 
         // Waits quiesce done for at least 512 core cycles
         // MF: verify generate FCB otherwise math is wrong.
-        PPE_WAIT_CORE_CYCLES(loop, 512)
+        PPE_WAIT_CORE_CYCLES(512)
 
         PK_TRACE_INF("SE2.B: Interfaces Quiesced");
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
index 796efe1e..7c98f92e 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
@@ -50,7 +50,6 @@ int
 p9_hcd_core_chiplet_reset(uint32_t core)
 {
     int rc = CME_STOP_SUCCESS;
-    uint32_t loop;
     data64_t scom_data;
 
     PK_TRACE("Init NET_CTRL0[1,3-5,11-14,16,18,22,25,26],step needed for hotplug");
@@ -72,7 +71,7 @@ p9_hcd_core_chiplet_reset(uint32_t core)
     PK_TRACE("Flip core glsmux to DPLL via PPM_CGCR[3]");
     CME_PUTSCOM(C_PPM_CGCR, core, BIT64(3));
     // 200 core clocks
-    PPE_WAIT_CORE_CYCLES(loop, 200);
+    PPE_WAIT_CORE_CYCLES(200);
 
     PK_TRACE("Assert chiplet enable via NET_CTRL0[0]");
     CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(0));
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
index 4b699c9e..a60e11ac 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
@@ -31,7 +31,6 @@ int
 p9_hcd_core_startclocks(uint32_t core)
 {
     int      rc = CME_STOP_SUCCESS;
-    int      loop;
     uint32_t id_vector;
     data64_t scom_data;
 
@@ -97,7 +96,7 @@ p9_hcd_core_startclocks(uint32_t core)
     CME_PUTSCOM(C_SYNC_CONFIG, core, scom_data.value);
 
     // 255 cache cycles
-    PPE_WAIT_CORE_CYCLES(loop, 510);
+    PPE_WAIT_CORE_CYCLES(510);
 
     PK_TRACE("Check chiplet_is_aligned");
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c
index 1a4cdf61..21cf6082 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c
@@ -54,7 +54,6 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex)
     int rc = SGPE_STOP_SUCCESS;
     uint64_t scom_data;
     uint32_t core, cbit;
-    uint32_t loop;
 
     for(core = 0, cbit = BIT32((quad << 2));
         core < CORES_PER_QUAD;
@@ -105,7 +104,7 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex)
 #endif
 
     // 40 ref cycles
-    PPE_WAIT_CORE_CYCLES(loop, 1600);
+    PPE_WAIT_CORE_CYCLES(1600);
 
     PK_TRACE("Assert chiplet enable via NET_CTRL0[0]");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, quad), BIT64(0));
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
index be504135..d4866061 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
@@ -32,7 +32,6 @@ int
 p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg)
 {
     int      rc = SGPE_STOP_SUCCESS;
-    uint32_t loop;
     uint64_t scom_data;
 
     PK_TRACE("Drop L2 Regional Fences via CPLT_CTRL1[8/9]");
@@ -69,7 +68,7 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg)
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SYNC_CONFIG, quad), scom_data);
 
     // 255 cache cycles
-    PPE_WAIT_CORE_CYCLES(loop, 510);
+    PPE_WAIT_CORE_CYCLES(510);
 
     PK_TRACE("Check chiplet_is_aligned");
 
@@ -119,9 +118,12 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg)
     // -------------------------------
 
     /// @todo Check the Global Checkstop FIR of dedicated EX chiplet
+
 #if NIMBUS_DD_LEVEL != 1
-    PK_TRACE("Clear flushmode_inhibit via CPLT_CTRL0[2]");
+
+    PK_TRACE("Drop flushmode_inhibit via CPLT_CTRL0[2]");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL0_CLEAR, quad), BIT64(2));
+
 #endif
 
     PK_TRACE("Set parital bad l2/l3 and stopped l2 pscom mask");
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
index c6af6978..02ddfc16 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
@@ -31,7 +31,7 @@ int
 p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex)
 {
     int        rc = SGPE_STOP_SUCCESS;
-    int        loop, exloop, excount = 0;
+    int        exloop, excount = 0;
     uint32_t   id_vector;
     data64_t   scom_data;
     ocb_qcsr_t qcsr;
@@ -55,19 +55,19 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex)
     {
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(0));
 #if !EPM_P9_TUNING
-        PPE_WAIT_CORE_CYCLES(loop, 48000);
+        PPE_WAIT_CORE_CYCLES(48000);
 #endif
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(1));
 #if !EPM_P9_TUNING
-        PPE_WAIT_CORE_CYCLES(loop, 4000);
+        PPE_WAIT_CORE_CYCLES(4000);
 #endif
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(2));
 #if !EPM_P9_TUNING
-        PPE_WAIT_CORE_CYCLES(loop, 16000);
+        PPE_WAIT_CORE_CYCLES(16000);
 #endif
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(3));
 #if !EPM_P9_TUNING
-        PPE_WAIT_CORE_CYCLES(loop, 4000);
+        PPE_WAIT_CORE_CYCLES(4000);
 #endif
     }
 
@@ -75,19 +75,19 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex)
     {
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(4));
 #if !EPM_P9_TUNING
-        PPE_WAIT_CORE_CYCLES(loop, 48000);
+        PPE_WAIT_CORE_CYCLES(48000);
 #endif
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(5));
 #if !EPM_P9_TUNING
-        PPE_WAIT_CORE_CYCLES(loop, 4000);
+        PPE_WAIT_CORE_CYCLES(4000);
 #endif
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(6));
 #if !EPM_P9_TUNING
-        PPE_WAIT_CORE_CYCLES(loop, 16000);
+        PPE_WAIT_CORE_CYCLES(16000);
 #endif
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, quad), BIT64(7));
 #if !EPM_P9_TUNING
-        PPE_WAIT_CORE_CYCLES(loop, 4000);
+        PPE_WAIT_CORE_CYCLES(4000);
 #endif
     }
 
@@ -134,7 +134,7 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex)
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SYNC_CONFIG, quad), scom_data.value);
 
     // 255 cache cycles
-    PPE_WAIT_CORE_CYCLES(loop, 510);
+    PPE_WAIT_CORE_CYCLES(510);
 
     PK_TRACE("Check chiplet_is_aligned");
 
@@ -290,9 +290,13 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex)
 
     /// @todo Check the Global Checkstop FIR of dedicated EX chiplet
 
+#if NIMBUS_DD_LEVEL != 1
+
     PK_TRACE("Drop flushmode_inhibit via CPLT_CTRL0[2]");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL0_CLEAR, quad), BIT64(2));
 
+#endif
+
     PK_TRACE("Set all l2s and partial bad l3 pscom mask");
     scom_data.value = PSCOM_MASK_ALL_L2;
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
index 32ebb9e3..6eac41ca 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c
@@ -99,10 +99,6 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
 {
     BootErrorCode_t l_retCode = CME_BOOT_SUCCESS;
 
-    //uint32_t cme_boot_loop;
-    uint32_t cme_bce_loop;
-    uint32_t cme_rdy_loop;
-
     do
     {
         int rc = 0;
@@ -348,7 +344,7 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
 
             } //for ( l_cmeIndex = 0 ....)
 
-            PPE_WAIT_CORE_CYCLES(cme_bce_loop, 256);
+            PPE_WAIT_CORE_CYCLES(256);
         } //while(l_bceCnt != activeCmeCnt)
 
         PK_TRACE("BCE done and resume scom_addr: 0x%08x", l_scomAddr);
@@ -405,7 +401,7 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme )
                     cmeReadyList = cmeReadyList | l_cmeActiveBit;
                 }//end for
 
-                PPE_WAIT_CORE_CYCLES(cme_rdy_loop, 256);
+                PPE_WAIT_CORE_CYCLES(256);
             } // while l_cmeRdyCnt != activeCmeCnt
         } //if all CME kicked off
     }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index 0dc0f2e0..72063887 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -77,7 +77,6 @@ p9_sgpe_stop_entry()
     uint32_t     climit;
     uint32_t     xentry;
     uint32_t     qentry;
-    uint32_t     loop;
     uint64_t     scom_data;
     uint64_t     temp_data;
     uint64_t     host_attn;
@@ -364,7 +363,7 @@ p9_sgpe_stop_entry()
             GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_L2_RCMD_DIS_REG, qloop, 1),
                         BIT64(0));
 
-        PPE_WAIT_CORE_CYCLES(loop, 256)
+        PPE_WAIT_CORE_CYCLES(256)
 
         PK_TRACE("Assert partial bad L2/L3 and stopping/stoped l2 pscom masks via RING_FENCE_MASK_LATCH");
         scom_data = 0;