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| author | Brian Vanderpool <vanderp@us.ibm.com> | 2017-11-28 12:36:43 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2018-02-01 16:20:11 -0600 |
| commit | 3db1688ceec8d741422b09a36520f2ca51f49d46 (patch) | |
| tree | 04c0f5e81b9bc52c6c4389fe70bc597cc6137ba8 | |
| parent | 5ecde4b2eb2ee6bf281e1c489b1457556f3552c2 (diff) | |
| download | talos-hcode-3db1688ceec8d741422b09a36520f2ca51f49d46.tar.gz talos-hcode-3db1688ceec8d741422b09a36520f2ca51f49d46.zip | |
PM: Add a PMCR update in progress field for pman_irr
Key_Cronus_Test=PM_REGRESS
Change-Id: I0969ead627c85b16fe32aa5a36e6057540d89f06
Original-Change-Id: I0ee389d747b45ab697138ce24d1e444f522b3bce
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50104
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
3 files changed, 21 insertions, 0 deletions
diff --git a/import/chips/p9/common/pmlib/include/pstate_pgpe_cme_api.h b/import/chips/p9/common/pmlib/include/pstate_pgpe_cme_api.h index 40cd6318..5492995a 100644 --- a/import/chips/p9/common/pmlib/include/pstate_pgpe_cme_api.h +++ b/import/chips/p9/common/pmlib/include/pstate_pgpe_cme_api.h @@ -80,6 +80,7 @@ enum PMSR_DEFS PMSR_SAFE_MODE = 33, PMSR_IVRM_ALLOWED = 34, PMSR_IVRM_ENABLED = 35, + PMSR_UPDATE_IN_PROGRESS = 58, PMSR_INVALID_PMCR_VERSION = 59, PMSR_VERSION_START = 60, PMSR_VERSION_LENGTH = 4 diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c index 8ab2a3ff..2f16fd67 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c @@ -717,3 +717,21 @@ void p9_cme_pstate_pmsr_updt(uint32_t coreMask) } } } + + +void p9_cme_pstate_pmsr_updt_in_progress(uint32_t coreMask) +{ + uint32_t cm; + uint64_t pmsrData; + + //CORE0 mask is 0x2, and CORE1 mask is 0x1. + //We AND with 0x1 to get the core number from mask. + for (cm = 2; cm > 0; cm--) + { + if (cm & coreMask) + { + pmsrData = in64(CME_LCL_PMSRS0 + ((cm & 0x1) << 5)) | BIT64(PMSR_UPDATE_IN_PROGRESS); + out64(CME_LCL_PMSRS0 + ((cm & 0x1) << 5), pmsrData); + } + } +} diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h index 285165e1..39133da0 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h @@ -196,7 +196,9 @@ void intercme_msg_recv(uint32_t* msg, INTERCME_MSG_TYPE type); void intercme_direct(INTERCME_DIRECT_INTF intf, INTERCME_DIRECT_TYPE type, uint32_t retry_enable); void p9_cme_core_stop_analog_control(uint32_t core_mask, ANALOG_CONTROL enable); void p9_cme_pstate_pmsr_updt(uint32_t coreMask); +void p9_cme_pstate_pmsr_updt_in_progress(uint32_t coreMask); void p9_cme_pstate_intercme_in0_handler(); + #ifdef USE_CME_RESCLK_FEATURE uint32_t p9_cme_resclk_get_index(uint32_t pstate); void p9_cme_resclk_update(ANALOG_TARGET target, uint32_t pstate, uint32_t curr_idx); |
