PGPE: STOP11+WOF+SafeMode Fixes

    -STOP11+WOF Fix
    -STOP11+WOF+Safe Mode

    Key_Cronus_Test=PM_REGRESS

Change-Id: I7b517b5722e13975a2b8a67544d50caa33fc4d92
Original-Change-Id: I7aae651213174049fa4fe89d6ac92fda2478e90a
CQ: SW410652
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48989
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

5 files changed, 61 insertions, 15 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
index 860083b6..c0f8b80e 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
@@ -47,7 +47,12 @@ extern CmeRecord G_cme_record;
 //
 //InterCME_IN0 handler
 //
-void p9_cme_pstate_intercme_in0_handler(void* arg, PkIrqId irq)
+void p9_cme_pstate_intercme_in0_irq_handler(void* arg, PkIrqId irq)
+{
+    p9_cme_pstate_intercme_in0_handler();
+}
+
+void p9_cme_pstate_intercme_in0_handler()
 {
     cppm_cmedb0_t dbData;
     dbData.value = 0;
@@ -119,9 +124,11 @@ void p9_cme_pstate_intercme_in0_handler(void* arg, PkIrqId irq)
     else if(dbData.fields.cme_message_number0 == MSGID_DB0_STOP_PSTATE_BROADCAST)
     {
         PK_TRACE("INTER0: DB0 Stop");
-        out32_sh(CME_LCL_EIMR_OR, (SHIFT64SH(34) | SHIFT64SH(35)));//Disable PMCR0/1
+        out32_sh(CME_LCL_EIMR_OR, (BITS64SH(34, 2)));//Disable PMCR0/1
         g_eimr_override |= BITS64(34, 2);
 
+        p9_cme_pstate_pmsr_updt(G_cme_record.core_enabled);
+
         //Set Core GPMMR RESET_STATE_INDICATOR bit to show pstates have stopped
         CME_PUTSCOM(PPM_GPMMR_OR, G_cme_record.core_enabled, BIT64(15));
     }
@@ -138,7 +145,7 @@ void p9_cme_pstate_intercme_in0_handler(void* arg, PkIrqId irq)
         PK_PANIC(CME_PSTATE_INVALID_DB0_MSGID);
     }
 
-    out32_sh(CME_LCL_EISR_CLR, G_cme_record.core_enabled << 25);//Clear DB0_C0/C1
+    out32_sh(CME_LCL_EISR_CLR, G_cme_record.core_enabled << SHIFT64SH(37));//Clear DB0_C0/C1
 
     intercme_direct(INTERCME_DIRECT_IN0, INTERCME_DIRECT_ACK, 0);
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h
index 440f2fee..285165e1 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h
@@ -185,7 +185,7 @@ void p9_cme_pstate_pmcr_thread(void*);
 void p9_cme_pstate_db_thread(void*);
 void p9_cme_pstate_pmcr_handler(void*, PkIrqId);
 void p9_cme_pstate_db_handler(void*, PkIrqId);
-void p9_cme_pstate_intercme_in0_handler(void*, PkIrqId);
+void p9_cme_pstate_intercme_in0_irq_handler(void*, PkIrqId);
 void p9_cme_pstate_intercme_msg_handler(void* arg, PkIrqId irq);
 int send_pig_packet(uint64_t data, uint32_t coreMask);
 void poll_dpll_update_complete();
@@ -196,6 +196,7 @@ void intercme_msg_recv(uint32_t* msg, INTERCME_MSG_TYPE type);
 void intercme_direct(INTERCME_DIRECT_INTF intf, INTERCME_DIRECT_TYPE type, uint32_t retry_enable);
 void p9_cme_core_stop_analog_control(uint32_t core_mask, ANALOG_CONTROL enable);
 void p9_cme_pstate_pmsr_updt(uint32_t coreMask);
+void p9_cme_pstate_intercme_in0_handler();
 #ifdef USE_CME_RESCLK_FEATURE
     uint32_t p9_cme_resclk_get_index(uint32_t pstate);
     void p9_cme_resclk_update(ANALOG_TARGET target, uint32_t pstate, uint32_t curr_idx);
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index 412359aa..c1353990 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -667,7 +667,7 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
         out32(OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
     }
 
-    //7. Send Pstate Start Doorbell0
+    //7. Send clip updates to all quads that are active
     pgpe_db0_clip_bcast_t db0_clip_bcast;
     db0_clip_bcast.value = 0;
     db0_clip_bcast.fields.msg_id = MSGID_DB0_CLIP_BROADCAST;
@@ -699,7 +699,7 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
                      PGPE_DB0_ACK_WAIT_CME,
                      G_pgpe_pstate_record.activeQuads);
 
-
+    //Send Pstate Start Doorbell0
     pgpe_db0_start_ps_bcast_t db0;
     db0.value = 0;
     db0.fields.msg_id = MSGID_DB0_START_PSTATE_BROADCAST;
@@ -791,7 +791,7 @@ void p9_pgpe_pstate_set_pmcr_owner(uint32_t owner)
         if(G_pgpe_pstate_record.activeQuads & QUAD_MASK(q))
         {
             //CME0 within this quad
-            if (qcsr.fields.ex_config & (0x800 >> 2 * q))
+            if (qcsr.fields.ex_config & (0x800 >> (q << 1)))
             {
                 if (owner == PMCR_OWNER_HOST)
                 {
@@ -804,7 +804,7 @@ void p9_pgpe_pstate_set_pmcr_owner(uint32_t owner)
             }
 
             //CME1 within this quad
-            if (qcsr.fields.ex_config & (0x400 >> 2 * q))
+            if (qcsr.fields.ex_config & (0x400 >> (q << 1)))
             {
                 if (owner == PMCR_OWNER_HOST)
                 {
@@ -828,10 +828,32 @@ void p9_pgpe_pstate_set_pmcr_owner(uint32_t owner)
 void p9_pgpe_pstate_stop()
 {
     PK_TRACE_INF("PSS: Pstate Stop Enter");
+    uint32_t q;
     pgpe_db0_stop_ps_bcast_t db0_stop;
+    ocb_qcsr_t qcsr;
+
+    qcsr.value = in32(OCB_QCSR);
     db0_stop.value = 0;
     db0_stop.fields.msg_id = MSGID_DB0_STOP_PSTATE_BROADCAST;
 
+    for (q = 0; q < MAX_QUADS; q++)
+    {
+        if(G_pgpe_pstate_record.activeQuads & QUAD_MASK(q))
+        {
+            //CME0 within this quad
+            if (qcsr.fields.ex_config & (0x800 >> (q << 1)))
+            {
+                GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 0), BIT64(0));
+            }
+
+            //CME1 within this quad
+            if (qcsr.fields.ex_config & (0x400 >> (q << 1)))
+            {
+                GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 1), BIT64(0));
+            }
+        }
+    }
+
     p9_pgpe_send_db0(db0_stop.value,
                      G_pgpe_pstate_record.activeCores,
                      PGPE_DB0_UNICAST,
@@ -1059,7 +1081,6 @@ void p9_pgpe_pstate_safe_mode()
 
     if (G_pgpe_pstate_record.pstatesStatus == PSTATE_ACTIVE)
     {
-        occScr2 |= BIT32(PGPE_SAFE_MODE_ACTIVE);
         //In the case of suspend, if active the send_suspend is handled in actuate_pstates thread
         p9_pgpe_pstate_apply_safe_clips();
     }
@@ -1073,10 +1094,19 @@ void p9_pgpe_pstate_safe_mode()
         }
     }
 
+    //Update PstatesStatus
     G_pgpe_pstate_record.pstatesStatus = suspend ? PSTATE_PM_SUSPEND_PENDING : PSTATE_SAFE_MODE;
+
+    //Mark WOF Disabled so that PGPE doesn't interlock with OCC anymore
+    G_pgpe_pstate_record.wofEnabled = 0;
+
+    //Operation Trace Entry
     trace = suspend ? ACK_PM_SUSP : ACK_SAFE_DONE;
     p9_pgpe_optrace(trace);
+
+    //Update OCC Scratch2
     occScr2 &= ~BIT32(PGPE_PSTATE_PROTOCOL_ACTIVE);
+
     out32(OCB_OCCS2, occScr2);
     PK_TRACE_INF("SAF: Safe Mode Exit");
 }
@@ -1183,6 +1213,7 @@ int32_t p9_pgpe_pstate_at_target()
 //
 void p9_pgpe_pstate_do_step()
 {
+
     //Do one actuate step
     PK_TRACE_DBG("STEP: Entry");
     PK_TRACE_DBG("STEP: GTgt,GCurr 0x%x, 0x%x", G_pgpe_pstate_record.globalPSTarget,
@@ -1343,7 +1374,6 @@ void p9_pgpe_pstate_do_step()
     G_pgpe_optrace_data.word[2] = (G_pgpe_pstate_record.eVidCurr << 16) | G_pgpe_pstate_record.eVidCurr;
     p9_pgpe_optrace(ACTUATE_STEP_DONE);
     PK_TRACE_DBG("STEP: Exit");
-
 }
 
 //
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
index 5466311a..7f1f9092 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
@@ -198,13 +198,19 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
                         //See if ACTIVE QUADS ack is pending
                         if (G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].pending_ack == 1)
                         {
+
                             ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].cmd;
                             ipcmsg_s2p_update_active_quads_t* args = (ipcmsg_s2p_update_active_quads_t*)async_cmd->cmd_data;
-                            args->fields.return_active_quads = args_wof_vfrt->active_quads;
-                            args->fields.return_code = IPC_SGPE_PGPE_RC_SUCCESS;
-                            G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].pending_ack = 0;
-                            ipc_send_rsp(G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].cmd, IPC_RC_SUCCESS);
-                            p9_pgpe_optrace(ACK_QUAD_ACTV);
+
+                            if (args_wof_vfrt->active_quads ==  G_pgpe_pstate_record.pReqActQuads->fields.requested_active_quads)
+                            {
+                                p9_pgpe_pstate_process_quad_exit(args->fields.requested_quads << 2);
+                                args->fields.return_active_quads = args_wof_vfrt->active_quads >> 2;
+                                args->fields.return_code = IPC_SGPE_PGPE_RC_SUCCESS;
+                                G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].pending_ack = 0;
+                                ipc_send_rsp(G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].cmd, IPC_RC_SUCCESS);
+                                p9_pgpe_optrace(ACK_QUAD_ACTV);
+                            }
                         }
                     }
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
index 3a76ed41..40bb2e1c 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
@@ -285,6 +285,7 @@ void p9_pgpe_process_sgpe_updt_active_quads()
             p9_pgpe_pstate_process_quad_entry_done(args->fields.requested_quads << 2);
         }
 
+        args->fields.return_active_quads = G_pgpe_pstate_record.activeQuads >> 2;
         args->fields.return_code = IPC_SGPE_PGPE_RC_SUCCESS;
     }
     //EXIT
@@ -302,6 +303,7 @@ void p9_pgpe_process_sgpe_updt_active_quads()
         else
         {
             p9_pgpe_pstate_process_quad_exit(args->fields.requested_quads << 2);
+            args->fields.return_active_quads = (G_pgpe_pstate_record.activeQuads >> 2) | args->fields.requested_quads;
             args->fields.return_code = IPC_SGPE_PGPE_RC_SUCCESS;
         }
     }