STOP: express processing targets of stop1/2 and stop5/8 exit

Change-Id: I4dd0d2fd1d87340b7cc73ecd4196310c96a23f24
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38290
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

38 files changed, 586 insertions, 583 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h
index c1dbb689..78593695 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h
@@ -138,11 +138,6 @@
 #define PERV_CPLT_STAT0        0x20000100
 
 
-/// CME STOP Return Codes
-enum CME_STOP_RETURN_CODE
-{
-    CME_STOP_SUCCESS                 = 0
-};
 
 /// CME STOP IRQs with shorter names
 enum CME_STOP_IRQ_SHORT_NAME
@@ -297,15 +292,14 @@ typedef struct
 /// CME STOP Entry and Exit Prototypes
 void p9_cme_pcbmux_savior_prologue(uint32_t);
 void p9_cme_pcbmux_savior_epilogue(uint32_t);
-
 void p9_cme_acquire_pcbmux(uint32_t, uint32_t);
 void p9_cme_release_pcbmux(uint32_t);
 
 void p9_cme_stop_enter_thread(void*);
 void p9_cme_stop_exit_thread(void*);
 void p9_cme_stop_eval_eimr_override();
-int  p9_cme_stop_entry();
-int  p9_cme_stop_exit();
+void p9_cme_stop_entry();
+void p9_cme_stop_exit();
 int  p9_cme_stop_exit_catchup(uint32_t*, uint32_t*, uint32_t*, uint8_t*, int*);
 
 void p9_cme_stop_enter_handler(void*, PkIrqId);
@@ -314,17 +308,17 @@ void p9_cme_stop_spwu_handler(void*, PkIrqId);
 void p9_cme_stop_db1_handler(void*, PkIrqId);
 void p9_cme_stop_db2_handler(void*, PkIrqId);
 
-int  p9_hcd_core_scan0(uint32_t, uint64_t, uint64_t);
-int  p9_hcd_core_pcb_arb(uint32_t, uint8_t);
-int  p9_hcd_core_poweron(uint32_t);
-int  p9_hcd_core_chiplet_reset(uint32_t);
-int  p9_hcd_core_gptr_time_initf(uint32_t);
-int  p9_hcd_core_chiplet_init(uint32_t);
-int  p9_hcd_core_repair_initf(uint32_t);
-int  p9_hcd_core_arrayinit(uint32_t);
-int  p9_hcd_core_initf(uint32_t);
-int  p9_hcd_core_startclocks(uint32_t);
-int  p9_hcd_core_scominit(uint32_t);
-int  p9_hcd_core_scomcust(uint32_t);
-int  p9_hcd_core_ras_runtime_scom(uint32_t);
-int  p9_hcd_core_occ_runtime_scom(uint32_t);
+void p9_hcd_core_scan0(uint32_t, uint64_t, uint64_t);
+void p9_hcd_core_pcb_arb(uint32_t, uint8_t);
+void p9_hcd_core_poweron(uint32_t);
+void p9_hcd_core_chiplet_reset(uint32_t);
+void p9_hcd_core_gptr_time_initf(uint32_t);
+void p9_hcd_core_chiplet_init(uint32_t);
+void p9_hcd_core_repair_initf(uint32_t);
+void p9_hcd_core_arrayinit(uint32_t);
+void p9_hcd_core_initf(uint32_t);
+void p9_hcd_core_startclocks(uint32_t);
+void p9_hcd_core_scominit(uint32_t);
+void p9_hcd_core_scomcust(uint32_t);
+void p9_hcd_core_ras_runtime_scom(uint32_t);
+void p9_hcd_core_occ_runtime_scom(uint32_t);
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 4aaf008c..60168754 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -257,7 +257,7 @@ void p9_cme_pcbmux_savior_epilogue(uint32_t core)
 
 #endif
 
-int
+void
 p9_cme_stop_entry()
 {
     int             catchup_ongoing     = 0;
@@ -317,7 +317,7 @@ p9_cme_stop_entry()
     {
         // PM_ACTIVE can be phantom, only gives warning
         PK_TRACE_INF("WARNING: Only Phantom PM_ACTIVE to be Ignored. Return");
-        return CME_STOP_SUCCESS;
+        return;
     }
 
     // NDD2: OOB bits wired to SISR
@@ -328,7 +328,7 @@ p9_cme_stop_entry()
         ((core & CME_MASK_C1) && (in32_sh(CME_LCL_SISR) & BITS64SH(61, 2))))
     {
         PK_TRACE_INF("WARNING: Attn/Recov Present, Abort Entry and Return");
-        return CME_STOP_SUCCESS;
+        return;
     }
 
     //===================================
@@ -1324,5 +1324,5 @@ p9_cme_stop_entry()
     MARK_TRAP(ENDSCOPE_STOP_ENTRY)
     //============================
 
-    return CME_STOP_SUCCESS;
+    return;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
index fb5a828a..f604f9a1 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
@@ -35,6 +35,266 @@ uint8_t G_dsl[MAX_CORES_PER_CME][MAX_THREADS_PER_CORE] = {{0, 0, 0, 0}, {0, 0, 0
 
 #endif
 
+void p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop)
+{
+    uint32_t     core_mask         = 0;
+    uint32_t     act_stop_level    = 0;
+    data64_t     scom_data         = {0};
+#if HW386841_DD1_DSL_STOP1_FIX
+    uint8_t      srr1[MAX_THREADS_PER_CORE] = {0, 0, 0, 0};
+    uint32_t     pscrs             = 0;
+    uint32_t     bitloc            = 0;
+    uint32_t     thread            = 0;
+    uint32_t     temp_dsl          = 0;
+    uint32_t     temp_srr1         = 0;
+    uint32_t     core_index        = 0;
+#endif
+
+    //--------------------------------------------------------------------------
+    PK_TRACE("+++++ +++++ END OF STOP EXIT +++++ +++++");
+    //--------------------------------------------------------------------------
+
+    PK_TRACE_DBG("Restore PSSCR.PLS+SRR1 back to actual level");
+
+#if HW386841_DD1_DSL_STOP1_FIX
+
+    for (core_mask = 2; core_mask; core_mask--)
+    {
+        if (core & core_mask)
+        {
+            CME_GETSCOM(PPM_SSHSRC, core_mask, CME_SCOM_AND, scom_data.value);
+
+            core_index            = core_mask & 1;
+            act_stop_level        = (scom_data.words.upper & BITS32(8, 4)) >> SHIFT32(11);
+            scom_data.words.lower = (BIT64SH(32) | BIT64SH(40) | BIT64SH(48) | BIT64SH(56));
+            scom_data.words.upper = 0;
+
+            for (thread = 0, bitloc = 36;
+                 thread < MAX_THREADS_PER_CORE;
+                 thread++,   bitloc += 8)
+            {
+                // address are 0x20 apart between threads and 0x80 apart between cores
+                pscrs = in32((CME_LCL_PSCRS00 + (core_index << 7) + (thread << 5)));
+
+                PK_TRACE_DBG("Old DSL[%d] of Core[%d] Thread[%d], current PSCRS[%x]",
+                             G_dsl[core_index][thread], core_index, thread, pscrs);
+
+                // Calculate new DSL
+                temp_dsl  = 0;
+                temp_srr1 = NO_STATE_LOSS;
+
+                if (pscrs & BIT32(2))
+                {
+                    temp_srr1 = SOME_STATE_LOSS_BUT_NOT_TIMEBASE;
+                    temp_dsl  = ((pscrs & BITS32(20, 4)) >> SHIFT32(23));
+
+                    if (temp_dsl >= STOP_LEVEL_11)
+                    {
+                        temp_dsl = STOP_LEVEL_11;
+                    }
+                    else if (temp_dsl >= STOP_LEVEL_8)
+                    {
+                        temp_dsl = STOP_LEVEL_8;
+                    }
+                    else if (temp_dsl >= STOP_LEVEL_4)
+                    {
+                        temp_dsl = STOP_LEVEL_4;
+                    }
+                    else if (temp_dsl >= STOP_LEVEL_2)
+                    {
+                        temp_dsl = STOP_LEVEL_2;
+                    }
+                }
+
+                G_dsl[core_index][thread] =
+                    MIN(temp_dsl, MAX(act_stop_level, G_dsl[core_index][thread]));
+
+                PK_TRACE_DBG("New DSL[%d]", G_dsl[core_index][thread]);
+
+                // Calculate new SRR1
+                if (G_dsl[core_index][thread] >= STOP_LEVEL_8)
+                {
+                    srr1[thread] = MOST_STATE_LOSS;
+                }
+                else if (G_dsl[core_index][thread] >= STOP_LEVEL_4)
+                {
+                    srr1[thread] = SOME_STATE_LOSS_BUT_NOT_TIMEBASE;
+                }
+                else
+                {
+                    srr1[thread] = temp_srr1;
+                }
+
+                PK_TRACE_DBG("Srr1[%d]", srr1[thread]);
+
+                // 36-39|44-47|52-55|60-63
+                scom_data.words.lower |=
+                    ((((uint32_t)G_dsl[core_index][thread]) << SHIFT64SH(bitloc)) |
+                     (((uint32_t)srr1[thread]) << SHIFT64SH((bitloc + 3))));
+            }
+
+            // Report PLS+SRR1
+            CME_PUTSCOM(DIRECT_CONTROLS, core_mask, scom_data.value);
+        }
+    }
+
+#else
+
+    for (core_mask = 2; core_mask; core_mask--)
+    {
+        if (core & core_mask)
+        {
+            CME_GETSCOM(PPM_SSHSRC, core_mask, CME_SCOM_AND, scom_data.value);
+
+            act_stop_level = (scom_data.words.upper & BITS32(8, 4)) >> SHIFT32(11);
+            scom_data.words.upper = 0;
+
+            if (act_stop_level >= STOP_LEVEL_8)
+            {
+                // MOST_STATE_LOSS(3) + b32/40/48/56
+                scom_data.words.lower =
+                    ((BIT64SH(32) | BITS64SH(38, 3) | BITS64SH(46, 3)  |
+                      BITS64SH(54, 3) | BITS64SH(62, 2)) |
+                     (act_stop_level << SHIFT64SH(36)) |
+                     (act_stop_level << SHIFT64SH(44)) |
+                     (act_stop_level << SHIFT64SH(52)) |
+                     (act_stop_level << SHIFT64SH(60)));
+            }
+            else if (act_stop_level >= STOP_LEVEL_4)
+            {
+                // SOME_STATE_LOSS_BUT_NOT_TIMEBASE(2)
+                scom_data.words.lower =
+                    ((BIT64SH(32) | BIT64SH(40) | BIT64SH(48) | BIT64SH(56)) |
+                     (BIT64SH(38) | BIT64SH(46) | BIT64SH(54) | BIT64SH(62)) |
+                     (act_stop_level << SHIFT64SH(36)) |
+                     (act_stop_level << SHIFT64SH(44)) |
+                     (act_stop_level << SHIFT64SH(52)) |
+                     (act_stop_level << SHIFT64SH(60)));
+            }
+            else
+            {
+                // SOME_STATE_LOSS_BUT_NOT_TIMEBASE(2) vs NO_STATE_LOSS(1)
+                scom_data.words.lower =
+                    ((BIT64SH(32) | BIT64SH(40) | BIT64SH(48) | BIT64SH(56)) |
+                     (act_stop_level << SHIFT64SH(36)) |
+                     (act_stop_level << SHIFT64SH(44)) |
+                     (act_stop_level << SHIFT64SH(52)) |
+                     (act_stop_level << SHIFT64SH(60)) |
+                     (((in32(CME_LCL_PSCRS00) & BIT32(2)) ?
+                       SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(39)) |
+                     (((in32(CME_LCL_PSCRS10) & BIT32(2)) ?
+                       SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(47)) |
+                     (((in32(CME_LCL_PSCRS20) & BIT32(2)) ?
+                       SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(55)) |
+                     (((in32(CME_LCL_PSCRS30) & BIT32(2)) ?
+                       SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS)));
+            }
+
+            CME_PUTSCOM(DIRECT_CONTROLS, core_mask, scom_data.value);
+        }
+    }
+
+#endif
+
+    PK_TRACE_INF("SX.0A: Core[%d] Waking up(pm_exit=1) via SICR[4/5]", core);
+    out32(CME_LCL_SICR_OR, core << SHIFT32(5));
+
+    PK_TRACE_DBG("Polling for Core Waking up(pm_active=0) via EINR[20/21]");
+
+    while((in32(CME_LCL_EINR)) & (core << SHIFT32(21)));
+
+#ifdef USE_PPE_IMPRECISE_MODE
+
+    // execute sync before change pcbmux to prevent queued scom issues
+    sync();
+
+#endif
+
+    PK_TRACE_DBG("Core Release PCB Mux via SICR[10/11]");
+    p9_cme_release_pcbmux(core);
+
+    PK_TRACE("Update STOP history: STOP exit completed, core ready");
+    scom_data.words.lower = 0;
+    scom_data.words.upper = SSH_EXIT_COMPLETE;
+    CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value);
+
+    for (core_mask = 2; core_mask; core_mask--)
+    {
+        if (core & core_mask)
+        {
+            G_cme_stop_record.req_level[core_mask & 1] = 0;
+            G_cme_stop_record.act_level[core_mask & 1] = 0;
+        }
+    }
+
+    G_cme_stop_record.core_running |=  core;
+    G_cme_stop_record.core_stopgpe &= ~core;
+
+    PK_TRACE_DBG("Drop halt STOP override disable via LMCR[14/15]");
+    out32(CME_LCL_LMCR_CLR, (core << SHIFT32(15)));
+
+#if SPWU_AUTO
+
+    PK_TRACE_DBG("Drop auto spwu disable, enable auto spwu via LMCR[12/13]");
+    out32(CME_LCL_LMCR_CLR, core << SHIFT32(13));
+
+    PK_TRACE_INF("SX.0B: Core Drop PM_EXIT via SICR[4/5]");
+    out32(CME_LCL_SICR_CLR, core << SHIFT32(5));
+
+#else
+
+    if (spwu_stop)
+    {
+        // done = spwu + !pm_active + !core_chiplet_fence + !pcbmux_req + !pcbmux_grant
+        // chiplet fence forces pm_active to zero
+        // Note: pm_exit is asserted above for every core waking up including spwu
+        PK_TRACE_INF("SX.0B: Core[%d] Assert SPWU_DONE via SICR[16/17]", spwu_stop);
+        out32(CME_LCL_EISR_CLR, spwu_stop << SHIFT32(15));  // clear spwu in EISR
+        out32(CME_LCL_EIPR_CLR, spwu_stop << SHIFT32(15));  // flip EIPR to falling edge
+        out32(CME_LCL_SICR_OR,  spwu_stop << SHIFT32(17));  // assert spwu_done now
+        G_cme_stop_record.core_in_spwu |= spwu_stop;
+    }
+
+    if ((core = (core & (~spwu_stop))))
+    {
+        PK_TRACE_INF("SX.0C: Core[%d] isnt SPWUed, Drop PM_EXIT via SICR[4/5]", core);
+        out32(CME_LCL_SICR_CLR, core << SHIFT32(5));
+    }
+
+#endif
+
+}
+
+
+void p9_cme_stop_exit_lv2(uint32_t core)
+{
+    //--------------------------------------------------------------------------
+    PK_TRACE("+++++ +++++ STOP LEVEL 2 EXIT +++++ +++++");
+    //--------------------------------------------------------------------------
+
+    //============================
+    MARK_TAG(SX_STARTCLOCKS, core)
+    //============================
+
+    // do this again here for stop2 in addition to chiplet_reset
+    // Note IPL doesnt need to do this twice
+    PK_TRACE("Assert core glitchless mux to DPLL via CGCR[3]");
+    CME_PUTSCOM(C_PPM_CGCR, core, BIT64(3));
+
+    // do this after assert glsmux so glitch can have time to resolve
+    // catchup to stop2 exit will acquire here
+    PK_TRACE_DBG("Core Ensure Pcb Mux");
+    p9_cme_acquire_pcbmux(core, 1);
+
+    PK_TRACE_INF("SX.2A: Core[%d] Start Clock", core);
+    p9_hcd_core_startclocks(core);
+
+    PK_TRACE("Clear CPPM PECE shadow via PECES");
+    CME_PUTSCOM(CPPM_PECES, core, 0);
+}
+
+
+
 #if !SKIP_EXIT_CATCHUP
 
 int
@@ -108,7 +368,7 @@ p9_cme_stop_exit_catchup(uint32_t* core,
 
 #endif
 
-int
+void
 p9_cme_stop_exit()
 {
     int          d2u4_flag         = 0;
@@ -120,20 +380,12 @@ p9_cme_stop_exit()
     uint32_t     wakeup            = 0;
     uint32_t     core              = 0;
     uint32_t     core_mask         = 0;
-    uint32_t     act_stop_level    = 0;
     data64_t     scom_data         = {0};
 #if !SPWU_AUTO
     uint32_t     spwu_stop         = 0;
     uint32_t     spwu_wake         = 0;
 #endif
 #if HW386841_DD1_DSL_STOP1_FIX
-    uint8_t      srr1[MAX_THREADS_PER_CORE] = {0, 0, 0, 0};
-    uint32_t     pscrs             = 0;
-    uint32_t     bitloc            = 0;
-    uint32_t     thread            = 0;
-    uint32_t     temp_dsl          = 0;
-    uint32_t     temp_srr1         = 0;
-    uint32_t     core_index        = 0;
     uint32_t     core_stop1        = 0;
 #endif
 
@@ -192,7 +444,7 @@ p9_cme_stop_exit()
         if (!core)
         {
             PK_TRACE_INF("WARNING: Only Freebie Special Wakeup Processed. Return");
-            return CME_STOP_SUCCESS;
+            return;
         }
     }
 
@@ -222,13 +474,21 @@ p9_cme_stop_exit()
         }
     }
 
-    PK_TRACE_INF("SX.1A: Core[%d] Requested Stop1 Exit", core_stop1);
+    if (core_stop1)
+    {
+        PK_TRACE_INF("SX.1A: Core[%d] Requested Stop1 Exit", core_stop1);
+        p9_cme_stop_exit_end(core_stop1, spwu_stop);
 
-    core = core & ~core_stop1;
+        core = core & ~core_stop1;
 
-    if (!core)
-    {
-        goto STOP1_EXIT;
+        if (!core)
+        {
+            //===========================
+            MARK_TRAP(ENDSCOPE_STOP_EXIT)
+            //===========================
+
+            return;
+        }
     }
 
 #endif
@@ -270,8 +530,27 @@ p9_cme_stop_exit()
     scom_data.words.upper = SSH_EXIT_IN_SESSION;
     CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value);
 
+    if (target_level == STOP_LEVEL_2)
+    {
+        p9_cme_stop_exit_lv2(core);
+
+        PK_TRACE("Drop chiplet fence via NC0INDIR[18]");
+        CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(18));
 
+        p9_cme_stop_exit_end(core, spwu_stop);
 
+        core         = deeper_core;
+        target_level = deeper_level;
+
+        if (!core)
+        {
+            //===========================
+            MARK_TRAP(ENDSCOPE_STOP_EXIT)
+            //===========================
+
+            return;
+        }
+    }
 
     if (deeper_level >= STOP_LEVEL_4)
     {
@@ -438,31 +717,7 @@ p9_cme_stop_exit()
         //disable ivrm?
     }
 
-
-
-    //--------------------------------------------------------------------------
-    PK_TRACE("+++++ +++++ STOP LEVEL 2 EXIT +++++ +++++");
-    //--------------------------------------------------------------------------
-
-    //============================
-    MARK_TAG(SX_STARTCLOCKS, core)
-    //============================
-
-    // do this again here for stop2 in addition to chiplet_reset
-    // Note IPL doesnt need to do this twice
-    PK_TRACE("Assert core glitchless mux to DPLL via CGCR[3]");
-    CME_PUTSCOM(C_PPM_CGCR, core, BIT64(3));
-
-    // do this after assert glsmux so glitch can have time to resolve
-    // catchup to stop2 exit will acquire here
-    PK_TRACE_DBG("Core Ensure Pcb Mux");
-    p9_cme_acquire_pcbmux(core, 1);
-
-    PK_TRACE_INF("SX.2A: Core[%d] Start Clock", core);
-    p9_hcd_core_startclocks(core);
-
-    PK_TRACE("Clear CPPM PECE shadow via PECES");
-    CME_PUTSCOM(CPPM_PECES, core, 0);
+    p9_cme_stop_exit_lv2(core);
 
     if (target_level < STOP_LEVEL_4)
     {
@@ -479,8 +734,6 @@ p9_cme_stop_exit()
         }
     }
 
-
-
     if (deeper_level >= STOP_LEVEL_4)
     {
 
@@ -684,226 +937,11 @@ p9_cme_stop_exit()
     MARK_TRAP(SX_ENABLE_ANALOG)
     //=========================
 
-    //--------------------------------------------------------------------------
-    PK_TRACE("+++++ +++++ END OF STOP EXIT +++++ +++++");
-    //--------------------------------------------------------------------------
-
-    PK_TRACE_DBG("Restore PSSCR.PLS+SRR1 back to actual level");
-
-#if HW386841_DD1_DSL_STOP1_FIX
-
-STOP1_EXIT:
-
-    core = core | core_stop1;
-
-    for (core_mask = 2; core_mask; core_mask--)
-    {
-        if (core & core_mask)
-        {
-            CME_GETSCOM(PPM_SSHSRC, core_mask, CME_SCOM_AND, scom_data.value);
-
-            core_index            = core_mask & 1;
-            act_stop_level        = (scom_data.words.upper & BITS32(8, 4)) >> SHIFT32(11);
-            scom_data.words.lower = (BIT64SH(32) | BIT64SH(40) | BIT64SH(48) | BIT64SH(56));
-            scom_data.words.upper = 0;
-
-            for (thread = 0, bitloc = 36;
-                 thread < MAX_THREADS_PER_CORE;
-                 thread++,   bitloc += 8)
-            {
-                // address are 0x20 apart between threads and 0x80 apart between cores
-                pscrs = in32((CME_LCL_PSCRS00 + (core_index << 7) + (thread << 5)));
-
-                PK_TRACE_DBG("Old DSL[%d] of Core[%d] Thread[%d], current PSCRS[%x]",
-                             G_dsl[core_index][thread], core_index, thread, pscrs);
-
-                // Calculate new DSL
-                temp_dsl  = 0;
-                temp_srr1 = NO_STATE_LOSS;
-
-                if (pscrs & BIT32(2))
-                {
-                    temp_srr1 = SOME_STATE_LOSS_BUT_NOT_TIMEBASE;
-                    temp_dsl  = ((pscrs & BITS32(20, 4)) >> SHIFT32(23));
-
-                    if (temp_dsl >= STOP_LEVEL_11)
-                    {
-                        temp_dsl = STOP_LEVEL_11;
-                    }
-                    else if (temp_dsl >= STOP_LEVEL_8)
-                    {
-                        temp_dsl = STOP_LEVEL_8;
-                    }
-                    else if (temp_dsl >= STOP_LEVEL_4)
-                    {
-                        temp_dsl = STOP_LEVEL_4;
-                    }
-                    else if (temp_dsl >= STOP_LEVEL_2)
-                    {
-                        temp_dsl = STOP_LEVEL_2;
-                    }
-                }
-
-                G_dsl[core_index][thread] =
-                    MIN(temp_dsl, MAX(act_stop_level, G_dsl[core_index][thread]));
-
-                PK_TRACE_DBG("New DSL[%d]", G_dsl[core_index][thread]);
-
-                // Calculate new SRR1
-                if (G_dsl[core_index][thread] >= STOP_LEVEL_8)
-                {
-                    srr1[thread] = MOST_STATE_LOSS;
-                }
-                else if (G_dsl[core_index][thread] >= STOP_LEVEL_4)
-                {
-                    srr1[thread] = SOME_STATE_LOSS_BUT_NOT_TIMEBASE;
-                }
-                else
-                {
-                    srr1[thread] = temp_srr1;
-                }
-
-                PK_TRACE_DBG("Srr1[%d]", srr1[thread]);
-
-                // 36-39|44-47|52-55|60-63
-                scom_data.words.lower |=
-                    ((((uint32_t)G_dsl[core_index][thread]) << SHIFT64SH(bitloc)) |
-                     (((uint32_t)srr1[thread]) << SHIFT64SH((bitloc + 3))));
-            }
-
-            // Report PLS+SRR1
-            CME_PUTSCOM(DIRECT_CONTROLS, core_mask, scom_data.value);
-        }
-    }
-
-#else
-
-    for (core_mask = 2; core_mask; core_mask--)
-    {
-        if (core & core_mask)
-        {
-            CME_GETSCOM(PPM_SSHSRC, core_mask, CME_SCOM_AND, scom_data.value);
-
-            act_stop_level = (scom_data.words.upper & BITS32(8, 4)) >> SHIFT32(11);
-            scom_data.words.upper = 0;
-
-            if (act_stop_level >= STOP_LEVEL_8)
-            {
-                // MOST_STATE_LOSS(3) + b32/40/48/56
-                scom_data.words.lower =
-                    ((BIT64SH(32) | BITS64SH(38, 3) | BITS64SH(46, 3)  |
-                      BITS64SH(54, 3) | BITS64SH(62, 2)) |
-                     (act_stop_level << SHIFT64SH(36)) |
-                     (act_stop_level << SHIFT64SH(44)) |
-                     (act_stop_level << SHIFT64SH(52)) |
-                     (act_stop_level << SHIFT64SH(60)));
-            }
-            else if (act_stop_level >= STOP_LEVEL_4)
-            {
-                // SOME_STATE_LOSS_BUT_NOT_TIMEBASE(2)
-                scom_data.words.lower =
-                    ((BIT64SH(32) | BIT64SH(40) | BIT64SH(48) | BIT64SH(56)) |
-                     (BIT64SH(38) | BIT64SH(46) | BIT64SH(54) | BIT64SH(62)) |
-                     (act_stop_level << SHIFT64SH(36)) |
-                     (act_stop_level << SHIFT64SH(44)) |
-                     (act_stop_level << SHIFT64SH(52)) |
-                     (act_stop_level << SHIFT64SH(60)));
-            }
-            else
-            {
-                // SOME_STATE_LOSS_BUT_NOT_TIMEBASE(2) vs NO_STATE_LOSS(1)
-                scom_data.words.lower =
-                    ((BIT64SH(32) | BIT64SH(40) | BIT64SH(48) | BIT64SH(56)) |
-                     (act_stop_level << SHIFT64SH(36)) |
-                     (act_stop_level << SHIFT64SH(44)) |
-                     (act_stop_level << SHIFT64SH(52)) |
-                     (act_stop_level << SHIFT64SH(60)) |
-                     (((in32(CME_LCL_PSCRS00) & BIT32(2)) ?
-                       SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(39)) |
-                     (((in32(CME_LCL_PSCRS10) & BIT32(2)) ?
-                       SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(47)) |
-                     (((in32(CME_LCL_PSCRS20) & BIT32(2)) ?
-                       SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS) << SHIFT64SH(55)) |
-                     (((in32(CME_LCL_PSCRS30) & BIT32(2)) ?
-                       SOME_STATE_LOSS_BUT_NOT_TIMEBASE : NO_STATE_LOSS)));
-            }
-
-            CME_PUTSCOM(DIRECT_CONTROLS, core_mask, scom_data.value);
-        }
-    }
-
-#endif
-
-    PK_TRACE_INF("SX.0A: Core[%d] Waking up(pm_exit=1) via SICR[4/5]", core);
-    out32(CME_LCL_SICR_OR, core << SHIFT32(5));
-
-    PK_TRACE_DBG("Polling for Core Waking up(pm_active=0) via EINR[20/21]");
-
-    while((in32(CME_LCL_EINR)) & (core << SHIFT32(21)));
-
-#ifdef USE_PPE_IMPRECISE_MODE
-
-    // execute sync before change pcbmux to prevent queued scom issues
-    sync();
-
-#endif
-
-    PK_TRACE_DBG("Core Release PCB Mux via SICR[10/11]");
-    p9_cme_release_pcbmux(core);
-
-    PK_TRACE("Update STOP history: STOP exit completed, core ready");
-    scom_data.words.lower = 0;
-    scom_data.words.upper = SSH_EXIT_COMPLETE;
-    CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value);
-
-    for (core_mask = 2; core_mask; core_mask--)
-    {
-        if (core & core_mask)
-        {
-            G_cme_stop_record.req_level[core_mask & 1] = 0;
-            G_cme_stop_record.act_level[core_mask & 1] = 0;
-        }
-    }
-
-    G_cme_stop_record.core_running |=  core;
-    G_cme_stop_record.core_stopgpe &= ~core;
-
-    PK_TRACE_DBG("Drop halt STOP override disable via LMCR[14/15]");
-    out32(CME_LCL_LMCR_CLR, (core << SHIFT32(15)));
-
-#if SPWU_AUTO
-
-    PK_TRACE_DBG("Drop auto spwu disable, enable auto spwu via LMCR[12/13]");
-    out32(CME_LCL_LMCR_CLR, core << SHIFT32(13));
-
-    PK_TRACE_INF("SX.0B: Core Drop PM_EXIT via SICR[4/5]");
-    out32(CME_LCL_SICR_CLR, core << SHIFT32(5));
-
-#else
-
-    if (spwu_stop)
-    {
-        // done = spwu + !pm_active + !core_chiplet_fence + !pcbmux_req + !pcbmux_grant
-        // chiplet fence forces pm_active to zero
-        // Note: pm_exit is asserted above for every core waking up including spwu
-        PK_TRACE_INF("SX.0B: Core[%d] Assert SPWU_DONE via SICR[16/17]", spwu_stop);
-        out32(CME_LCL_EISR_CLR, spwu_stop << SHIFT32(15));  // clear spwu in EISR
-        out32(CME_LCL_EIPR_CLR, spwu_stop << SHIFT32(15));  // flip EIPR to falling edge
-        out32(CME_LCL_SICR_OR,  spwu_stop << SHIFT32(17));  // assert spwu_done now
-        G_cme_stop_record.core_in_spwu |= spwu_stop;
-    }
-
-    if ((core = (core & (~spwu_stop))))
-    {
-        PK_TRACE_INF("SX.0C: Core[%d] isnt SPWUed, Drop PM_EXIT via SICR[4/5]", core);
-        out32(CME_LCL_SICR_CLR, core << SHIFT32(5));
-    }
-
-#endif
+    p9_cme_stop_exit_end(core, spwu_stop);
 
     //===========================
     MARK_TRAP(ENDSCOPE_STOP_EXIT)
     //===========================
 
-    return CME_STOP_SUCCESS;
+    return;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c
index aed2dec1..72011bc2 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c
@@ -28,10 +28,9 @@
 #include "p9_cme_stop_exit_marks.h"
 #include "p9_ringid_cme_enums.h"
 
-int
+void
 p9_hcd_core_arrayinit(uint32_t core)
 {
-    int rc = CME_STOP_SUCCESS;
     uint64_t scom_data = 0;
 
 #if RUN_NDD1_ABIST_IN_PARALLEL_MODE
@@ -109,6 +108,4 @@ p9_hcd_core_arrayinit(uint32_t core)
 
     PK_TRACE("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
     CME_PUTSCOM(C_CPLT_CONF0_CLEAR, core, BIT64(34));
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_init.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_init.c
index 3d1ef150..8308d8a6 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_init.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_init.c
@@ -26,10 +26,8 @@
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
 
-int
+void
 p9_hcd_core_chiplet_init(uint32_t core)
 {
-    int rc = CME_STOP_SUCCESS;
-
-    return rc;
+    return;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
index 677c1310..e9a960ee 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
@@ -46,10 +46,9 @@ enum P9_HCD_CORE_CHIPLET_RESET_CONSTANTS
                                BIT64(16) | BIT64(18) | BIT64(22) | BITS64(25, 2))
 };
 
-int
+void
 p9_hcd_core_chiplet_reset(uint32_t core)
 {
-    int rc             = CME_STOP_SUCCESS;
     data64_t scom_data = {0};
 
     PK_TRACE("Init NET_CTRL0[1,3-5,11-14,16,18,22,25,26],step needed for hotplug");
@@ -113,6 +112,4 @@ p9_hcd_core_chiplet_reset(uint32_t core)
 
     PK_TRACE("Drop core progdly bypass(skewadjust) via NET_CTRL1[2]");
     CME_PUTSCOM(CPPM_NC1INDIR_CLR, core, BIT64(2));
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c
index 5cc11f26..fbc8ddf5 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c
@@ -28,16 +28,12 @@
 #include "p9_cme_stop_exit_marks.h"
 #include "p9_ringid_cme_enums.h"
 
-int
+void
 p9_hcd_core_gptr_time_initf(uint32_t core)
 {
-    int rc = CME_STOP_SUCCESS;
-
     PK_TRACE("Scan ec_gptr ring core value %d", core);
     putRing(core, CME_SCOM_EQ, ec_gptr);
 
     PK_TRACE("Scan ec_time ring core value %d", core);
     putRing(core, CME_SCOM_EQ, ec_time);
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c
index a544cc76..db91d946 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_initf.c
@@ -28,16 +28,12 @@
 #include "p9_cme_stop_exit_marks.h"
 #include "p9_ringid_cme_enums.h"
 
-int
+void
 p9_hcd_core_initf(uint32_t core)
 {
-    int rc = CME_STOP_SUCCESS;
-
     PK_TRACE("Scan ec_func ring core value %d", core);
     putRing(core, CME_SCOM_EQ, ec_func);
 
     PK_TRACE("Scan ec_mode ring core value %d", core);
     putRing(core, CME_SCOM_EQ, ec_mode);
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_occ_runtime_scom.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_occ_runtime_scom.c
index d8fcbbbf..d041fde7 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_occ_runtime_scom.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_occ_runtime_scom.c
@@ -26,8 +26,8 @@
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
 
-int
+void
 p9_hcd_core_occ_runtime_scom(uint32_t core)
 {
-    return 0;
+    return;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c
index 2f2e37ce..ccd27bfa 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_pcb_arb.c
@@ -26,7 +26,7 @@
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
 
-int
+void
 p9_hcd_core_pcb_arb(uint32_t core, uint8_t req_rel)
 {
     uint32_t sisr = 0;
@@ -42,6 +42,4 @@ p9_hcd_core_pcb_arb(uint32_t core, uint8_t req_rel)
         }
     }
     while(1);
-
-    return CME_STOP_SUCCESS;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
index 626c87eb..372e3198 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
@@ -26,11 +26,9 @@
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
 
-int
+void
 p9_hcd_core_poweron(uint32_t core)
 {
-    int rc = CME_STOP_SUCCESS;
-
     PK_TRACE("Drop chiplet enable via NET_CTRL0[0]");
     CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(0));
 
@@ -89,6 +87,4 @@ p9_hcd_core_poweron(uint32_t core)
     PK_TRACE("Turn Off Force Von");
     CME_PUTSCOM(PPM_PFCS_CLR, core, BITS64(0, 2));
 #endif
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_ras_runtime_scom.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_ras_runtime_scom.c
index ddabf844..cf19004e 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_ras_runtime_scom.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_ras_runtime_scom.c
@@ -26,8 +26,8 @@
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
 
-int
+void
 p9_hcd_core_ras_runtime_scom(uint32_t core)
 {
-    return 0;
+    return;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_repair_initf.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_repair_initf.c
index 013e85a3..13ec6b91 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_repair_initf.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_repair_initf.c
@@ -28,10 +28,10 @@
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
 #include "p9_ringid_cme_enums.h"
-int
+
+void
 p9_hcd_core_repair_initf(uint32_t core)
 {
-    int rc = CME_STOP_SUCCESS;
     int i = 0;
 
     // Markers needed for repair ininf
@@ -55,6 +55,4 @@ p9_hcd_core_repair_initf(uint32_t core)
         PK_TRACE("Scan ec_repr ring core value %d", core);
         putRing(core, CME_SCOM_EQ, ec_repr);
     }
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c
index bd3c39e8..9ee7436f 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c
@@ -26,10 +26,9 @@
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
 
-int
+void
 p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type)
 {
-    int rc = CME_STOP_SUCCESS;
 #if EPM_BROADSIDE_SCAN0
     // clean up the scan region
     CME_PUTSCOM(PERV_SCAN_REGION_TYPE, core, 0);
@@ -88,5 +87,4 @@ p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type)
     PK_TRACE("Clear Scan Select Register");
     CME_PUTSCOM(PERV_SCAN_REGION_TYPE, core, 0);
 #endif
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scomcust.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scomcust.c
index 5a970f08..d76f5b85 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scomcust.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scomcust.c
@@ -26,11 +26,9 @@
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
 
-int
+void
 p9_hcd_core_scomcust(uint32_t core)
 {
     PK_TRACE("Drop chiplet fence via NC0INDIR[18]");
     CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(18));
-
-    return 0;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
index e2665b62..f826a15d 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
@@ -43,10 +43,9 @@ enum P9_HCD_CORE_SCOMINIT_CONSTANTS
     NEST_HANG_LIMIT_200_HANG_PULSES = 0x64
 };
 
-int
+void
 p9_hcd_core_scominit(uint32_t core)
 {
-    int      rc        = CME_STOP_SUCCESS;
     data64_t scom_data = {0};
 
     // how about bit 6?
@@ -78,6 +77,4 @@ p9_hcd_core_scominit(uint32_t core)
 #endif
     scom_data.words.upper |= (NEST_HANG_LIMIT_100_HANG_PULSES << SHIFT32(15));
     CME_PUTSCOM(C_HANG_CONTROL, core, scom_data.value);
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
index 9a540e17..8b965de0 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
@@ -26,10 +26,9 @@
 #include "p9_cme_stop.h"
 #include "p9_cme_stop_exit_marks.h"
 
-int
+void
 p9_hcd_core_startclocks(uint32_t core)
 {
-    int      rc        = CME_STOP_SUCCESS;
     uint32_t id_vector = 0;
     data64_t scom_data = {0};
 
@@ -151,6 +150,4 @@ p9_hcd_core_startclocks(uint32_t core)
 
     PK_TRACE("Drop Core-L2/CC/TLBIE Quiesces via CME_LCL_SICR[6,8]/[7,9][21]");
     out32(CME_LCL_SICR_CLR, ((core << SHIFT32(7)) | (core << SHIFT32(9)) | BIT32(21)));
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c
index 2d394c66..fd6a4ee5 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c
@@ -26,10 +26,9 @@
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
 
-int
+void
 p9_hcd_cache_arrayinit(uint32_t quad, uint32_t ex)
 {
-    int rc             = SGPE_STOP_SUCCESS;
     uint64_t scom_data = 0;
 
     PK_TRACE("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
@@ -115,6 +114,4 @@ p9_hcd_cache_arrayinit(uint32_t quad, uint32_t ex)
 
     PK_TRACE("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CONF0_CLEAR, quad), BIT64(34));
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_init.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_init.c
index 04709af2..9e94fa90 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_init.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_init.c
@@ -26,10 +26,8 @@
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
 
-int
+void
 p9_hcd_cache_chiplet_init(uint32_t quad)
 {
-    int rc = SGPE_STOP_SUCCESS;
-
-    return rc;
+    return;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C
index fadc87c4..08400d52 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C
@@ -43,9 +43,8 @@
 #include <fapi2.H>
 
 
-extern "C" int p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t quad)
+extern "C" void p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t quad)
 {
-    int rc = SGPE_STOP_SUCCESS;
     fapi2::Target<fapi2::TARGET_TYPE_EQ>           l_eqTarget
     (
         fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET)
@@ -67,5 +66,4 @@ extern "C" int p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t quad)
 fapi_try_exit:
 
     FAPI_DBG("<<p9_hcd_cache_chiplet_l3_dcc_setup");
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c
index a5e70627..65bef949 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c
@@ -48,10 +48,9 @@ enum P9_HCD_CACHE_CHIPLET_RESET_CONSTANTS
                                BIT64(18) | BIT64(22) | BITS64(25, 2))
 };
 
-int
+void
 p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex)
 {
-    int rc              = SGPE_STOP_SUCCESS;
     uint64_t scom_data  = 0;
     uint32_t core       = 0;
     uint32_t cbit       = 0;
@@ -275,6 +274,4 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex)
 
     p9_hcd_cache_scan0(quad, regions, SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME);
 #endif
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C
index 8f92f54c..8e5d9485 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C
@@ -43,9 +43,8 @@
 
 
 
-extern "C" int p9_hcd_cache_dcc_skewadjust_setup(uint32_t quad)
+extern "C" void p9_hcd_cache_dcc_skewadjust_setup(uint32_t quad)
 {
-    int rc = SGPE_STOP_SUCCESS;
     fapi2::Target<fapi2::TARGET_TYPE_EQ>        l_eqTarget
     (
         fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET)
@@ -140,5 +139,4 @@ extern "C" int p9_hcd_cache_dcc_skewadjust_setup(uint32_t quad)
 fapi_try_exit:
 
     FAPI_DBG("<<p9_hcd_cache_dcc_skewadjust_setup");
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_initf.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_initf.C
index 5fb0c021..4e7b67cc 100755
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_initf.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_initf.C
@@ -29,9 +29,8 @@
 #include "p9_ringid_sgpe.H"
 #include <fapi2.H>
 
-extern "C" int p9_hcd_cache_dpll_initf(uint32_t quad)
+extern "C" void p9_hcd_cache_dpll_initf(uint32_t quad)
 {
-    int rc = SGPE_STOP_SUCCESS;
     fapi2::Target<fapi2::TARGET_TYPE_EQ> l_eqTarget
     (
         fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET)
@@ -48,6 +47,4 @@ extern "C" int p9_hcd_cache_dpll_initf(uint32_t quad)
     // Markers needed for cache ininf
 fapi_try_exit:
     FAPI_INF("<<p9_hcd_cache_dpll_initf");
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c
index 95d9f312..a26abf0f 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c
@@ -26,10 +26,9 @@
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
 
-int
+void
 p9_hcd_cache_dpll_setup(uint32_t quad)
 {
-    int      rc        = SGPE_STOP_SUCCESS;
     uint64_t scom_data = 0;
 
     PK_TRACE("Drop analog logic fence via QPPM_PFCS[11]");
@@ -110,6 +109,4 @@ p9_hcd_cache_dpll_setup(uint32_t quad)
 
     PK_TRACE("Drop skew/duty cycle adjust func_clksel via NET_CTRL0[22]");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), ~BIT64(22));
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_gptr_time_initf.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_gptr_time_initf.C
index 3725e197..887ac09d 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_gptr_time_initf.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_gptr_time_initf.C
@@ -60,11 +60,9 @@
 //------------------------------------------------------------------------------
 
 
-extern "C" int p9_hcd_cache_gptr_time_initf(uint32_t quad)
+extern "C" void p9_hcd_cache_gptr_time_initf(uint32_t quad)
 {
     FAPI_INF(">>p9_hcd_cache_gptr_time_initf");
-
-    int rc = SGPE_STOP_SUCCESS;
     fapi2::Target<fapi2::TARGET_TYPE_EQ> l_eqTarget
     (
         fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET)
@@ -108,5 +106,4 @@ extern "C" int p9_hcd_cache_gptr_time_initf(uint32_t quad)
 fapi_try_exit:
 
     FAPI_INF("<<9_hcd_cache_gptr_time_init");
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_initf.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_initf.C
index 4388cbd9..da637bf2 100755
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_initf.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_initf.C
@@ -29,9 +29,8 @@
 #include "p9_ringid_sgpe.H"
 #include <fapi2.H>
 
-extern "C" int p9_hcd_cache_initf(uint32_t quad)
+extern "C" void p9_hcd_cache_initf(uint32_t quad)
 {
-    int rc = SGPE_STOP_SUCCESS;
     fapi2::Target<fapi2::TARGET_TYPE_EQ> l_eqTarget
     (
         fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET)
@@ -58,6 +57,4 @@ extern "C" int p9_hcd_cache_initf(uint32_t quad)
     // Markers needed for cache ininf
 fapi_try_exit:
     FAPI_INF("<<p9_hcd_cache_initf");
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
index 989492c9..40c91034 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c
@@ -28,10 +28,9 @@
 
 extern SgpeStopRecord G_sgpe_stop_record;
 
-int
+void
 p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg)
 {
-    int      rc        = SGPE_STOP_SUCCESS;
     uint64_t scom_data = 0;
 
     PK_TRACE("Drop L2 Regional Fences via CPLT_CTRL1[8/9]");
@@ -150,6 +149,4 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg)
     }
 
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_RING_FENCE_MASK_LATCH, quad), scom_data);
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_occ_runtime_scom.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_occ_runtime_scom.c
index e56de266..c0fcbda0 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_occ_runtime_scom.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_occ_runtime_scom.c
@@ -26,8 +26,8 @@
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
 
-int
+void
 p9_hcd_cache_occ_runtime_scom(uint32_t quad)
 {
-    return 0;
+    return;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c
index c8a55358..72e63ca3 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c
@@ -26,11 +26,9 @@
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
 
-int
+void
 p9_hcd_cache_poweron(uint32_t quad)
 {
-    int rc = SGPE_STOP_SUCCESS;
-
     PK_TRACE("Drop chiplet enable via NET_CTRL0[0]");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), ~BIT64(0));
 
@@ -93,6 +91,4 @@ p9_hcd_cache_poweron(uint32_t quad)
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, quad), BITS64(0, 4));
 #endif
 #endif
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_ras_runtime_scom.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_ras_runtime_scom.c
index f207ceea..0b1e9d07 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_ras_runtime_scom.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_ras_runtime_scom.c
@@ -26,8 +26,8 @@
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
 
-int
+void
 p9_hcd_cache_ras_runtime_scom(uint32_t quad)
 {
-    return 0;
+    return;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_repair_initf.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_repair_initf.C
index 61637c21..0bbff9ff 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_repair_initf.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_repair_initf.C
@@ -60,11 +60,9 @@
 //------------------------------------------------------------------------------
 
 
-extern "C" int p9_hcd_cache_repair_initf(uint32_t quad)
+extern "C" void p9_hcd_cache_repair_initf(uint32_t quad)
 {
     FAPI_INF(">>p9_hcd_cache_repair_initf");
-
-    int rc = SGPE_STOP_SUCCESS;
     fapi2::Target<fapi2::TARGET_TYPE_EQ> l_eqTarget
     (
         fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET)
@@ -91,5 +89,4 @@ extern "C" int p9_hcd_cache_repair_initf(uint32_t quad)
 fapi_try_exit:
 
     FAPI_INF("<<p9_hcd_cache_repair_initf");
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c
index 84777f05..54af6b41 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c
@@ -26,10 +26,9 @@
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
 
-int
+void
 p9_hcd_cache_scan0(uint32_t quad, uint64_t regions, uint64_t scan_type)
 {
-    int rc = SGPE_STOP_SUCCESS;
 #if EPM_BROADSIDE_SCAN0
     // clean up the scan region
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_SCAN_REGION_TYPE, quad), 0);
@@ -88,5 +87,4 @@ p9_hcd_cache_scan0(uint32_t quad, uint64_t regions, uint64_t scan_type)
     PK_TRACE("Clear Scan Select Register");
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_SCAN_REGION_TYPE, quad), 0);
 #endif
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c
index 39415c09..7228924f 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scomcust.c
@@ -26,11 +26,9 @@
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
 
-int
+void
 p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_ex, int is_stop8)
 {
-
-    int      rc        = SGPE_STOP_SUCCESS;
     data64_t scom_data = {0};
 
 #if !SKIP_HOMER_ACCESS
@@ -135,6 +133,4 @@ p9_hcd_cache_scomcust(uint32_t quad, uint32_t m_ex, int is_stop8)
         PK_TRACE("Drop chiplet fence via NET_CTRL0[18]");
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), ~BIT64(18));
     }
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
index 233c535f..1b0d7706 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c
@@ -28,10 +28,9 @@
 
 extern SgpeStopRecord G_sgpe_stop_record;
 
-int
+void
 p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8)
 {
-    uint32_t   rc                                          = SGPE_STOP_SUCCESS;
     uint32_t   attr_proc_fabric_pump_mode_chip_is_node     = 0; // default group
     uint32_t   ex_loop                                     = 0;
     uint32_t   ex_count                                    = 0;
@@ -175,6 +174,4 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8)
             }
         }
     }
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
index 9a340420..d5ae19ee 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c
@@ -26,10 +26,9 @@
 #include "p9_sgpe_stop.h"
 #include "p9_sgpe_stop_exit_marks.h"
 
-int
+void
 p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex)
 {
-    uint32_t   rc        = SGPE_STOP_SUCCESS;
     uint32_t   id_vector = 0;
     uint32_t   ex_mask   = 0;
     uint32_t   bitloc    = 0;
@@ -197,6 +196,4 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex)
     }
 
     GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_RING_FENCE_MASK_LATCH, quad), scom_data.value);
-
-    return rc;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index dd62ef7a..4a56721c 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -170,11 +170,6 @@ enum SGPE_IPC_CONSTANTS
     SGPE_IPC_RETURN_CODE_ACK          = 1
 };
 
-enum SGPE_STOP_RETURN_CODES
-{
-    SGPE_STOP_SUCCESS                 = 0
-};
-
 enum SGPE_STOP_IRQ_SHORT_NAMES
 {
     IRQ_STOP_TYPE2                    = OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING,
@@ -326,28 +321,28 @@ void p9_sgpe_ipc_pgpe_suspend_stop(ipc_msg_t* cmd, void* arg);
 void p9_sgpe_stop_pig_handler(void*, PkIrqId);
 void p9_sgpe_stop_enter_thread(void*);
 void p9_sgpe_stop_exit_thread(void*);
-int  p9_sgpe_stop_entry();
-int  p9_sgpe_stop_exit();
+void p9_sgpe_stop_entry();
+void p9_sgpe_stop_exit();
 
 /// Procedures shared between Istep4 and SGPE Stop
-int  p9_hcd_cache_scan0(uint32_t, uint64_t, uint64_t);
-int  p9_hcd_cache_poweron(uint32_t);
-int  p9_hcd_cache_chiplet_reset(uint32_t, uint32_t);
-int  p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t);
-int  p9_hcd_cache_gptr_time_initf(uint32_t);
-int  p9_hcd_cache_dpll_initf(uint32_t);
-int  p9_hcd_cache_dpll_setup(uint32_t);
-int  p9_hcd_cache_dcc_skewadjust_setup(uint32_t);
-int  p9_hcd_cache_chiplet_init(uint32_t);
-int  p9_hcd_cache_repair_initf(uint32_t);
-int  p9_hcd_cache_arrayinit(uint32_t, uint32_t ex);
-int  p9_hcd_cache_initf(uint32_t);
-int  p9_hcd_cache_startclocks(uint32_t, uint32_t);
-int  p9_hcd_cache_l2_startclocks(uint32_t, uint32_t, uint32_t);
-int  p9_hcd_cache_scominit(uint32_t, uint32_t, int);
-int  p9_hcd_cache_scomcust(uint32_t, uint32_t, int);
-int  p9_hcd_cache_ras_runtime_scom(uint32_t);
-int  p9_hcd_cache_occ_runtime_scom(uint32_t);
+void p9_hcd_cache_scan0(uint32_t, uint64_t, uint64_t);
+void p9_hcd_cache_poweron(uint32_t);
+void p9_hcd_cache_chiplet_reset(uint32_t, uint32_t);
+void p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t);
+void p9_hcd_cache_gptr_time_initf(uint32_t);
+void p9_hcd_cache_dpll_initf(uint32_t);
+void p9_hcd_cache_dpll_setup(uint32_t);
+void p9_hcd_cache_dcc_skewadjust_setup(uint32_t);
+void p9_hcd_cache_chiplet_init(uint32_t);
+void p9_hcd_cache_repair_initf(uint32_t);
+void p9_hcd_cache_arrayinit(uint32_t, uint32_t ex);
+void p9_hcd_cache_initf(uint32_t);
+void p9_hcd_cache_startclocks(uint32_t, uint32_t);
+void p9_hcd_cache_l2_startclocks(uint32_t, uint32_t, uint32_t);
+void p9_hcd_cache_scominit(uint32_t, uint32_t, int);
+void p9_hcd_cache_scomcust(uint32_t, uint32_t, int);
+void p9_hcd_cache_ras_runtime_scom(uint32_t);
+void p9_hcd_cache_occ_runtime_scom(uint32_t);
 
 #ifdef __cplusplus
 }  // extern "C"
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index 5ae7c1f7..e2c98382 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -44,7 +44,7 @@ extern SgpeStopRecord                           G_sgpe_stop_record;
 
 #endif
 
-int
+void
 p9_sgpe_stop_entry()
 {
     int          entry_ongoing[2] = {0, 0};
@@ -1145,5 +1145,5 @@ p9_sgpe_stop_entry()
     MARK_TRAP(ENDSCOPE_STOP_ENTRY)
     //============================
 
-    return SGPE_STOP_SUCCESS;
+    return;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
index f277d070..d15dc992 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
@@ -144,7 +144,190 @@ fused_core_mode_scan_fix(uint32_t qloop, int l2bit)
 
 #endif
 
-int
+void p9_sgpe_stop_exit_pre(uint32_t cexit, uint32_t qspwu,
+                           uint32_t qloop, uint32_t* m_l2, uint32_t* m_pg)
+{
+    uint32_t cloop     = 0;
+    data64_t scom_data = {0};
+
+    //--------------------------------------------------------------------------
+    PK_TRACE_INF("+++++ +++++ BEGIN OF STOP EXIT +++++ +++++");
+    //--------------------------------------------------------------------------
+
+    if (G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG] & BIT32(qloop))
+    {
+        *m_pg |= FST_EX_IN_QUAD;
+    }
+
+    if (G_sgpe_stop_record.group.ex_r[VECTOR_CONFIG] & BIT32(qloop))
+    {
+        *m_pg |= SND_EX_IN_QUAD;
+    }
+
+    if ((((cexit & BITS32(0, 2)) || (qspwu & BIT32(0))) &&
+         (G_sgpe_stop_record.state[qloop].act_state_x0 >= STOP_LEVEL_8)))
+    {
+        *m_l2 |= FST_EX_IN_QUAD;
+    }
+
+    if ((((cexit & BITS32(2, 2)) || (qspwu & BIT32(0))) &&
+         (G_sgpe_stop_record.state[qloop].act_state_x1 >= STOP_LEVEL_8)))
+    {
+        *m_l2 |= SND_EX_IN_QUAD;
+    }
+
+    *m_l2 = *m_l2 & *m_pg;
+
+    PK_TRACE("Update QSSR: stop_exit_ongoing");
+    out32(OCB_QSSR_OR, BIT32(qloop + 26));
+
+    for(cloop = 0; cloop < CORES_PER_QUAD; cloop++)
+    {
+        if(!(cexit & BIT32(cloop)))
+        {
+            continue;
+        }
+
+        PK_TRACE("Update STOP history on core[%d]: in transition of exit",
+                 ((qloop << 2) + cloop));
+        scom_data.words.lower = 0;
+        scom_data.words.upper = SSH_EXIT_IN_SESSION;
+        GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, ((qloop << 2) + cloop), 0,
+                        scom_data.value);
+    }
+}
+
+
+
+void p9_sgpe_stop_exit_lv8(uint32_t qloop, uint32_t m_l2, uint32_t m_pg)
+{
+    data64_t scom_data = {0};
+
+    //--------------------------------------------------------------------------
+    PK_TRACE("+++++ +++++ EX STOP EXIT [LEVEL 8-10] +++++ +++++");
+    //--------------------------------------------------------------------------
+
+    //========================================================
+    MARK_TAG(SX_L2_STARTCLOCKS, ((m_l2 << 6) | (32 >> qloop)))
+    //========================================================
+
+    // do this again here for stop8 in addition to dpll_setup
+    PK_TRACE("Switch L2 glsmux select to DPLL output via EXCGCR[34,35]");
+    GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_OR, qloop), BITS64(34, 2));
+
+    PK_TRACE_INF("SX.8A: Cache[%d] EX_PG[%d] Start L2[%d] Clocks",
+                 qloop, m_pg, m_l2);
+    p9_hcd_cache_l2_startclocks(qloop, m_l2, m_pg);
+
+    // for l2 scom init and restore that cannot be done via stop11
+    // as if that certain l2 wasnt exiting(thus lack of clock for scom)
+
+    PK_TRACE_INF("SX.8B: Cache L2 Scominit");
+    p9_hcd_cache_scominit(qloop, m_l2, 1);
+
+    PK_TRACE_DBG("Cache L2 Scomcust");
+    p9_hcd_cache_scomcust(qloop, m_l2, 1);
+
+    // reset ex actual state if ex is exited.
+    if (m_l2 & FST_EX_IN_QUAD)
+    {
+        G_sgpe_stop_record.state[qloop].act_state_x0 = 0;
+    }
+
+    if (m_l2 & SND_EX_IN_QUAD)
+    {
+        G_sgpe_stop_record.state[qloop].act_state_x1 = 0;
+    }
+
+    if (G_sgpe_stop_record.state[qloop].act_state_x0 == 0 &&
+        G_sgpe_stop_record.state[qloop].act_state_x1 == 0)
+    {
+        PK_TRACE("Release cache clock controller atomic lock");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CC_ATOMIC_LOCK, qloop), 0);
+        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CC_ATOMIC_LOCK, qloop), scom_data.value);
+
+        if (scom_data.words.upper & BIT32(0))
+        {
+            PK_TRACE_INF("ERROR: Failed to Release Cache %d Clk Ctrl Atomic Lock. Register Content: %x",
+                         qloop, scom_data.words.upper);
+            PK_PANIC(SGPE_STOP_EXIT_DROP_CLK_LOCK_FAILED);
+        }
+    }
+
+    PK_TRACE("Update QSSR: drop l2_stopped");
+    out32(OCB_QSSR_CLR, (m_l2 << SHIFT32((qloop << 1) + 1)));
+}
+
+
+void p9_sgpe_stop_exit_end(uint32_t cexit, uint32_t qspwu, uint32_t qloop)
+{
+    uint32_t cloop = 0;
+    data64_t scom_data = {0};
+
+    //--------------------------------------------------------------------------
+    PK_TRACE("+++++ +++++ END OF STOP EXIT +++++ +++++");
+    //--------------------------------------------------------------------------
+
+    if (qspwu & BIT32(0))
+    {
+        PK_TRACE_INF("SP.WU: Quad[%d] Assert SPWU_DONE", qloop);
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_OR, qloop), BIT64(0));
+        G_sgpe_stop_record.group.qswu[VECTOR_CONFIG] |= BIT32(qloop);
+        G_sgpe_stop_record.group.qswu[VECTOR_EXIT]   &= ~BIT32(qloop);
+    }
+
+    // process core portion of core request
+    for(cloop = 0; cloop < CORES_PER_QUAD; cloop++)
+    {
+        if(!(cexit & BIT32(cloop)))
+        {
+            continue;
+        }
+
+#if DEBUG_RUNTIME_STATE_CHECK
+
+        if(G_sgpe_stop_record.level[qloop][cloop] != 0)
+        {
+            GPE_GETSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR,
+                                           ((qloop << 2) + cloop)), scom_data.value);
+
+            if (!(scom_data.value & BIT64(13)))
+            {
+                PKTRACE("ERROR.A: core[%d] was not set before release",
+                        ((qloop << 2) + cloop));
+                pk_halt();
+            }
+        }
+
+#endif
+
+        // reset clevel to 0 if core is going to wake up
+        G_sgpe_stop_record.level[qloop][cloop] = 0;
+
+#if NIMBUS_DD_LEVEL != 1
+
+        p9_dd1_cppm_unicast_wr(
+            GPE_SCOM_ADDR_CORE(CPPM_CPMMR,     ((qloop << 2) + cloop)),
+            GPE_SCOM_ADDR_CORE(CPPM_CPMMR_OR,  ((qloop << 2) + cloop)),
+            BIT64(0), OR_OP);
+
+#endif
+
+        PK_TRACE_INF("SX.CME: Core[%d] Switch CorePPM Wakeup Back to CME via CPMMR[13]",
+                     ((qloop << 2) + cloop));
+        p9_dd1_cppm_unicast_wr(
+            GPE_SCOM_ADDR_CORE(CPPM_CPMMR,     ((qloop << 2) + cloop)),
+            GPE_SCOM_ADDR_CORE(CPPM_CPMMR_CLR, ((qloop << 2) + cloop)),
+            BIT64(13), CLR_OP);
+    }
+
+    PK_TRACE("Update QSSR: drop stop_exit_ongoing");
+    out32(OCB_QSSR_CLR, BIT32(qloop + 26));
+}
+
+
+
+void
 p9_sgpe_stop_exit()
 {
     uint32_t     m_l2            = 0;
@@ -182,6 +365,7 @@ p9_sgpe_stop_exit()
                  G_sgpe_stop_record.group.ex_r[VECTOR_EXIT],
                  G_sgpe_stop_record.group.quad[VECTOR_EXIT]);
 
+
 #if !SKIP_IPC
 
     // If any core exits, including waking up from stop5 to stop15
@@ -285,8 +469,6 @@ p9_sgpe_stop_exit()
 
 #endif
 
-
-
     for(cexit = G_sgpe_stop_record.group.core[VECTOR_EXIT],
         qspwu = G_sgpe_stop_record.group.qswu[VECTOR_EXIT],
         qloop = 0, m_l2 = 0, m_pg = 0;
@@ -298,54 +480,39 @@ p9_sgpe_stop_exit()
         {
             continue;
         }
-
-        //--------------------------------------------------------------------------
-        PK_TRACE("+++++ +++++ BEGIN OF STOP EXIT +++++ +++++");
-        //--------------------------------------------------------------------------
-
-        if (G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG] & BIT32(qloop))
+        else if (G_sgpe_stop_record.state[qloop].act_state_q >= STOP_LEVEL_11)
         {
-            m_pg |= FST_EX_IN_QUAD;
+            continue;
         }
 
-        if (G_sgpe_stop_record.group.ex_r[VECTOR_CONFIG] & BIT32(qloop))
-        {
-            m_pg |= SND_EX_IN_QUAD;
-        }
+        p9_sgpe_stop_exit_pre(cexit, qspwu, qloop, &m_l2, &m_pg);
 
-        if ((((cexit & BITS32(0, 2)) || (qspwu & BIT32(0))) &&
-             (G_sgpe_stop_record.state[qloop].act_state_x0 >= STOP_LEVEL_8)))
+        if (m_l2)
         {
-            m_l2 |= FST_EX_IN_QUAD;
+            p9_sgpe_stop_exit_lv8(qloop, m_l2, m_pg);
         }
 
-        if ((((cexit & BITS32(2, 2)) || (qspwu & BIT32(0))) &&
-             (G_sgpe_stop_record.state[qloop].act_state_x1 >= STOP_LEVEL_8)))
-        {
-            m_l2 |= SND_EX_IN_QUAD;
-        }
+        p9_sgpe_stop_exit_end(cexit, qspwu, qloop);
 
-        m_l2 = m_l2 & m_pg;
+        G_sgpe_stop_record.group.core[VECTOR_EXIT] &=
+            ~((cexit & BITS32(0, 4)) >> (qloop << 2));
+    }
 
-        PK_TRACE("Update QSSR: stop_exit_ongoing");
-        out32(OCB_QSSR_OR, BIT32(qloop + 26));
 
-        for(cloop = 0; cloop < CORES_PER_QUAD; cloop++)
-        {
-            if(!(cexit & BIT32(cloop)))
-            {
-                continue;
-            }
 
-            PK_TRACE("Update STOP history on core[%d]: in transition of exit",
-                     ((qloop << 2) + cloop));
-            scom_data.words.lower = 0;
-            scom_data.words.upper = SSH_EXIT_IN_SESSION;
-            GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, ((qloop << 2) + cloop), 0,
-                            scom_data.value);
-        }
+    for(cexit = G_sgpe_stop_record.group.core[VECTOR_EXIT],
+        qspwu = G_sgpe_stop_record.group.qswu[VECTOR_EXIT],
+        qloop = 0, m_l2 = 0, m_pg = 0;
+        (cexit > 0 || qspwu > 0) && (qloop < MAX_QUADS);
+        cexit = cexit << 4, qspwu = qspwu << 1, qloop++, m_l2 = 0, m_pg = 0)
+    {
 
+        if (!((cexit & BITS32(0, 4)) || (qspwu & BIT32(0))))
+        {
+            continue;
+        }
 
+        p9_sgpe_stop_exit_pre(cexit, qspwu, qloop, &m_l2, &m_pg);
 
         if(m_l2 && G_sgpe_stop_record.state[qloop].act_state_q >= STOP_LEVEL_11)
         {
@@ -595,60 +762,7 @@ p9_sgpe_stop_exit()
 
         if (m_l2)
         {
-
-            //--------------------------------------------------------------------------
-            PK_TRACE("+++++ +++++ EX STOP EXIT [LEVEL 8-10] +++++ +++++");
-            //--------------------------------------------------------------------------
-
-            //========================================================
-            MARK_TAG(SX_L2_STARTCLOCKS, ((m_l2 << 6) | (32 >> qloop)))
-            //========================================================
-
-            // do this again here for stop8 in addition to dpll_setup
-            PK_TRACE("Switch L2 glsmux select to DPLL output via EXCGCR[34,35]");
-            GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_OR, qloop), BITS64(34, 2));
-
-            PK_TRACE_INF("SX.8A: Cache[%d] EX_PG[%d] Start L2[%d] Clocks",
-                         qloop, m_pg, m_l2);
-            p9_hcd_cache_l2_startclocks(qloop, m_l2, m_pg);
-
-            // for l2 scom init and restore that cannot be done via stop11
-            // as if that certain l2 wasnt exiting(thus lack of clock for scom)
-
-            PK_TRACE_INF("SX.8B: Cache L2 Scominit");
-            p9_hcd_cache_scominit(qloop, m_l2, 1);
-
-            PK_TRACE_DBG("Cache L2 Scomcust");
-            p9_hcd_cache_scomcust(qloop, m_l2, 1);
-
-            // reset ex actual state if ex is exited.
-            if (m_l2 & FST_EX_IN_QUAD)
-            {
-                G_sgpe_stop_record.state[qloop].act_state_x0 = 0;
-            }
-
-            if (m_l2 & SND_EX_IN_QUAD)
-            {
-                G_sgpe_stop_record.state[qloop].act_state_x1 = 0;
-            }
-
-            if (G_sgpe_stop_record.state[qloop].act_state_x0 == 0 &&
-                G_sgpe_stop_record.state[qloop].act_state_x1 == 0)
-            {
-                PK_TRACE("Release cache clock controller atomic lock");
-                GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CC_ATOMIC_LOCK, qloop), 0);
-                GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CC_ATOMIC_LOCK, qloop), scom_data.value);
-
-                if (scom_data.words.upper & BIT32(0))
-                {
-                    PK_TRACE_INF("ERROR: Failed to Release Cache %d Clk Ctrl Atomic Lock. Register Content: %x",
-                                 qloop, scom_data.words.upper);
-                    PK_PANIC(SGPE_STOP_EXIT_DROP_CLK_LOCK_FAILED);
-                }
-            }
-
-            PK_TRACE("Update QSSR: drop l2_stopped");
-            out32(OCB_QSSR_CLR, (m_l2 << SHIFT32((qloop << 1) + 1)));
+            p9_sgpe_stop_exit_lv8(qloop, m_l2, m_pg);
         }
 
         if(m_l2 && G_sgpe_stop_record.state[qloop].act_state_q >= STOP_LEVEL_11)
@@ -933,65 +1047,7 @@ p9_sgpe_stop_exit()
             out32(OCB_QSSR_CLR, BIT32(qloop + 14));
         }
 
-        //--------------------------------------------------------------------------
-        PK_TRACE("+++++ +++++ END OF STOP EXIT +++++ +++++");
-        //--------------------------------------------------------------------------
-
-        if (qspwu & BIT32(0))
-        {
-            PK_TRACE_INF("SP.WU: Quad[%d] Assert SPWU_DONE", qloop);
-            GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_OR, qloop), BIT64(0));
-            G_sgpe_stop_record.group.qswu[VECTOR_CONFIG] |= BIT32(qloop);
-            G_sgpe_stop_record.group.qswu[VECTOR_EXIT]   &= ~BIT32(qloop);
-        }
-
-        // process core portion of core request
-        for(cloop = 0; cloop < CORES_PER_QUAD; cloop++)
-        {
-            if(!(cexit & BIT32(cloop)))
-            {
-                continue;
-            }
-
-#if DEBUG_RUNTIME_STATE_CHECK
-
-            if(G_sgpe_stop_record.level[qloop][cloop] != 0)
-            {
-                GPE_GETSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR,
-                                               ((qloop << 2) + cloop)), scom_data.value);
-
-                if (!(scom_data.value & BIT64(13)))
-                {
-                    PKTRACE("ERROR.A: core[%d] was not set before release",
-                            ((qloop << 2) + cloop));
-                    pk_halt();
-                }
-            }
-
-#endif
-
-            // reset clevel to 0 if core is going to wake up
-            G_sgpe_stop_record.level[qloop][cloop] = 0;
-
-#if NIMBUS_DD_LEVEL != 1
-
-            p9_dd1_cppm_unicast_wr(
-                GPE_SCOM_ADDR_CORE(CPPM_CPMMR,     ((qloop << 2) + cloop)),
-                GPE_SCOM_ADDR_CORE(CPPM_CPMMR_OR,  ((qloop << 2) + cloop)),
-                BIT64(0), OR_OP);
-
-#endif
-
-            PK_TRACE_INF("SX.CME: Core[%d] Switch CorePPM Wakeup Back to CME via CPMMR[13]",
-                         ((qloop << 2) + cloop));
-            p9_dd1_cppm_unicast_wr(
-                GPE_SCOM_ADDR_CORE(CPPM_CPMMR,     ((qloop << 2) + cloop)),
-                GPE_SCOM_ADDR_CORE(CPPM_CPMMR_CLR, ((qloop << 2) + cloop)),
-                BIT64(13), CLR_OP);
-        }
-
-        PK_TRACE("Update QSSR: drop stop_exit_ongoing");
-        out32(OCB_QSSR_CLR, BIT32(qloop + 26));
+        p9_sgpe_stop_exit_end(cexit, qspwu, qloop);
     }
 
     G_sgpe_stop_record.group.core[VECTOR_ACTIVE] |=
@@ -1003,5 +1059,5 @@ p9_sgpe_stop_exit()
     MARK_TRAP(ENDSCOPE_STOP_EXIT)
     //===========================
 
-    return SGPE_STOP_SUCCESS;
+    return;
 }