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* unsupported insn for bswap emittedDoug Gilbert2017-10-061-1/+1
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* Indicate that PPE42 fused branch instructions modify the CRDoug Gilbert2017-08-182-16/+27
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* Prevent unsupported load/store index updateinstructions on PPEDoug Gilbert2017-02-101-5/+119
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* Fix compile issue when compiling with gcc 6Douglas Gilbert2017-01-171-2/+2
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* Fix insn attribute length field for load zero-extend operationDoug Gilbert2016-10-282-29/+22
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* PPE42 compare immediate branch with immediate value out of rangeDoug Gilbert2016-09-131-4/+21
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* requre 8 byte alignment on offsettable memory access for 64bit load/storeDoug Gilbert2016-08-153-6/+27
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* Add RTL to correctly handle unavailable lwzux instructionDoug Gilbert2016-08-151-2/+15
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* PPE42 compiler generates invalid crnot instructionDoug Gilbert2016-08-151-2/+6
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* Turn off 64bit load/stores in epilog/proglogDoug Gilbert2016-08-152-4/+6
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* Fix PPE42 illegal stwux asm commandDoug Gilbert2016-08-152-2/+26
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* Unsigned compare immediate branch emitting wrong instructionsDoug Gilbert2016-08-152-1/+7
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* Remove more places lbzux was being usedDoug Gilbert2016-08-151-466/+507
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* Fix where signed compare should be unsigned compareDoug Gilbert2016-08-151-11/+10
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* Delivered 05/2015Doug Gilbert2016-08-152-1/+3
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* provide clrbwibcDoug Gilbert2016-08-152-30/+45
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* bnbwi supportDoug Gilbert2016-08-154-6/+144
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* Add ppe405 and ppe42 cpu typesDoug Gilbert2016-08-157-111/+144
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* 64 bit load/store peepholesDoug Gilbert2016-08-153-13/+188
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* 64 bit load/storeDoug Gilbert2016-08-153-19/+43
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* Compare-branch fused instructionsDoug Gilbert2016-08-154-31/+204
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* hack1Doug Gilbert2016-08-154-890/+900
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* [gcc]wschmidt2014-10-133-5/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2014-10-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Backport from mainline r215880 2014-10-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Issue a warning message when vec_lvsl or vec_lvsr is used with a little endian target. Backport from mainline r215882 2014-10-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * altivec.md (altivec_lvsl): New define_expand. (altivec_lvsl_direct): Rename define_insn from altivec_lvsl. (altivec_lvsr): New define_expand. (altivec_lvsr_direct): Rename define_insn from altivec_lvsr. * rs6000.c (rs6000_expand_builtin): Change to use altivec_lvs[lr]_direct; remove commented-out code. [gcc/testsuite] 2014-10-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Backport from mainline r215880 2014-10-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * g++.dg/ext/altivec-2.C: Compile with -Wno-deprecated to avoid failing with the new warning message. * gcc.dg/vmx/3c-01a.c: Likewise. * gcc.dg/vmx/ops-long-1.c: Likewise. * gcc.dg/vmx/ops.c: Likewise. * gcc.target/powerpc/altivec-20.c: Likewise. * gcc.target/powerpc/altivec-6.c: Likewise. * gcc.target/powerpc/altivec-vec-merge.c: Likewise. * gcc.target/powerpc/vsx-builtin-8.c: Likewise. * gcc.target/powerpc/warn-lvsl-lvsr.c: New test. Backport from mainline r215882 2014-10-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/lvsl-lvsr.c: New test. Backport from mainline r216017 2014-10-08 Pat Haugen <pthaugen@us.ibm.com> * gcc.dg/vmx/3c-01a.c: Add default options from vmx.exp. * gcc.dg/vmx/ops.c: Likewise. * gcc.dg/vmx/ops-long-1.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@216134 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]wschmidt2014-09-251-1/+2
| | | | | | | | | | | | | | | | | | | 2014-09-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com> PR target/63335 * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Exclude VSX_BUILTIN_XVCMPGEDP_P from special handling. [gcc/testsuite] 2014-09-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com> PR target/63335 * gcc.target/powerpc/pr63335.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@215603 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-09-23 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-09-231-10/+27
| | | | | | | | | | | | | | | | | | | | | | | * config/rs6000/rs6000.md (f32_vsx): New mode attributes to refine the constraints used on 32/64-bit floating point moves. (f32_av): Likewise. (f64_vsx): Likewise. (f64_dm): Likewise. (f64_av): Likewise. (BOOL_REGS_OUTPUT): Use wt constraint for TImode instead of wa. (BOOL_REGS_OP1): Likewise. (BOOL_REGS_OP2): Likewise. (BOOL_REGS_UNARY): Likewise. (mov<mode>_hardfloat, SFmode/SDmode): Tighten down constraints for 32/64-bit floating point moves. Do not use wa, instead use ww/ws for moves involving VSX registers. Do not use constraints that target VSX registers for decimal types. (mov<mode>_hardfloat32, DFmode/DDmode): Likewise. (mov<mode>_hardfloat64, DFmode/DDmode): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@215522 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-09-19 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-09-194-109/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Back port from trunk: 2014-09-19 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/predicates.md (fusion_gpr_mem_load): Move testing for base_reg_operand to be common between LO_SUM and PLUS. (fusion_gpr_mem_combo): New predicate to match a fused address that combines the addis and memory offset address. * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Change calling signature. (emit_fusion_gpr_load): Likewise. * config/rs6000/rs6000.c (fusion_gpr_load_p): Change calling signature to pass each argument separately, rather than using an operands array. Rewrite the insns found by peephole2 to be a single insn, rather than hoping the insns will still be together when the peephole pass is done. Drop being called via a normal peephole. (emit_fusion_gpr_load): Change calling signature to be called from the fusion_gpr_load_<mode> insns with a combined memory address instead of the peephole pass passing the addis and offset separately. * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): New unspec for GPR fusion. (power8 fusion peephole): Drop support for doing power8 via a normal peephole that was created by the peephole2 pass. (power8 fusion peephole2): Create a new insn with the fused address, so that the fused operation is kept together after register allocation is done. (fusion_gpr_load_<mode>): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@215405 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-09-101-11/+11
| | | | | | | | | | | | | | | Backport from mainline 2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/vsx.md (vsx_fmav4sf4): Use correct constraints for V2DF, V4SF, DF, and DI modes. (vsx_fmav2df2): Likewise. (vsx_float_fix_<mode>2): Likewise. (vsx_reduc_<VEC_reduc_name>_v2df_scalar): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@215139 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-09-09 Bill Schmidt <wschmidt@us.ibm.com>wschmidt2014-09-091-1/+1
| | | | | | | | | | | | | | | | | | | | Backported from mainline 2014-09-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/vsx.md (*vsx_extract_<mode>_load): Always match selection of 0th memory doubleword, regardless of endianness. 2014-09-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Backported from mainline 2014-09-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/vsx-extract-1.c: Test 0th doubleword regardless of endianness. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@215096 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-08-223-8/+6
| | | | | | | | | | | | | | | | | | | | Backport fro mainline 2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/62195 * doc/md.texi (Machine Constraints): Update PowerPC wi constraint documentation to state it is only for VSX operations. * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Make wi constraint only active if VSX. * config/rs6000/rs6000.md (lfiwax): Use wj constraint instead of wi cosntraint for ISA 2.07 lxsiwax/lxsiwzx instructions. (lfiwzx): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@214336 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-08-12 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-08-125-197/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backport patch from mainline 2014-08-11 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/constraints.md (wh constraint): New constraint, for FP registers if direct move is available. (wi constraint): New constraint, for VSX/FP registers that can handle 64-bit integers. (wj constraint): New constraint for VSX/FP registers that can handle 64-bit integers for direct moves. (wk constraint): New constraint for VSX/FP registers that can handle 64-bit doubles for direct moves. (wy constraint): Make documentation match implementation. * config/rs6000/rs6000.c (struct rs6000_reg_addr): Add scalar_in_vmx_p field to simplify tests of whether SFmode or DFmode can go in the Altivec registers. (rs6000_hard_regno_mode_ok): Use scalar_in_vmx_p field. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_debug_print_mode): Add debug support for scalar_in_vmx_p field, and wh/wi/wj/wk constraints. (rs6000_init_hard_regno_mode_ok): Setup scalar_in_vmx_p field, and the wh/wi/wj/wk constraints. (rs6000_preferred_reload_class): If SFmode/DFmode can go in the upper registers, prefer VSX registers unless the operation is a memory operation with REG+OFFSET addressing. * config/rs6000/vsx.md (VSr mode attribute): Add support for DImode. Change SFmode to use ww constraint instead of d to allow SF registers in the upper registers. (VSr2): Likewise. (VSr3): Likewise. (VSr5): Fix thinko in comment. (VSa): New mode attribute that is an alternative to wa, that returns the VSX register class that a mode can go in, but may not be the preferred register class. (VS_64dm): New mode attribute for appropriate register classes for referencing 64-bit elements of vectors for direct moves and normal moves. (VS_64reg): Likewise. (vsx_mov<mode>): Change wa constraint to <VSa> to limit the register allocator to only registers the data type can handle. (vsx_le_perm_load_<mode>): Likewise. (vsx_le_perm_store_<mode>): Likewise. (vsx_xxpermdi2_le_<mode>): Likewise. (vsx_xxpermdi4_le_<mode>): Likewise. (vsx_lxvd2x2_le_<mode>): Likewise. (vsx_lxvd2x4_le_<mode>): Likewise. (vsx_stxvd2x2_le_<mode>): Likewise. (vsx_add<mode>3): Likewise. (vsx_sub<mode>3): Likewise. (vsx_mul<mode>3): Likewise. (vsx_div<mode>3): Likewise. (vsx_tdiv<mode>3_internal): Likewise. (vsx_fre<mode>2): Likewise. (vsx_neg<mode>2): Likewise. (vsx_abs<mode>2): Likewise. (vsx_nabs<mode>2): Likewise. (vsx_smax<mode>3): Likewise. (vsx_smin<mode>3): Likewise. (vsx_sqrt<mode>2): Likewise. (vsx_rsqrte<mode>2): Likewise. (vsx_tsqrt<mode>2_internal): Likewise. (vsx_fms<mode>4): Likewise. (vsx_nfma<mode>4): Likewise. (vsx_eq<mode>): Likewise. (vsx_gt<mode>): Likewise. (vsx_ge<mode>): Likewise. (vsx_eq<mode>_p): Likewise. (vsx_gt<mode>_p): Likewise. (vsx_ge<mode>_p): Likewise. (vsx_xxsel<mode>): Likewise. (vsx_xxsel<mode>_uns): Likewise. (vsx_copysign<mode>3): Likewise. (vsx_float<VSi><mode>2): Likewise. (vsx_floatuns<VSi><mode>2): Likewise. (vsx_fix_trunc<mode><VSi>2): Likewise. (vsx_fixuns_trunc<mode><VSi>2): Likewise. (vsx_x<VSv>r<VSs>i): Likewise. (vsx_x<VSv>r<VSs>ic): Likewise. (vsx_btrunc<mode>2): Likewise. (vsx_b2trunc<mode>2): Likewise. (vsx_floor<mode>2): Likewise. (vsx_ceil<mode>2): Likewise. (vsx_<VS_spdp_insn>): Likewise. (vsx_xscvspdp): Likewise. (vsx_xvcvspuxds): Likewise. (vsx_float_fix_<mode>2): Likewise. (vsx_set_<mode>): Likewise. (vsx_extract_<mode>_internal1): Likewise. (vsx_extract_<mode>_internal2): Likewise. (vsx_extract_<mode>_load): Likewise. (vsx_extract_<mode>_store): Likewise. (vsx_splat_<mode>): Likewise. (vsx_xxspltw_<mode>): Likewise. (vsx_xxspltw_<mode>_direct): Likewise. (vsx_xxmrghw_<mode>): Likewise. (vsx_xxmrglw_<mode>): Likewise. (vsx_xxsldwi_<mode>): Likewise. (vsx_xscvdpspn): Tighten constraints to only use register classes the types use. (vsx_xscvspdpn): Likewise. (vsx_xscvdpspn_scalar): Likewise. * config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wh, wi, wj, and wk constraints. (GPR_REG_CLASS_P): New helper macro for register classes targeting general purpose registers. * config/rs6000/rs6000.md (f32_dm): Use wh constraint for SDmode direct moves. (zero_extendsidi2_lfiwz): Use wj constraint for direct move of DImode instead of wm. Use wk constraint for direct move of DFmode instead of wm. (extendsidi2_lfiwax): Likewise. (lfiwax): Likewise. (lfiwzx): Likewise. (movdi_internal64): Likewise. * doc/md.texi (PowerPC and IBM RS6000): Document wh, wi, wj, and wk constraints. Make the wy constraint documentation match them implementation. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@213871 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/rs6000/rs6000.md (*movdi_internal64): Add a new constraint.carrot2014-08-091-5/+7
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@213769 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/60102edmarwjr2014-08-043-55/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [libgcc] 2014-08-04 Rohit <rohitarulraj@freescale.com> * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update based on change in SPE high register numbers and 3 HTM registers. [gcc] 2014-08-04 Rohit <rohitarulraj@freescale.com> * config/rs6000/rs6000.c (rs6000_reg_names) : Add SPE high register names. (alt_reg_names) : Likewise. (rs6000_dwarf_register_span) : For SPE high registers, replace dwarf register numbers with GCC hard register numbers. (rs6000_init_dwarf_reg_sizes_extra) : Likewise. (rs6000_dbx_register_number): For SPE high registers, return dwarf register number for the corresponding GCC hard register number. * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard register numbers for SPE high registers. (DWARF_FRAME_REGISTERS) : Likewise. (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. (DWARF_FRAME_REGNUM) : Likewise. (FIXED_REGISTERS) : Likewise. (CALL_USED_REGISTERS) : Likewise. (CALL_REALLY_USED_REGISTERS) : Likewise. (REG_ALLOC_ORDER) : Likewise. (enum reg_class) : Likewise. (REG_CLASS_NAMES) : Likewise. (REG_CLASS_CONTENTS) : Likewise. (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. [gcc/testsuite] 2014-08-04 Rohit <rohitarulraj@freescale.com> * gcc.target/powerpc/pr60102.c: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@213597 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/uweigand2014-07-245-3/+32
| | | | | | | | | | | | | | | | | | | | | | | | * config/rs6000/rs6000-protos.h (rs6000_special_adjust_field_align_p): Add prototype. * config/rs6000/rs6000.c (rs6000_special_adjust_field_align_p): New function. Issue -Wpsabi warning if future GCC releases will use different field alignment rules for this type. * config/rs6000/sysv4.h (ADJUST_FIELD_ALIGN): Call it. * config/rs6000/linux64.h (ADJUST_FIELD_ALIGN): Likewise. * config/rs6000/freebsd64.h (ADJUST_FIELD_ALIGN): Likewise. gcc/testsuite/ * gcc.target/powerpc/ppc64-abi-warn-3.c: New test. * gcc.c-torture/execute/20050316-1.x: Add -Wno-psabi. * gcc.c-torture/execute/20050604-1.x: Add -Wno-psabi. * gcc.c-torture/execute/20050316-3.x: New file. Add -Wno-psabi. * gcc.c-torture/execute/pr23135.x: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@213021 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/uweigand2014-07-241-7/+44
| | | | | | | | | | | | | | * config/rs6000/rs6000.c (rs6000_function_arg_boundary): Issue -Wpsabi note when encountering a type where future GCC releases will apply different alignment requirements. gcc/testsuite/ * gcc.target/powerpc/ppc64-abi-warn-2.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@213020 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/uweigand2014-07-241-0/+32
| | | | | | | | | | | | | | | * config/rs6000/rs6000.c (rs6000_function_arg): If a float argument does not fit fully into floating-point registers, and there is still space in the register parameter area, issue -Wpsabi note that the ABI will change in a future GCC release. gcc/testsuite/ * gcc.target/powerpc/ppc64-abi-warn-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@213019 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/rs6000/sysv4.h (LIBASAN_EARLY_SPEC): Define.bergner2014-07-211-0/+16
| | | | | | | (LIBTSAN_EARLY_SPEC): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@212898 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-06-26 Bill Schmidt <wschmidt@linux.vnet.ibm.com>wschmidt2014-06-261-1/+1
| | | | | | | | | | PR target/61542 * config/rs6000/vsx.md (vsx_extract_v4sf): Fix bug with element extraction other than index 3. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@212048 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/bergner2014-06-134-40/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backport from mainline 2014-06-13 Peter Bergner <bergner@vnet.ibm.com> PR target/61415 * config/rs6000/rs6000-builtin.def (BU_MISC_1): Delete. (BU_MISC_2): Rename to ... (BU_LDBL128_2): ... this. * config/rs6000/rs6000.h (RS6000_BTM_LDBL128): New define. (RS6000_BTM_COMMON): Add RS6000_BTM_LDBL128. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle RS6000_BTM_LDBL128. (rs6000_invalid_builtin): Add long double 128-bit builtin support. (rs6000_builtin_mask_names): Add RS6000_BTM_LDBL128. * config/rs6000/rs6000.md (unpacktf_0): Remove define)expand. (unpacktf_1): Likewise. * doc/extend.texi (__builtin_longdouble_dw0): Remove documentation. (__builtin_longdouble_dw1): Likewise. * doc/sourcebuild.texi (longdouble128): Document. gcc/testsuite/ Backport from mainline 2014-06-13 Peter Bergner <bergner@vnet.ibm.com> PR target/61415 * lib/target-supports.exp (check_effective_target_longdouble128): New. * gcc.target/powerpc/pack02.c: Use it. * gcc.target/powerpc/tfmode_off.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@211656 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/61300amodra2014-06-113-16/+53
| | | | | | | | | | | | | | | | | | * doc/tm.texi.in (INCOMING_REG_PARM_STACK_SPACE): Document. * doc/tm.texi: Regenerate. * function.c (INCOMING_REG_PARM_STACK_SPACE): Provide default. Use throughout in place of REG_PARM_STACK_SPACE. * config/rs6000/rs6000.c (rs6000_reg_parm_stack_space): Add "incoming" param. Pass to rs6000_function_parms_need_stack. (rs6000_function_parms_need_stack): Add "incoming" param, ignore prototype_p when incoming. Use function decl when incoming to handle K&R style functions. * config/rs6000/rs6000.h (REG_PARM_STACK_SPACE): Adjust. (INCOMING_REG_PARM_STACK_SPACE): Define. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@211482 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2014-06-061-17/+24
| | | | | | | | | | | | | | | | | | | | | | | Back port from trunk 2014-06-06 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/61431 * config/rs6000/vsx.md (VSX_LE): Split VSX_D into 2 separate iterators, VSX_D that handles 64-bit types, and VSX_LE that handles swapping the two 64-bit double words on little endian systems. Include V1TImode and optionally TImode in VSX_LE so that these types are properly swapped. Change all of the insns and splits that do the 64-bit swaps to use VSX_LE. (vsx_le_perm_load_<mode>): Likewise. (vsx_le_perm_store_<mode>): Likewise. (splitters for little endian memory operations): Likewise. (vsx_xxpermdi2_le_<mode>): Likewise. (vsx_lxvd2x2_le_<mode>): Likewise. (vsx_stxvd2x2_le_<mode>): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@211331 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/61231amodra2014-05-232-3/+4
| | | | | | | | | | * config/rs6000/rs6000.c (mem_operand_gpr): Handle SImode. * config/rs6000/rs6000.md (extendsidi2_lfiwax, extendsidi2_nocell): Use "Y" constraint rather than "m". git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@210836 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/bergner2014-05-221-1/+1
| | | | | | | | | | * config/rs6000/htm.md (ttest): Use correct shift value to get CR0. gcc/testsuite/ * gcc.target/powerpc/htm-ttest.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@210817 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/61193bergner2014-05-161-2/+7
| | | | | | | | | * config/rs6000/htmxlintrin.h (_HTM_TBEGIN_STARTED): New define. (__TM_simple_begin): Use it. (__TM_begin): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@210487 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/bergner2014-05-053-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | * config/rs6000/rs6000.h (RS6000_BTM_HARD_FLOAT): New define. (RS6000_BTM_COMMON): Add RS6000_BTM_HARD_FLOAT. (TARGET_EXTRA_BUILTINS): Add TARGET_HARD_FLOAT. * config/rs6000/rs6000-builtin.def (BU_MISC_1): Use RS6000_BTM_HARD_FLOAT. (BU_MISC_2): Likewise. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle RS6000_BTM_HARD_FLOAT. (rs6000_option_override_internal): Enforce -mhard-float if -mhard-dfp is explicitly used. (rs6000_invalid_builtin): Add hard floating builtin support. (rs6000_expand_builtin): Relax the gcc_assert to allow the new hard float builtins. (rs6000_builtin_mask_names): Add RS6000_BTM_HARD_FLOAT. gcc/testsuite/ * gcc.target/powerpc/pack02.c (dg-options): Add -mhard-float. (dg-require-effective-target): Change target to powerpc_fprs. * gcc.target/powerpc/pack03.c (dg-options): Add -mhard-dfp. (dg-require-effective-target): Change target to dfprt. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@210055 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2014-04-307-15/+606
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com> Back port from mainline 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com> * doc/extend.texi (PowerPC Built-in Functions): Document new powerpc extended divide, bcd, pack/unpack 128-bit, builtin functions. (PowerPC AltiVec/VSX Built-in Functions): Likewise. * config/rs6000/predicates.md (const_0_to_3_operand): New predicate to match 0..3 integer constants. * config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros to support adding miscellaneous builtin functions. (BU_DFP_MISC_2): Likewise. (BU_P7_MISC_1): Likewise. (BU_P7_MISC_2): Likewise. (BU_P8V_MISC_3): Likewise. (BU_MISC_1): Likewise. (BU_MISC_2): Likewise. (DIVWE): Add extended divide builtin functions. (DIVWEO): Likewise. (DIVWEU): Likewise. (DIVWEUO): Likewise. (DIVDE): Likewise. (DIVDEO): Likewise. (DIVDEU): Likewise. (DIVDEUO): Likewise. (DXEX): Add decimal floating-point builtin functions. (DXEXQ): Likewise. (DDEDPD): Likewise. (DDEDPDQ): Likewise. (DENBCD): Likewise. (DENBCDQ): Likewise. (DIEX): Likewise. (DIEXQ): Likewise. (DSCLI): Likewise. (DSCLIQ): Likewise. (DSCRI): Likewise. (DSCRIQ): Likewise. (CDTBCD): Add new BCD builtin functions. (CBCDTD): Likewise. (ADDG6S): Likewise. (BCDADD): Likewise. (BCDADD_LT): Likewise. (BCDADD_EQ): Likewise. (BCDADD_GT): Likewise. (BCDADD_OV): Likewise. (BCDSUB): Likewise. (BCDSUB_LT): Likewise. (BCDSUB_EQ): Likewise. (BCDSUB_GT): Likewise. (BCDSUB_OV): Likewise. (PACK_TD): Add new pack/unpack 128-bit type builtin functions. (UNPACK_TD): Likewise. (PACK_TF): Likewise. (UNPACK_TF): Likewise. (UNPACK_TF_0): Likewise. (UNPACK_TF_1): Likewise. (PACK_V1TI): Likewise. (UNPACK_V1TI): Likewise. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add support for decimal floating point builtin functions. (rs6000_expand_ternop_builtin): Add checks for the new builtin functions that take constant arguments. (rs6000_invalid_builtin): Add decimal floating point builtin support. (rs6000_init_builtins): Setup long double, _Decimal64, and _Decimal128 types for new builtin functions. (builtin_function_type): Set the unsigned flags appropriately for the new builtin functions. (rs6000_opt_masks): Add support for decimal floating point builtin functions. * config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal floating point builtin functions. (RS6000_BTM_COMMON): Likewise. (RS6000_BTI_long_double): Likewise. (RS6000_BTI_dfloat64): Likewise. (RS6000_BTI_dfloat128): Likewise. (long_double_type_internal_node): Likewise. (dfloat64_type_internal_node): Likewise. (dfloat128_type_internal_node): Likewise. * config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA 2.07 bcd arithmetic instructions. (UNSPEC_BCDSUB): Likewise. (UNSPEC_BCD_OVERFLOW): Likewise. (UNSPEC_BCD_ADD_SUB): Likewise. (bcd_add_sub): Likewise. (BCD_TEST): Likewise. (bcd<bcd_add_sub>): Likewise. (bcd<bcd_add_sub>_test): Likewise. (bcd<bcd_add_sub>_test2): Likewise. (bcd<bcd_add_sub>_<code>): Likewise. (peephole2 for combined bcd ops): Likewise. * config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new decimal floating point builtin functions. (UNSPEC_DENBCD): Likewise. (UNSPEC_DXEX): Likewise. (UNSPEC_DIEX): Likewise. (UNSPEC_DSCLI): Likewise. (UNSPEC_DSCRI): Likewise. (D64_D128): Likewise. (dfp_suffix): Likewise. (dfp_ddedpd_<mode>): Likewise. (dfp_denbcd_<mode>): Likewise. (dfp_dxex_<mode>): Likewise. (dfp_diex_<mode>): Likewise. (dfp_dscli_<mode>): Likewise. (dfp_dscri_<mode>): Likewise. * config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD builtin functions. (UNSPEC_CDTBCD): Likewise. (UNSPEC_CBCDTD): Likewise. (UNSPEC_DIVE): Add support for new extended divide builtin functions. (UNSPEC_DIVEO): Likewise. (UNSPEC_DIVEU): Likewise. (UNSPEC_DIVEUO): Likewise. (UNSPEC_UNPACK_128BIT): Add support for new builtin functions to pack/unpack 128-bit types. (UNSPEC_PACK_128BIT): Likewise. (idiv_ldiv): New mode attribute to set the 32/64-bit divide type. (udiv<mode>3): Use idiv_ldiv mode attribute. (div<mode>3): Likewise. (addg6s): Add new BCD builtin functions. (cdtbcd): Likewise. (cbcdtd): Likewise. (UNSPEC_DIV_EXTEND): Add support for new extended divide instructions. (div_extend): Likewise. (div<div_extend>_<mode>"): Likewise. (FP128_64): Add support for new builtin functions to pack/unpack 128-bit types. (unpack<mode>): Likewise. (unpacktf_0): Likewise. (unpacktf_1): Likewise. (unpack<mode>_dm): Likewise. (unpack<mode>_nodm): Likewise. (pack<mode>): Likewise. (unpackv1ti): Likewise. (packv1ti): Likewise. [gcc/testsuite] 2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com> Back port from mainline 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/pack01.c: New test to test the new pack and unpack builtin functionss for 128-bit types. * gcc.target/powerpc/pack02.c: Likewise. * gcc.target/powerpc/pack03.c: Likewise. * gcc.target/powerpc/extend-divide-1.c: New test to test extended divide builtin functionss. * gcc.target/powerpc/extend-divide-2.c: Likewise. * gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin functions. * gcc.target/powerpc/bcd-2.c: Likewise. * gcc.target/powerpc/bcd-3.c: Likewise. * gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP builtin functionss. * gcc.target/powerpc/dfp-builtin-2.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209954 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/rs6000/rs6000.md (addti3, subti3): New.pthaugen2014-04-291-0/+43
| | | | | | | | | * gcc.target/powerpc/ti_math1.c: New. * gcc.target/powerpc/ti_math2.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209912 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/rs6000/sync.md (AINT mode_iterator): Move definition.pthaugen2014-04-283-17/+93
| | | | | | | | | | | (loadsync_<mode>): Change mode. (load_quadpti, store_quadpti): New. (atomic_load<mode>, atomic_store<mode>): Add support for TI mode. * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209876 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]meissner2014-04-222-1/+20
| | | | | | | | | | | | | | | | | | | | | | 2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60735 * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64 case): If mode is DDmode and TARGET_E500_DOUBLE allow move. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print some more debug information for E500 if -mdebug=reg. [gcc/testsuite] 2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60735 * gcc.target/powerpc/pr60735.c: New test. Insure _Decimal64 does not cause errors if -mspe. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209664 138bc75d-0d04-0410-961f-82ee72b054a4
* [gcc]wschmidt2014-04-221-2/+12
| | | | | | | | | | | | | | | | | | | 2014-04-22 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/vsx.md (vsx_xxmrghw_<mode>): Adjust for little-endian. (vsx_xxmrglw_<mode>): Likewise. [gcc/testsuite] 2014-04-22 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.dg/vmx/merge-vsx.c: Add V4SI and V4SF tests. * gcc.dg/vmx/merge-vsx-be-order.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209638 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-04-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>wschmidt2014-04-152-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | PR target/60839 Revert the following patch 2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60735 * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have software floating point or no floating point registers, do not allow any type in the FPRs. Eliminate a test for SPE SIMD types in GPRs that occurs after we tested for GPRs that would never be true. * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64): Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE, since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE, specifically allow DDmode, since that does not use the SPE SIMD instructions. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209426 138bc75d-0d04-0410-961f-82ee72b054a4
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