diff options
92 files changed, 84 insertions, 28451 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 363ea14cfb4..1aa0a321312 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,10 +1,57 @@ +2003-05-15 Zack Weinberg <zack@codesourcery.com> + + * config.gcc: Purge all targets obsoleted in GCC 3.3. Also + remove hppa*-*-mpeix* which could not be built, and prune + files from tmake_file= or tm_file= lists that don't exist. + + * config/alpha/alpha-interix.h, config/alpha/alpha32.h + * config/alpha/t-interix, config/arm/conix-elf.h + * config/arm/t-arm-aout, config/arm/t-strongarm-coff + * config/arm/unknown-elf-oabi.h, config/i386/win32.h + * config/m68k/3b1.h, config/m68k/3b1g.h, config/m68k/amix.h + * config/m68k/atari.h, config/m68k/ccur-GAS.h, config/m68k/crds.h + * config/m68k/hp2bsd.h, config/m68k/hp3bsd.h + * config/m68k/hp3bsd44.h, config/m68k/linux-aout.h + * config/m68k/m68k-psos.h, config/m68k/mot3300.h + * config/m68k/pbb.h, config/m68k/plexus.h, config/m68k/sun2.h + * config/m68k/sun2o4.h, config/m68k/sun3.h, config/m68k/sun3mach.h + * config/m68k/sun3n.h, config/m68k/sun3n3.h, config/m68k/sun3o3.h + * config/m68k/t-mot3300, config/m68k/t-mot3300-gald + * config/m68k/t-mot3300-gas, config/m68k/t-mot3300-gld + * config/m68k/tower-as.h, config/m68k/tower.h + * config/m88k/aout-dbx.h, config/m88k/m88k-aout.h + * config/m88k/m88k-modes.def, config/m88k/m88k-move.sh + * config/m88k/m88k-protos.h, config/m88k/m88k.c + * config/m88k/m88k.h, config/m88k/m88k.md, config/m88k/openbsd.h + * config/m88k/sysv4.h, config/m88k/t-luna, config/m88k/t-luna-gas + * config/m88k/t-m88k, config/m88k/t-sysv4, config/mcore/gfloat.h + * config/mips/rtems64.h, config/mips/sni-gas.h + * config/mips/sni-svr4.h, config/mips/t-ecoff + * config/mn10200/lib1funcs.asm, config/mn10200/mn10200-protos.h + * config/mn10200/mn10200.c, config/mn10200/mn10200.h + * config/mn10200/mn10200.md, config/mn10200/t-mn10200 + * config/pa/pa-hiux.h, config/pa/pa-hpux7.h, config/pa/pa-hpux9.h + * config/pa/pa-oldas.h, config/pa/t-mpeix, config/psos.h + * config/romp/romp-protos.h, config/romp/romp.c + * config/romp/romp.h, config/romp/romp.md, config/rs6000/aix31.h + * config/rs6000/aix3newas.h, config/rs6000/mach.h + * config/sparc/bsd.h, config/sparc/hal.h + * config/sparc/linux-aout.h, config/sparc/lynx-ng.h + * config/sparc/lynx.h, config/sparc/netbsd.h + * config/sparc/sp86x-aout.h, config/sparc/splet.h + * config/sparc/sun4gas.h, config/sparc/sun4o3.h + * config/sparc/sunos4.h, config/sparc/t-chorus-elf + * config/sparc/t-halos, config/sparc/t-sparcbare + * config/sparc/t-splet, config/sparc/t-sunos41 + * config/v850/rtems.h: Delete file. + 2003-05-15 Aldy Hernandez <aldyh@redhat.com> - * config/rs6000/rs6000-protos.h (function_value): Protoize. + * config/rs6000/rs6000-protos.h (function_value): Protoize. - * config/rs6000/rs6000.h (FUNCTION_VALUE): Call function. + * config/rs6000/rs6000.h (FUNCTION_VALUE): Call function. - * config/rs6000/rs6000.c (rs6000_function_value): New. + * config/rs6000/rs6000.c (rs6000_function_value): New. 2003-05-15 Philip Blundell <philb@gnu.org> diff --git a/gcc/config.gcc b/gcc/config.gcc index b168c7cfd52..b1c55edcb11 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -226,62 +226,7 @@ need_64bit_hwint= # Obsolete configurations. case $machine in - m88k-*-* \ - | mn10200-*-* \ - | romp-*-* \ - | alpha*-*-interix* \ - | alpha*-*-linux*libc1* \ - | alpha*-*-linux*ecoff* \ - | arm*-*-aout* \ - | arm*-*-conix* \ - | arm*-*-oabi \ - | strongarm-*-coff* \ - | hppa1.0-*-osf* \ - | hppa1.0-*-bsd* \ - | hppa1.[01]-*-hpux[789]* \ - | hppa*-*-hiux* \ - | hppa*-*-lites* \ - | i?86-*-win32 \ - | m68000-hp-bsd* \ - | m68000-sun-sunos* \ - | m68000-att-sysv* \ - | m68k-atari-sysv* \ - | m68k-motorola-sysv* \ - | m68k-ncr-sysv* \ - | m68k-plexus-sysv* \ - | m68k-tti-* \ - | m68k-crds-unos* \ - | m68k-cbm-sysv* \ - | m68k-ccur-rtu* \ - | m68k-hp-bsd* \ - | m68k-sun-mach* \ - | m68k-sun-sunos* \ - | m68k-*-linux*aout* \ - | m68k-*-linux*libc1* \ - | m68k-*-psos* \ - | mips*-*-ecoff* \ - | mips-sni-sysv4 \ - | mips64orion-*-rtems* \ - | ns32k-*-openbsd* \ - | powerpc*-*-sysv* \ - | powerpc*-*-linux*libc1* \ - | rs6000-ibm-aix[123]* \ - | rs6000-bull-bosx \ - | rs6000-*-mach* \ - | sparc-*-aout* \ - | sparc-*-netbsd*aout* \ - | sparc-*-bsd* \ - | sparc-*-chorusos* \ - | sparc-*-linux*aout* \ - | sparc-*-linux*libc1* \ - | sparc-*-lynxos* \ - | sparc-hal-solaris2* \ - | sparc-*-sunos[34]* \ - | sparclet-*-aout* \ - | sparclite-*-aout* \ - | sparc86x-*-aout* \ - | v850-*-rtems* \ - ) + dummy) if test "x$enable_obsolete" != xyes; then echo "*** Configuration $machine is obsolete." >&2 echo "*** Specify --enable-obsolete to build it anyway." >&2 @@ -291,6 +236,32 @@ case $machine in fi;; esac +# Unsupported targets list. Do not put an entry in this list unless +# it would otherwise be caught by a more permissive pattern. The list +# should be in alphabetical order. +case $machine in + alpha*-*-linux*libc1* \ + | i[34567]86-sequent-sysv* \ + | i[34567]86-go32-* \ + | i[34567]86-*-go32* \ + | m68k-*-linux*aout* \ + | m68k-*-linux*libc1* \ + | mips64orion*-*-rtems* \ + | powerpc-*-linux*libc1* \ + | sparc-*-linux*aout* \ + | sparc-*-linux*libc1* \ + | sparc-hal-solaris2* \ + | thumb-*-* \ + | *-*-linux*coff* \ + | *-*-linux*oldld* \ + | *-*-rtemsaout* \ + | *-*-rtemscoff* \ + ) + echo "*** Configuration $machine not supported" 1>&2 + exit 1 + ;; +esac + # Set default cpu_type, tm_file, tm_p_file and xm_file so it can be # updated in each machine entry. Also set default extra_headers for some # machines. @@ -396,7 +367,7 @@ esac case $machine in *-*-linux*) case $machine in - *-*-linux*ecoff* | *-*-linux*libc1* | *-*-linux*oldld* | *-*-linux*aout*) + *-*-linux*libc1* | *-*-linux*aout*) ;; *) extra_parts="crtbegin.o crtbeginS.o crtbeginT.o crtend.o crtendS.o" @@ -566,39 +537,6 @@ alpha*-*-unicosmk*) # tmake_file="alpha/t-ieee" tmake_file="alpha/t-unicosmk" ;; -alpha-*-interix) - tm_file="${tm_file} alpha/alpha32.h interix.h alpha/alpha-interix.h" - - # GAS + IEEE_CONFORMANT+IEEE (no inexact); - #target_cpu_default="MASK_GAS|MASK_IEEE_CONFORMANT|MASK_IEEE" - - # GAS + IEEE_CONFORMANT - target_cpu_default="MASK_GAS|MASK_IEEE_CONFORMANT" - - tmake_file="alpha/t-alpha t-interix alpha/t-interix alpha/t-ieee" - if test x$enable_threads = xyes ; then - thread_file='posix' - fi - if test x$stabs = xyes ; then - tm_file="${tm_file} dbxcoff.h" - fi - #prefix='$$INTERIX_ROOT'/usr/contrib - #local_prefix='$$INTERIX_ROOT'/usr/contrib - ;; -alpha*-*-linux*ecoff*) - echo "Configuration $machine no longer supported" 1>&2 - exit 1 - ;; -alpha*-*-linux*libc1*) - tm_file="${tm_file} alpha/elf.h alpha/linux.h alpha/linux-elf.h" - target_cpu_default="MASK_GAS" - tmake_file="t-slibgcc-elf-ver t-linux t-linux-gnulibc1 alpha/t-alpha alpha/t-crtfm alpha/t-ieee" - extra_parts="crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o" - gas=yes gnu_ld=yes - if test x$enable_threads = xyes; then - thread_file='posix' - fi - ;; alpha*-*-linux*) tm_file="${tm_file} alpha/elf.h alpha/linux.h alpha/linux-elf.h" target_cpu_default="MASK_GAS" @@ -699,10 +637,6 @@ arm-*-coff* | armel-*-coff*) tm_file="arm/semi.h arm/aout.h arm/arm.h arm/coff.h" tmake_file=arm/t-arm-coff ;; -arm-semi-aout | armel-semi-aout) - tm_file="arm/semi.h arm/aout.h arm/arm.h" - tmake_file=arm/t-semi - ;; arm-semi-aof | armel-semi-aof) tm_file="arm/semiaof.h arm/aof.h arm/arm.h" tmake_file=arm/t-semi @@ -736,10 +670,6 @@ arm*-*-uclinux*) # ARM ucLinux tm_file="dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h arm/linux-gas.h arm/linux-elf.h arm/uclinux-elf.h" tmake_file=arm/t-arm-elf ;; -arm*-*-aout) - tm_file="arm/aout.h arm/arm.h" - tmake_file=arm/t-arm-aout - ;; arm*-*-ecos-elf) tm_file="dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h arm/ecos-elf.h" tmake_file=arm/t-arm-elf @@ -755,14 +685,6 @@ arm*-*-elf | ep9312-*-elf) tm_file="dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h" tmake_file=arm/t-arm-elf ;; -arm*-*-conix*) - tm_file="dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/conix-elf.h arm/aout.h arm/arm.h" - tmake_file=arm/t-arm-elf - ;; -arm*-*-oabi) - tm_file="arm/unknown-elf-oabi.h dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h" - tmake_file=arm/t-arm-elf - ;; arm-*-pe*) tm_file="arm/semi.h arm/aout.h arm/arm.h arm/coff.h arm/pe.h" tmake_file=arm/t-pe @@ -865,12 +787,6 @@ hppa1.1-*-rtems*) thread_file='rtems' fi ;; -hppa1.0-*-osf*) - tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-osf.h" - tmake_file="pa/t-bsd pa/t-pa" - xmake_file="pa/x-ada" - use_collect2=yes - ;; hppa1.1-*-bsd*) tm_file="${tm_file} pa/pa32-regs.h pa/som.h" target_cpu_default="MASK_PA_11" @@ -878,52 +794,6 @@ hppa1.1-*-bsd*) xmake_file="pa/x-ada" use_collect2=yes ;; -hppa1.0-*-bsd*) - tm_file="${tm_file} pa/pa32-regs.h pa/som.h" - tmake_file="pa/t-bsd pa/t-pa" - xmake_file="pa/x-ada" - use_collect2=yes - ;; -hppa1.0-*-hpux7*) - tm_file="pa/pa-oldas.h ${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux7.h" - tmake_file=pa/t-pa-hpux - install_headers_dir=install-headers-cpio - use_collect2=yes - ;; -hppa1.0-*-hpux8.0[0-2]*) - tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h" - tmake_file=pa/t-pa-hpux - if test x$gas != xyes - then - tm_file="pa/pa-oldas.h ${tm_file}" - fi - install_headers_dir=install-headers-cpio - use_collect2=yes - ;; -hppa1.1-*-hpux8.0[0-2]*) - target_cpu_default="MASK_PA_11" - tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h" - tmake_file=pa/t-pa-hpux - if test x$gas != xyes - then - tm_file="pa/pa-oldas.h ${tm_file}" - fi - install_headers_dir=install-headers-cpio - use_collect2=yes - ;; -hppa1.1-*-hpux8*) - target_cpu_default="MASK_PA_11" - tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h" - tmake_file=pa/t-pa-hpux - install_headers_dir=install-headers-cpio - use_collect2=yes - ;; -hppa1.0-*-hpux8*) - tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h" - tmake_file=pa/t-pa-hpux - install_headers_dir=install-headers-cpio - use_collect2=yes - ;; hppa1.1-*-hpux10* | hppa2*-*-hpux10*) target_cpu_default="MASK_PA_11" tm_file="${tm_file} pa/pa32-regs.h pa/long_double.h pa/som.h pa/pa-hpux.h pa/pa-hpux10.h" @@ -1013,47 +883,6 @@ hppa1.0-*-hpux11*) install_headers_dir=install-headers-cpio use_collect2=yes ;; -hppa1.1-*-hpux* | hppa2*-*-hpux*) - target_cpu_default="MASK_PA_11" - tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h pa/pa-hpux9.h" - tmake_file=pa/t-pa-hpux - install_headers_dir=install-headers-cpio - use_collect2=yes - ;; -hppa1.0-*-hpux*) - tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h pa/pa-hpux9.h" - tmake_file=pa/t-pa-hpux - install_headers_dir=install-headers-cpio - use_collect2=yes - ;; -hppa1.1-*-hiux* | hppa2*-*-hiux*) - target_cpu_default="MASK_PA_11" - tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h pa/pa-hiux.h" - tmake_file=pa/t-pa-hpux - install_headers_dir=install-headers-cpio - use_collect2=yes - ;; -hppa1.0-*-hiux*) - tm_file="${tm_file} pa/pa32-regs.h pa/som.h pa/pa-hpux.h pa/pa-hiux.h" - tmake_file=pa/t-pa-hpux - install_headers_dir=install-headers-cpio - use_collect2=yes - ;; -hppa*-*-lites*) - tm_file="${tm_file} pa/pa32-regs.h dbxelf.h elfos.h pa/elf.h" - target_cpu_default="MASK_PA_11" - tmake_file="pa/t-bsd pa/t-pa" - xmake_file="pa/x-ada" - use_collect2=yes - ;; -hppa*-*-mpeix*) - tm_file="${tm_file} pa/pa32-regs.h pa/long_double.h pa/som.h pa/pa-mpeix.h" - tmake_file=pa/t-mpeix - echo "You must use gas. Assuming it is already installed." - gas=yes - install_headers_dir=install-headers-tar - use_collect2=yes - ;; i370-*-opened*) # IBM 360/370/390 Architecture xm_defines='FATAL_EXIT_CODE=12' tm_file=i370/oe.h @@ -1083,12 +912,7 @@ i[34567]86-*-elf*) ;; i[34567]86-ncr-sysv4*) # NCR 3000 - ix86 running system V.4 xm_defines="SMALL_ARG_MAX" - if test x$stabs = xyes -a x$gas = xyes - then - tm_file=i386/sysv4gdb.h - else - tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h svr4.h i386/sysv4.h i386/sysv4-cpp.h" - fi + tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h svr4.h i386/sysv4.h i386/sysv4-cpp.h" extra_parts="crtbegin.o crtend.o" tmake_file=i386/t-crtpic ;; @@ -1107,10 +931,6 @@ i[34567]86-sequent-ptx4* | i[34567]86-sequent-sysv4*) extra_parts="crtbegin.o crtend.o" install_headers_dir=install-headers-cpio ;; -i[34567]86-sequent-sysv*) # would otherwise be caught by i?86-*-sysv* - echo "*** Configuration $machine not supported" 1>&2 - exit 1 - ;; i[34567]86-*-aout*) tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h i386/gstabs.h i386/i386-aout.h" ;; @@ -1151,10 +971,6 @@ i[34567]86-*-openbsd*) i[34567]86-*-coff*) tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h dbxcoff.h i386/i386-coff.h" ;; -i[34567]86-*-linux*oldld*) # would otherwise be caught by i?86-*-linux* - echo "*** Configuration $machine not supported" 1>&2 - exit 1 - ;; i[34567]86-*-linux*aout*) # Intel 80386's running GNU/Linux # with a.out format tmake_file="t-linux-aout i386/t-crtstuff" @@ -1185,10 +1001,6 @@ x86_64-*-linux*) ;; i[34567]86-*-gnu*) ;; -i[34567]86-go32-msdos | i[34567]86-*-go32*) - echo "GO32/DJGPP V1.X is no longer supported. Use *-pc-msdosdjgpp for DJGPP V2.X instead." - exit 1 - ;; i[34567]86-pc-msdosdjgpp*) xm_file=i386/xm-djgpp.h tm_file="dbxcoff.h ${tm_file} i386/djgpp.h" @@ -1220,11 +1032,6 @@ i[34567]86-*-mach*) # tmake_file=t-libc-ok use_collect2=yes ;; -i[34567]86-go32-rtems* | i[34567]86-*-rtemscoff*) - # would otherwise be caught by i?86-*-rtems* - echo "*** Configuration $machine not supported" 1>&2 - exit 1 - ;; i[34567]86-*-rtems*) tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h i386/i386elf.h i386/rtemself.h rtems.h" extra_parts="crtbegin.o crtend.o crti.o crtn.o" @@ -1319,16 +1126,6 @@ i386-*-vsta) # Intel 80386's running VSTa kernel xm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h i386/xm-vsta.h" tm_file="${tm_file} i386/vsta.h" ;; -i[34567]86-*-win32) - xm_file=i386/xm-cygwin.h - tmake_file=i386/t-cygwin - tm_file="${tm_file} i386/win32.h" - extra_objs=winnt.o - if test x$enable_threads = xyes; then - thread_file='win32' - fi - exeext=.exe - ;; i[34567]86-*-pe | i[34567]86-*-cygwin*) tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h dbxcoff.h i386/cygming.h i386/cygwin.h" xm_file=i386/xm-cygwin.h @@ -1472,10 +1269,6 @@ m68hc12-*-*|m6812-*-*) out_file="m68hc11/m68hc11.c" tmake_file="m68hc11/t-m68hc11-gas" ;; -m68000-hp-bsd*) # HP 9000/200 running BSD - tm_file=m68k/hp2bsd.h - use_collect2=yes - ;; m68000-hp-hpux*) # HP 9000 series 300 if test x$gas = xyes then @@ -1487,95 +1280,11 @@ m68000-hp-hpux*) # HP 9000 series 300 install_headers_dir=install-headers-cpio use_collect2=yes ;; -m68000-sun-sunos3*) - tm_file=m68k/sun2.h - use_collect2=yes - ;; -m68000-sun-sunos4*) - tm_file=m68k/sun2o4.h - use_collect2=yes - ;; -m68000-att-sysv*) - if test x$gas = xyes - then - tm_file=m68k/3b1g.h - else - tm_file=m68k/3b1.h - fi - use_collect2=yes - ;; -m68k-atari-sysv4*) # Atari variant of V.4. - tm_file=m68k/atari.h - tmake_file=t-svr4 - extra_parts="crtbegin.o crtend.o" - ;; -m68k-apollo-sysv* | m68k-bull-sysv*) - # can otherwise be caught by m68k-*-sysv4* - echo "*** Configuration $machine not supported" 1>&2 - exit 1 - ;; -m68k-motorola-sysv*) - tm_file=m68k/mot3300.h - if test x$gas = xyes - then - if test x$gnu_ld = xyes - then - tmake_file=m68k/t-mot3300-gald - else - tmake_file=m68k/t-mot3300-gas - use_collect2=yes - fi - else - if test x$gnu_ld = xyes - then - tmake_file=m68k/t-mot3300-gld - else - tmake_file=m68k/t-mot3300 - use_collect2=yes - fi - fi - gdb_needs_out_file_path=yes - extra_parts="crt0.o mcrt0.o" - ;; -m68k-ncr-sysv*) # NCR Tower 32 SVR3 - tm_file=m68k/tower-as.h - extra_parts="crtbegin.o crtend.o" - ;; -m68k-plexus-sysv*) - tm_file=m68k/plexus.h - use_collect2=yes - ;; -m68k-tti-*) - tm_file=m68k/pbb.h - ;; -m68k-crds-unos*) - tm_file=m68k/crds.h - use_collect2=yes - ;; -m68k-cbm-sysv4*) # Commodore variant of V.4. - tm_file=m68k/amix.h - tmake_file=t-svr4 - extra_parts="crtbegin.o crtend.o" - ;; -m68k-ccur-rtu) - tm_file=m68k/ccur-GAS.h - use_collect2=yes - ;; -m68k-hp-bsd4.4*) # HP 9000/3xx running 4.4bsd - tm_file=m68k/hp3bsd44.h - use_collect2=yes - ;; -m68k-hp-bsd*) # HP 9000/3xx running Berkeley Unix - tm_file=m68k/hp3bsd.h - use_collect2=yes - ;; m68k-hp-hpux7*) # HP 9000 series 300 running HPUX version 7. if test x$gas = xyes then - xmake_file=m68k/x-hp320g tm_file=m68k/hp320g.h else - xmake_file=m68k/x-hp320 tm_file=m68k/hpux7.h fi install_headers_dir=install-headers-cpio @@ -1584,37 +1293,13 @@ m68k-hp-hpux7*) # HP 9000 series 300 running HPUX version 7. m68k-hp-hpux*) # HP 9000 series 300 if test x$gas = xyes then - xmake_file=m68k/x-hp320g tm_file=m68k/hp320g.h else - xmake_file=m68k/x-hp320 tm_file=m68k/hp320.h fi install_headers_dir=install-headers-cpio use_collect2=yes ;; -m68k-sun-mach*) - tm_file=m68k/sun3mach.h - use_collect2=yes - ;; -m68k-sun-sunos3*) - if test x$with_fp = xno - then - tm_file=m68k/sun3n3.h - else - tm_file=m68k/sun3o3.h - fi - use_collect2=yes - ;; -m68k-sun-sunos*) # For SunOS 4 (the default). - if test x$with_fp = xno - then - tm_file=m68k/sun3n.h - else - tm_file=m68k/sun3.h - fi - use_collect2=yes - ;; m68k-*-aout*) tmake_file=m68k/t-m68kbare tm_file="m68k/m68k-aout.h libgloss.h" @@ -1656,34 +1341,12 @@ m68k-*-sysv4*) # Motorola m68k's running system V.4 tmake_file=t-svr4 extra_parts="crtbegin.o crtend.o" ;; -m68k-*-linux*aout*) # Motorola m68k's running GNU/Linux - # with a.out format - tm_file=m68k/linux-aout.h - tmake_file="t-linux-aout" - gnu_ld=yes - ;; -m68k-*-linux*libc1) # Motorola m68k's running GNU/Linux - # with ELF format using the - # GNU/Linux C library 5 - tm_file=m68k/linux.h - tmake_file="t-slibgcc-elf-ver t-linux t-linux-gnulibc1" - extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" - gnu_ld=yes - ;; m68k-*-linux*) # Motorola m68k's running GNU/Linux # with ELF format using glibc 2 # aka the GNU/Linux C library 6. tm_file=m68k/linux.h tmake_file="t-slibgcc-elf-ver t-linux" ;; -m68k-*-psos*) - tmake_file=m68k/t-m68kbare - tm_file=m68k/m68k-psos.h - ;; -m68k-*-rtemscoff*) # would otherwise be caught by m68k-*-rtems* - echo "*** Configuration $machine not supported" 1>&2 - exit 1 - ;; m68k-*-rtems*) tmake_file="m68k/t-m68kbare t-rtems m68k/t-crtstuff" tm_file="m68k/m68k-none.h m68k/m68kelf.h dbxelf.h elfos.h m68k/m68kemb.h m68k/m68020-elf.h m68k/rtemself.h rtems.h" @@ -1692,18 +1355,6 @@ m68k-*-rtems*) thread_file='rtems' fi ;; -m88k-*-aout*) - tm_file=m88k/m88k-aout.h - ;; -m88k-*-openbsd*) - tmake_file="${tmake_file} m88k/t-luna-gas" - tm_file="m88k/aout-dbx.h aoutos.h m88k/m88k.h openbsd.h ${tm_file}" - ;; -m88k-*-sysv4*) - tm_file="dbxelf.h elfos.h svr4.h m88k/sysv4.h" - extra_parts="crtbegin.o crtend.o" - tmake_file=m88k/t-sysv4 - ;; mcore-*-elf) tm_file="dbxelf.h elfos.h svr4.h ${tm_file} mcore/mcore-elf.h" tmake_file=mcore/t-mcore @@ -1757,23 +1408,6 @@ mips-sgi-irix5cross64) # Irix5 host, Irix 6 target, cross64 # thread_file='irix' # fi ;; -mips-sni-sysv4) - if test x$gas = xyes - then - if test x$stabs = xyes - then - tm_file=mips/iris5gdb.h - else - tm_file="mips/sni-svr4.h mips/sni-gas.h" - fi - else - tm_file=mips/sni-svr4.h - fi - if test x$gnu_ld != xyes - then - use_collect2=yes - fi - ;; mips-sgi-irix5*) # SGI System V.4., IRIX 5 if test x$gas = xyes then @@ -1796,10 +1430,6 @@ mips-sgi-irix5*) # SGI System V.4., IRIX 5 # thread_file='irix' # fi ;; -mips-sgi-*) # would otherwise be caught by mips-*-elf* - echo "*** Configuration $machine not supported" 1>&2 - exit 1 - ;; mips*-*-netbsd*) # NetBSD/mips, either endian. target_cpu_default="MASK_GAS|MASK_ABICALLS" tm_file="elfos.h ${tm_file} mips/netbsd.h" @@ -1807,7 +1437,7 @@ mips*-*-netbsd*) # NetBSD/mips, either endian. ;; mips64*-*-linux*) tm_file="dbxelf.h elfos.h svr4.h linux.h ${tm_file} mips/linux.h mips/linux64.h" - tmake_file="t-slibgcc-elf-ver t-linux mips/t-linux mips/t-linux64" + tmake_file="t-slibgcc-elf-ver t-linux mips/t-linux64" # This default ABI is a partial lie: t-linux64 overrides the # DRIVER_SELF_SPEC that sets the default abi, in the spec file @@ -1840,12 +1470,6 @@ mips*-*-openbsd*) # mips big endian target_cpu_default="MASK_GAS|MASK_ABICALLS" tm_file="mips/openbsd-be.h ${tm_file}" ;; -mips-*-ecoff* | mipsel-*-ecoff*) - if test x$stabs = xyes; then - tm_file="${tm_file} dbx.h" - fi - tmake_file=mips/t-ecoff - ;; mipsisa32-*-elf* | mipsisa32el-*-elf*) tm_file="${tm_file} mips/elf.h" tmake_file=mips/t-isa3264 @@ -1896,16 +1520,6 @@ mips64orion-*-elf* | mips64orionel-*-elf*) target_cpu_default="MASK_64BIT|MASK_FLOAT64|MASK_GAS" tm_defines="MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_O64" ;; -mips64orion-*-rtems*) - tm_file="${tm_file} mips/elforion.h mips/elf64.h mips/rtems64.h rtems.h" - tmake_file="mips/t-elf t-rtems" - tmake_file=mips/t-elf - target_cpu_default="MASK_64BIT|MASK_FLOAT64|MASK_GAS" - tm_defines="MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_O64" - if test x$enable_threads = xyes; then - thread_file='rtems' - fi - ;; mips*-*-rtems*) tm_file="${tm_file} mips/elf.h mips/rtems.h rtems.h" tmake_file="mips/t-elf t-rtems" @@ -1920,14 +1534,6 @@ mipstx39-*-elf* | mipstx39el-*-elf*) mmix-knuth-mmixware) need_64bit_hwint=yes ;; -mn10200-*-*) - tm_file="dbxelf.h elfos.h svr4.h ${tm_file}" - if test x$stabs = xyes - then - tm_file="${tm_file} dbx.h" - fi - use_collect2=no - ;; mn10300-*-*) tm_file="dbxelf.h elfos.h svr4.h ${tm_file}" if test x$stabs = xyes @@ -1953,14 +1559,8 @@ pdp11-*-*) ;; avr-*-*) ;; -ns32k-*-openbsd*) - # Nothing special - ;; -romp-*-openbsd*) - # Nothing special - ;; powerpc-*-openbsd*) - tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-openbsd" + tmake_file="${tmake_file} rs6000/t-fprules " extra_headers= ;; powerpc64-*-linux*) @@ -1990,10 +1590,6 @@ powerpc*-*-freebsd*) tm_file="${tm_file} dbxelf.h elfos.h ${fbsd_tm_file} rs6000/sysv4.h rs6000/freebsd.h" tmake_file="rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm" ;; -powerpc-*-sysv*) - tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h" - tmake_file="rs6000/t-fprules rs6000/t-ppcos rs6000/t-ppccomm" - ;; powerpc-*-netbsd*) tm_file="${tm_file} dbxelf.h elfos.h netbsd.h netbsd-elf.h freebsd-spec.h rs6000/sysv4.h rs6000/netbsd.h" tmake_file="${tmake_file} rs6000/t-netbsd" @@ -2033,23 +1629,16 @@ powerpc-*-eabi*) ;; powerpc-*-rtems*) tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/eabi.h rs6000/rtems.h rtems.h" - tmake_file="rs6000/t-fprules rs6000/t-rtems t-rtems rs6000/t-ppccomm" + tmake_file="rs6000/t-fprules t-rtems rs6000/t-ppccomm" if test x$enable_threads = xyes; then thread_file='rtems' fi ;; -powerpc-*-linux*libc1) - tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/linux.h" - tmake_file="rs6000/t-fprules rs6000/t-ppcos t-slibgcc-elf-ver t-linux t-linux-gnulibc1 rs6000/t-ppccomm" - if test x$enable_threads = xyes; then - thread_file='posix' - fi - ;; -powerpc-*-linux-gnualtivec*) +powerpc-*-linux*altivec*) tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h" tmake_file="rs6000/t-fprules rs6000/t-ppcos t-slibgcc-elf-ver t-linux rs6000/t-ppccomm" ;; -powerpc-*-linux-gnuspe*) +powerpc-*-linux*spe*) tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxspe.h" tmake_file="rs6000/t-fprules rs6000/t-ppcos t-slibgcc-elf-ver t-linux rs6000/t-ppccomm" ;; @@ -2100,16 +1689,6 @@ powerpcle-*-eabi*) tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h" tmake_file="rs6000/t-fprules rs6000/t-ppcgas rs6000/t-ppccomm" ;; -rs6000-ibm-aix3.[01]*) - tm_file="${tm_file} rs6000/aix.h rs6000/aix31.h rs6000/xcoff.h" - use_collect2=yes - ;; -rs6000-ibm-aix3.2.[456789]* | powerpc-ibm-aix3.2.[456789]*) - tm_file="${tm_file} rs6000/aix.h rs6000/aix3newas.h rs6000/xcoff.h" - tmake_file="rs6000/t-fprules rs6000/t-newas" - use_collect2=yes - extra_headers= - ;; rs6000-ibm-aix4.[12]* | powerpc-ibm-aix4.[12]*) tm_file="${tm_file} rs6000/aix.h rs6000/aix41.h rs6000/xcoff.h" tmake_file="rs6000/t-fprules rs6000/t-newas" @@ -2137,18 +1716,6 @@ rs6000-ibm-aix[56789].* | powerpc-ibm-aix[56789].*) thread_file='aix' extra_headers= ;; -rs6000-ibm-aix*) - tm_file="${tm_file} rs6000/aix.h rs6000/xcoff.h" - use_collect2=yes - ;; -rs6000-bull-bosx) - tm_file="${tm_file} rs6000/aix.h rs6000/xcoff.h" - use_collect2=yes - ;; -rs6000-*-mach*) - tm_file="${tm_file} rs6000/mach.h" - use_collect2=yes - ;; rs6000-*-lynxos*) tm_file="lynx.h rs6000/lynx.h" tmake_file=rs6000/t-fprules @@ -2274,19 +1841,9 @@ sh-*-*) sparc-tti-*) tm_file="${tm_file} sparc/pbd.h" ;; -sparc-*-aout*) - tmake_file=sparc/t-sparcbare - tm_file="sparc/sparc.h aoutos.h sparc/aout.h libgloss.h" - ;; sparc-*-netbsdelf*) tm_file="${tm_file} elfos.h svr4.h sparc/sysv4.h netbsd.h netbsd-elf.h sparc/netbsd-elf.h" ;; -sparc-*-netbsd*) - tm_file="${tm_file} sparc/aout.h netbsd.h netbsd-aout.h sparc/netbsd.h" - tmake_file=t-netbsd - extra_parts="" - use_collect2=yes - ;; sparc-*-openbsd*) tm_file="sparc/sparc.h ${tm_file}" # needed to unconfuse gdb @@ -2299,51 +1856,15 @@ sparc64-*-openbsd*) gas=yes gnu_ld=yes with_cpu=ultrasparc ;; -sparc-*-bsd*) - tm_file="${tm_file} sparc/bsd.h" - ;; -sparc-*-chorusos*) - tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sol2.h sparc/sol2.h sparc/elf.h chorus.h" - tmake_file="sparc/t-chorus-elf sparc/t-crtfm" - extra_parts="crti.o crtn.o crtbegin.o crtend.o" - case x${enable_threads} in - xyes | xpthreads | xposix) - thread_file='posix' - ;; - esac - ;; sparc-*-elf*) tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sol2.h sparc/sol2.h sparc/elf.h" tmake_file="sparc/t-elf sparc/t-crtfm" extra_parts="crti.o crtn.o crtbegin.o crtend.o" ;; -sparc-*-linux*aout*) # SPARC's running GNU/Linux, a.out - tm_file="aoutos.h sparc/sparc.h sparc/aout.h sparc/linux-aout.h" - gnu_ld=yes - ;; -sparc-*-linux*libc1*) # SPARC's running GNU/Linux, libc5 - tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/linux.h" - tmake_file="t-slibgcc-elf-ver t-linux t-linux-gnulibc1 sparc/t-crtfm" - extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" - gnu_ld=yes - ;; sparc-*-linux*) # SPARC's running GNU/Linux, libc6 tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/linux.h" tmake_file="t-slibgcc-elf-ver t-linux sparc/t-crtfm" ;; -sparc-*-lynxos*) - if test x$gas = xyes - then - tm_file="${tm_file} lynx.h sparc/aout.h sparc/lynx.h" - else - tm_file="${tm_file} lynx-ng.h sparc/aout.h sparc/lynx-ng.h" - fi - tmake_file=sparc/t-sunos41 - ;; -sparc-*-rtemsaout*) # would otherwise be caught by sparc-*-rtems* - echo "*** Configuration $machine not supported" 1>&2 - exit 1 - ;; sparc-*-rtems*) tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sol2.h sparc/sol2.h sparc/elf.h sparc/rtemself.h rtems.h" tmake_file="sparc/t-elf sparc/t-crtfm t-rtems" @@ -2382,18 +1903,6 @@ sparc64-*-solaris2* | sparcv9-*-solaris2*) fi need_64bit_hwint=yes ;; -sparc-hal-solaris2*) - tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sol2.h sparc/sol2.h sparc/hal.h" - tmake_file="sparc/t-halos sparc/t-sol2 sparc/t-crtfm" - if test x$gnu_ld = xyes; then - tm_file="${tm_file} sparc/sol2-gld.h" - tmake_file="$tmake_file t-slibgcc-elf-ver" - else - tmake_file="$tmake_file t-slibgcc-sld" - fi - extra_parts="crt1.o crti.o crtn.o gmon.o crtbegin.o crtend.o" - thread_file='solaris' - ;; sparc-*-solaris2*) tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sol2.h sparc/sol2.h" if test x$gnu_ld = xyes; then @@ -2438,48 +1947,20 @@ sparc-*-solaris2*) fi fi ;; -sparc-*-sunos4.0*) - tm_file="${tm_file} sparc/aout.h sparc/sunos4.h" - use_collect2=yes - ;; -sparc-*-sunos4*) - tm_file="${tm_file} sparc/aout.h sparc/sunos4.h" - tmake_file=sparc/t-sunos41 - use_collect2=yes - if test x$gas = xyes; then - tm_file="${tm_file} sparc/sun4gas.h" - fi - ;; -sparc-*-sunos3*) - tm_file="${tm_file} sparc/aout.h sparc/sun4o3.h" - use_collect2=yes - ;; sparc-*-sysv4*) tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h" tmake_file=t-svr4 extra_parts="crtbegin.o crtend.o" ;; -sparclet-*-aout*) - tm_file="${tm_file} aoutos.h sparc/aout.h sparc/splet.h libgloss.h" - tmake_file=sparc/t-splet - ;; sparclite-*-coff*) tm_file="${tm_file} gofast.h sparc/lite.h svr3.h sparc/litecoff.h dbxcoff.h libgloss.h" tmake_file=sparc/t-sparclite ;; -sparclite-*-aout*) - tm_file="${tm_file} gofast.h sparc/aout.h sparc/lite.h aoutos.h libgloss.h" - tmake_file=sparc/t-sparclite - ;; sparclite-*-elf*) tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sol2.h sparc/sol2.h sparc/elf.h gofast.h sparc/liteelf.h" tmake_file="sparc/t-sparclite sparc/t-crtfm" extra_parts="crtbegin.o crtend.o" ;; -sparc86x-*-aout*) - tm_file="${tm_file} gofast.h sparc/aout.h sparc/sp86x-aout.h aoutos.h libgloss.h" - tmake_file=sparc/t-sp86x - ;; sparc86x-*-elf*) tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sol2.h sparc/sol2.h sparc/elf.h gofast.h sparc/sp86x-elf.h" tmake_file="sparc/t-sp86x sparc/t-crtfm" @@ -2520,13 +2001,6 @@ strongarm-*-elf*) md_file=arm/arm.md extra_modes=arm/arm-modes.def ;; -strongarm-*-coff*) - tm_file="arm/semi.h arm/aout.h arm/coff.h arm/strongarm-coff.h arm/arm.h" - tmake_file=arm/t-strongarm-coff - out_file=arm/arm.c - md_file=arm/arm.md - extra_modes=arm/arm-modes.def - ;; strongarm-*-pe) tm_file="arm/semi.h arm/aout.h arm/coff.h arm/strongarm-coff.h arm/arm.h arm/pe.h arm/strongarm-pe.h" tmake_file=arm/t-strongarm-pe @@ -2535,23 +2009,6 @@ strongarm-*-pe) extra_modes=arm/arm-modes.def extra_objs=pe.o ;; -thumb*-*-*) - { echo "config.gcc: error: -*** The Thumb targets have been deprecated. The equivalent -*** ARM based toolchain can now generate Thumb instructions -*** when the -mthumb switch is given to the compiler." 1>&2; exit 1; } - ;; -v850-*-rtems*) - tm_file="dbxelf.h elfos.h svr4.h ${tm_file} v850/v850.h v850/rtems.h rtems.h" - tmake_file="v850/t-v850 t-rtems" - if test x$stabs = xyes - then - tm_file="${tm_file} dbx.h" - fi - use_collect2=no - c_target_objs="v850-c.o" - cxx_target_objs="v850-c.o" - ;; v850e-*-*) target_cpu_default="TARGET_CPU_v850e" tm_file="dbxelf.h elfos.h svr4.h v850/v850.h" diff --git a/gcc/config/alpha/alpha-interix.h b/gcc/config/alpha/alpha-interix.h deleted file mode 100644 index 3f1580d05c6..00000000000 --- a/gcc/config/alpha/alpha-interix.h +++ /dev/null @@ -1,150 +0,0 @@ -/* Definitions of target machine for GNU compiler, for DEC Alpha - running Windows/NT. - Copyright (C) 1995, 1996, 1999, 2000, 2002 Free Software Foundation, Inc. - - Donn Terry, Softway Systems, Inc. - From code - Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* cpp handles __STDC__ */ -/* The three "Alpha" defines on the first such line are from the CLAXP spec */ -#define TARGET_OS_CPP_BUILTINS() \ - do { \ - builtin_define ("__INTERIX"); \ - builtin_define ("__OPENNT"); \ - builtin_define ("__Alpha_AXP"); \ - builtin_define ("_M_ALPHA"); \ - builtin_define ("_ALPHA_"); \ - builtin_define ("__stdcall="); \ - builtin_define ("__cdecl="); \ - builtin_assert ("system=unix"); \ - builtin_assert ("system=interix"); \ - } while (0) - -#undef CPP_SUBTARGET_SPEC -#define CPP_SUBTARGET_SPEC "\ --remap \ -%{posix:-D_POSIX_SOURCE} \ --isystem %$INTERIX_ROOT/usr/include" - -#undef TARGET_VERSION -#define TARGET_VERSION fprintf (stderr, " (alpha Interix)"); - -/* alpha.h sets this, but it doesn't apply to us */ -#undef OBJECT_FORMAT_ECOFF -#undef OBJECT_FORMAT_COFF - -/* LINK_SPEC */ - -/* MD_STARTFILE_PREFIX */ - -/* ASM_OUTPUT_LOOP_ALIGN; ASM_OUTPUT_ALIGN_CODE */ - -/* Codegen macro overrides for NT internal conventions */ - -/* the below are ecoff specific... we don't need them, so - undef them (they'll get a default later) */ - -#undef PUT_SDB_BLOCK_START -#undef PUT_SDB_BLOCK_END - -/* The following are needed for C++, but also needed for profiling */ - -/* Support const sections and the ctors and dtors sections for g++. */ - -#define READONLY_DATA_SECTION_ASM_OP "\t.rdata" - -/* Define the pseudo-ops used to switch to the .ctors and .dtors sections. - - Note that we want to give these sections the SHF_WRITE attribute - because these sections will actually contain data (i.e. tables of - addresses of functions in the current root executable or shared library - file) and, in the case of a shared library, the relocatable addresses - will have to be properly resolved/relocated (and then written into) by - the dynamic linker when it actually attaches the given shared library - to the executing process. (Note that on SVR4, you may wish to use the - `-z text' option to the ELF linker, when building a shared library, as - an additional check that you are doing everything right. But if you do - use the `-z text' option when building a shared library, you will get - errors unless the .ctors and .dtors sections are marked as writable - via the SHF_WRITE attribute.) */ - -#define CTORS_SECTION_ASM_OP "\t.ctors" -#define DTORS_SECTION_ASM_OP "\t.dtors" - -/* The linker will take care of this, and having them causes problems with - ld -r (specifically -rU). */ -#define CTOR_LISTS_DEFINED_EXTERNALLY 1 - -#define SET_ASM_OP "\t.set\t" -/* Output a definition (implements alias) */ -#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ -do \ -{ \ - fprintf ((FILE), "\t"); \ - assemble_name (FILE, LABEL1); \ - fprintf (FILE, "="); \ - assemble_name (FILE, LABEL2); \ - fprintf (FILE, "\n"); \ - } \ -while (0) - -/* We use the defaults, so undef the null definitions */ -#undef PUT_SDB_FUNCTION_START -#undef PUT_SDB_FUNCTION_END -#undef PUT_SDB_EPILOGUE_END - -#define HOST_PTR_PRINTF "%p" -#define HOST_PTR_AS_INT unsigned long - -#define PCC_BITFIELD_TYPE_MATTERS 1 -#define PCC_BITFIELD_TYPE_TEST TYPE_NATIVE(rec) -#define GROUP_BITFIELDS_BY_ALIGN TYPE_NATIVE(rec) - -/* DWARF2 Unwinding doesn't work with exception handling yet. */ -#undef DWARF2_UNWIND_INFO -#define DWARF2_UNWIND_INFO 0 - -/* Don't assume anything about the header files. */ -#define NO_IMPLICIT_EXTERN_C - -/* The definition of this macro implies that there are cases where - a scalar value cannot be returned in registers. - - On NT (according to the spec) anything except strings/array that fits - in 64 bits is returned in the registers (this appears to differ from - the rest of the Alpha family). */ - -#undef RETURN_IN_MEMORY -#define RETURN_IN_MEMORY(TYPE) \ - (TREE_CODE (TYPE) == ARRAY_TYPE || int_size_in_bytes(TYPE) > 8) - -#define ASM_LOAD_ADDR(loc, reg) " lda " #reg "," #loc "\n" - -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) \ -{ \ - alpha_write_verstamp (FILE); \ - fprintf (FILE, "\t.set noreorder\n"); \ - fprintf (FILE, "\t.set volatile\n"); \ - fprintf (FILE, "\t.set noat\n"); \ - fprintf (FILE, "\t.globl\t__fltused\n"); \ - ASM_OUTPUT_SOURCE_FILENAME (FILE, main_input_filename); \ -} diff --git a/gcc/config/alpha/alpha32.h b/gcc/config/alpha/alpha32.h deleted file mode 100644 index 8d9df0b8ebf..00000000000 --- a/gcc/config/alpha/alpha32.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Definitions of target machine for GNU compiler, for DEC Alpha - running Windows/NT. - Copyright (C) 1995, 1996, 1998, 1999 Free Software Foundation, Inc. - - Derived from code - Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) - - Donn Terry, Softway Systems, Inc. - - This file contains the code-generation stuff common to the 32-bit - versions of the DEC/Compaq Alpha architecture. It is shared by - Interix and NT/Win32 ports. It should not contain compile-time - or run-time dependent environment values (such as compiler options - or anything containing a file or pathname.) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#undef TARGET_ABI_WINDOWS_NT -#define TARGET_ABI_WINDOWS_NT 1 - -/* WinNT (and thus Interix) use unsigned int */ -#define SIZE_TYPE "unsigned int" - -/* Pointer is 32 bits but the hardware has 64-bit addresses, sign extended. */ -#undef POINTER_SIZE -#define POINTER_SIZE 32 -#define POINTERS_EXTEND_UNSIGNED 0 - -/* We don't change Pmode to the "obvious" SI mode... the above appears - to affect the in-memory size; we want the registers to stay DImode - to match the md file */ - -/* "long" is 32 bits. */ -#undef LONG_TYPE_SIZE -#define LONG_TYPE_SIZE 32 - - -/* Output assembler code for a block containing the constant parts - of a trampoline, leaving space for the variable parts. - - The trampoline should set the static chain pointer to value placed - into the trampoline and should branch to the specified routine. */ - -#undef TRAMPOLINE_TEMPLATE -#define TRAMPOLINE_TEMPLATE(FILE) \ -{ \ - fprintf (FILE, "\tbr $27,$LTRAMPP\n"); \ - fprintf (FILE, "$LTRAMPP:\n\tldl $1,12($27)\n"); \ - fprintf (FILE, "\tldl $27,16($27)\n"); \ - fprintf (FILE, "\tjmp $31,($27),0\n"); \ - fprintf (FILE, "\t.long 0,0\n"); \ -} - -/* Length in units of the trampoline for entering a nested function. */ - -#undef TRAMPOLINE_SIZE -#define TRAMPOLINE_SIZE 24 - -/* The alignment of a trampoline, in bits. */ - -#undef TRAMPOLINE_ALIGNMENT -#define TRAMPOLINE_ALIGNMENT 32 - -/* Emit RTL insns to initialize the variable parts of a trampoline. - FNADDR is an RTX for the address of the function's pure code. - CXT is an RTX for the static chain value for the function. */ - -#undef INITIALIZE_TRAMPOLINE -#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ - alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 20, 16, 12) diff --git a/gcc/config/alpha/t-interix b/gcc/config/alpha/t-interix deleted file mode 100644 index 3d570c65ba0..00000000000 --- a/gcc/config/alpha/t-interix +++ /dev/null @@ -1,7 +0,0 @@ -# t-interix - -# System headers will track gcc's needs. -USER_H= - -LIB1ASMSRC = alpha/lib1funcs.asm -LIB1ASMFUNCS = _divqu _divq _divlu _divl _remqu _remq _remlu _reml diff --git a/gcc/config/arm/conix-elf.h b/gcc/config/arm/conix-elf.h deleted file mode 100644 index f7e2f070397..00000000000 --- a/gcc/config/arm/conix-elf.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Definitions of target machine for GNU compiler, - for ARM with ConiX OS. - Copyright (C) 2000, 2001 Free Software Foundation, Inc. - Contributed by Philip Blundell <pb@futuretv.com> - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 2, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING. If not, write to - the Free Software Foundation, 59 Temple Place - Suite 330, - `Boston, MA 02111-1307, USA. */ - -/* elfos.h should have already been included. Now just override - any conflicting definitions and add any extras. */ - -/* Run-time Target Specification. */ -#undef TARGET_VERSION -#define TARGET_VERSION fputs (" (ARM/ELF ConiX)", stderr); - -/* Default to using APCS-32 and software floating point. */ -#undef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_32) - -#ifndef CPP_APCS_PC_DEFAULT_SPEC -#define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_32__" -#endif - -#ifndef SUBTARGET_CPU_DEFAULT -#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm7tdmi -#endif - -#define TARGET_OS_CPP_BUILTINS() \ - do { \ - builtin_define ("__CONIX__"); \ - builtin_define ("__ELF__"); \ - } while (0) diff --git a/gcc/config/arm/t-arm-aout b/gcc/config/arm/t-arm-aout deleted file mode 100644 index 2ce20e4fb74..00000000000 --- a/gcc/config/arm/t-arm-aout +++ /dev/null @@ -1,29 +0,0 @@ -LIB1ASMSRC = arm/lib1funcs.asm -LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _call_via_rX _interwork_call_via_rX - -# We want fine grained libraries, so use the new code to build the -# floating point emulation libraries. -FPBIT = fp-bit.c -DPBIT = dp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - echo '#ifndef __ARMEB__' >> fp-bit.c - echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c - echo '#endif' >> fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c - -dp-bit.c: $(srcdir)/config/fp-bit.c - echo '#ifndef __ARMEB__' > dp-bit.c - echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c - echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c - echo '#endif' >> dp-bit.c - cat $(srcdir)/config/fp-bit.c >> dp-bit.c - -# MULTILIB_OPTIONS = mhard-float/msoft-float mapcs-32/mapcs-26 mno-thumb-interwork/mthumb-interwork arm/thumb -# MULTILIB_DIRNAMES = le be fpu soft 32bit 26bit normal interwork arm thumb -# MULTILIB_MATCHES = -# MULTILIB_EXCEPTIONS = *mapcs-26/*mthumb-interwork* *mpacs-26/*mthumb* - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib diff --git a/gcc/config/arm/t-strongarm-coff b/gcc/config/arm/t-strongarm-coff deleted file mode 100644 index 0a66360cb27..00000000000 --- a/gcc/config/arm/t-strongarm-coff +++ /dev/null @@ -1,34 +0,0 @@ -LIB1ASMSRC = arm/lib1funcs.asm -LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func - -# We want fine grained libraries, so use the new code to build the -# floating point emulation libraries. -FPBIT = fp-bit.c -DPBIT = dp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - echo '#ifndef __ARMEB__' >> fp-bit.c - echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c - echo '#endif' >> fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c - -dp-bit.c: $(srcdir)/config/fp-bit.c - echo '#ifndef __ARMEB__' > dp-bit.c - echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c - echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c - echo '#endif' >> dp-bit.c - cat $(srcdir)/config/fp-bit.c >> dp-bit.c - -MULTILIB_OPTIONS = mlittle-endian/mbig-endian mhard-float/msoft-float -MULTILIB_DIRNAMES = le be fpu soft -MULTILIB_MATCHES = -EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib - -# Currently there is a bug somwehere in GCC's alias analysis -# or scheduling code that is breaking _fpmul_parts in fp-bit.c. -# Disabling function inlining is a workaround for this problem. -TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline diff --git a/gcc/config/arm/unknown-elf-oabi.h b/gcc/config/arm/unknown-elf-oabi.h deleted file mode 100644 index 112cc69916f..00000000000 --- a/gcc/config/arm/unknown-elf-oabi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* Definitions for non-Linux based ARM systems using ELF old abi - Copyright (C) 1998, 1999 Free Software Foundation, Inc. - Contributed by Catherine Moore <clm@cygnus.com> - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 2, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, 59 Temple Place - Suite 330, - Boston, MA 02111-1307, USA. */ - -/* Run-time Target Specification. */ -#undef TARGET_VERSION -#define TARGET_VERSION fputs (" (ARM/ELF non-Linux old abi)", stderr); - -#undef ASM_SPEC -#define ASM_SPEC "-moabi %{mbig-endian:-EB} %{mcpu=*:-mcpu=%*} %{march=*:-march=%*} \ - %{mapcs-*:-mapcs-%*} %{mthumb-interwork:-mthumb-interwork}" - diff --git a/gcc/config/i386/win32.h b/gcc/config/i386/win32.h deleted file mode 100644 index 93f58c93f12..00000000000 --- a/gcc/config/i386/win32.h +++ /dev/null @@ -1,173 +0,0 @@ -/* Operating system specific defines to be used when targeting GCC for - hosting on Windows NT 3.x, using a Unix style C library and tools, - as distinct from winnt.h, which is used to build GCC for use with a - windows style library and tool set and uses the Microsoft tools. - Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2002 - Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* Enable parsing of #pragma pack(push,<n>) and #pragma pack(pop). */ -#define HANDLE_PRAGMA_PACK_PUSH_POP 1 - -#define DBX_DEBUGGING_INFO 1 -#define SDB_DEBUGGING_INFO 1 -#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG - -#include "i386/unix.h" -#include "i386/bsd.h" -#include "i386/gas.h" -#include "dbxcoff.h" - -/* Augment TARGET_SWITCHES with the cygwin/win32 options. */ -#define MASK_WIN32 0x40000000 /* Use -lming32 interface */ -#define MASK_CYGWIN 0x20000000 /* Use -lcygwin interface */ -#define MASK_WINDOWS 0x10000000 /* Use windows interface */ -#define MASK_DLL 0x08000000 /* Use dll interface */ -#define MASK_NOP_FUN_DLLIMPORT 0x20000 /* Ignore dllimport for functions */ - -#define TARGET_WIN32 (target_flags & MASK_WIN32) -#define TARGET_CYGWIN (target_flags & MASK_CYGWIN) -#define TARGET_WINDOWS (target_flags & MASK_WINDOWS) -#define TARGET_DLL (target_flags & MASK_DLL) -#define TARGET_NOP_FUN_DLLIMPORT (target_flags & MASK_NOP_FUN_DLLIMPORT) - -#undef SUBTARGET_SWITCHES -#define SUBTARGET_SWITCHES \ - { "win32", MASK_WIN32, \ - N_("Use Mingw32 interface") }, \ - { "cygwin", MASK_CYGWIN, \ - N_("Use Cygwin interface") }, \ - { "windows", MASK_WINDOWS, \ - N_("Use bare Windows interface") }, \ - { "dll", MASK_DLL, \ - N_("Generate code for a DLL") }, \ - { "nop-fun-dllimport", MASK_NOP_FUN_DLLIMPORT, \ - N_("Ignore dllimport for functions") }, \ - { "no-nop-fun-dllimport", MASK_NOP_FUN_DLLIMPORT, "" }, - - -#define TARGET_OS_CPP_BUILTINS() \ - do \ - { \ - builtin_define ("_WIN32"); \ - builtin_define_std ("WINNT"); \ - builtin_define ("_X86_"); \ - builtin_define ("__stdcall=__attribute__((__stdcall__))"); \ - builtin_define ("__cdecl=__attribute__((__cdecl__))"); \ - builtin_assert ("system=winnt"); \ - if (TARGET_CYGWIN) \ - { \ - builtin_define ("__CYGWIN32__"); \ - builtin_define ("__CYGWIN__"); \ - } \ - else \ - builtin_define ("__MINGW32__"); \ - } \ - while (0) - -#undef STARTFILE_SPEC - -#define STARTFILE_SPEC "%{mdll:dllcrt0%O%s} %{!mdll: %{!mcygwin:mcrt0%O%s} \ - %{mcygwin:crt0%O%s} %{pg:gcrt0%O%s}}" - -#undef CPP_SPEC -#define CPP_SPEC "%{posix:-D_POSIX_SOURCE} \ - %{!mcygwin:-iwithprefixbefore include/mingw32}" - -/* We have to dynamic link to get to the system DLLs. All of libc, libm and - the Unix stuff is in cygwin.dll. The import library is called - 'libcygwin.a'. For Windows applications, include more libraries, but - always include kernel32. We'd like to specific subsystem windows to - ld, but that doesn't work just yet. */ - -#undef LIB_SPEC -#define LIB_SPEC "%{pg:-lgmon} \ - %{!mcygwin:-lmingw32 -lmoldname -lmsvcrt -lcrtdll} \ - %{mcygwin:-lcygwin} %{mwindows:-luser32 -lgdi32 -lcomdlg32} \ - -lkernel32 -ladvapi32 -lshell32" - -#define LINK_SPEC "%{mwindows:--subsystem windows} \ - %{mdll:--dll -e _DllMainCRTStartup@12}" - -#define SIZE_TYPE "unsigned int" -#define PTRDIFF_TYPE "int" -#define WCHAR_TYPE_SIZE 16 -#define WCHAR_TYPE "short unsigned int" -/* Currently we do not have the atexit() function, - so take that from libgcc2.c */ - -#define NEED_ATEXIT 1 - -#undef TARGET_ENCODE_SECTION_INFO -#define TARGET_ENCODE_SECTION_INFO i386_pe_encode_section_info -#undef TARGET_STRIP_NAME_ENCODING -#define TARGET_STRIP_NAME_ENCODING i386_pe_strip_name_encoding_full - -/* Emit code to check the stack when allocating more that 4000 - bytes in one go. */ - -#define CHECK_STACK_LIMIT 4000 - -/* By default, target has a 80387, uses IEEE compatible arithmetic, - and returns float values in the 387 and needs stack probes */ -#undef TARGET_SUBTARGET_DEFAULT - -#define TARGET_SUBTARGET_DEFAULT \ - (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_STACK_PROBE) - -/* This is how to output an assembler line - that says to advance the location counter - to a multiple of 2**LOG bytes. */ - -#undef ASM_OUTPUT_ALIGN -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ - if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) - -/* Define this macro if in some cases global symbols from one translation - unit may not be bound to undefined symbols in another translation unit - without user intervention. For instance, under Microsoft Windows - symbols must be explicitly imported from shared libraries (DLLs). */ -#define MULTIPLE_SYMBOL_SPACES - -extern void i386_pe_unique_section PARAMS ((tree, int)); -#define TARGET_ASM_UNIQUE_SECTION i386_pe_unique_section - -#define SUPPORTS_ONE_ONLY 1 - -/* Switch into a generic section. */ -#define TARGET_ASM_NAMED_SECTION i386_pe_asm_named_section - -/* Select attributes for named sections. */ -#define TARGET_SECTION_TYPE_FLAGS i386_pe_section_type_flags - -#undef ASM_COMMENT_START -#define ASM_COMMENT_START " #" - -/* Don't assume anything about the header files. */ -#define NO_IMPLICIT_EXTERN_C - -#define SUBTARGET_PROLOGUE \ - if (current_function_profile \ - && MAIN_NAME_P (DECL_NAME (current_function_decl)) \ - { \ - rtx xops[1]; \ - xops[0] = gen_rtx_MEM (FUNCTION_MODE, \ - gen_rtx (SYMBOL_REF, Pmode, "_monstartup")); \ - emit_call_insn (gen_rtx (CALL, VOIDmode, xops[0], const0_rtx)); \ - } diff --git a/gcc/config/m68k/3b1.h b/gcc/config/m68k/3b1.h deleted file mode 100644 index 5b3fe4e02b3..00000000000 --- a/gcc/config/m68k/3b1.h +++ /dev/null @@ -1,470 +0,0 @@ -/* Definitions of target machine for GNU compiler. - AT&T UNIX PC version (pc7300, 3b1) - Copyright (C) 1987, 1993, 1996, 1999, 2000 Free Software Foundation, Inc. - Contributed by Alex Crain (alex@umbc3.umd.edu). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#define SGS_SWITCH_TABLES /* Different switch table handling */ - -#include "m68k/hp320.h" - -/* See m68k.h. 0 means 680[01]0 with no 68881. */ - -#undef TARGET_DEFAULT -#define TARGET_DEFAULT 0 - -/* Don't try using XFmode. */ -#undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* -m68020 requires special flags to the assembler. */ - -#undef ASM_SPEC -#define ASM_SPEC "%{m68020:-68020}%{!m68020:-68010} %{m68881:-68881}" - -/* we use /lib/libp/lib* when profiling */ - -#undef LIB_SPEC -#define LIB_SPEC "%{!shlib:%{p:-L/lib/libp} %{pg:-L/lib/libp} -lc}" - -/* shared libraries need to use crt0s.o */ - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC \ - "%{!shlib:%{pg:mcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}\ - %{shlib:crt0s.o%s shlib.ifile%s} " - -/* Make output for SDB. */ - -#define SDB_DEBUGGING_INFO 1 - -/* The .file command should always begin the output. */ - -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) \ -output_file_directive ((FILE), main_input_filename) - -/* Define __HAVE_68881__ in preprocessor if -m68881 is specified. - This will control the use of inline 68881 insns in certain macros. */ - -#undef CPP_SPEC -#define CPP_SPEC "%{m68881:-D__HAVE_68881__}" - -/* Names to predefine in the preprocessor for this target machine. */ -/* ihnp4!lmayk!lgm@eddie.mit.edu says mc68000 and m68k should not be here. */ - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dmc68k -Dunix -Dunixpc -D__motorola__ -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k" - -#undef REGISTER_NAMES -#define REGISTER_NAMES \ -{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ - "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", \ - "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7"} - -/* Specify how to pad function arguments. - Value should be `upward', `downward' or `none'. - Same as the default, except no padding for large or variable-size args. */ - -#define FUNCTION_ARG_PADDING(MODE, TYPE) \ - (((MODE) == BLKmode \ - ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ - && int_size_in_bytes (TYPE) < PARM_BOUNDARY / BITS_PER_UNIT) \ - : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY) \ - ? downward : none) - -/* The 3b1 does not have `atexit'. */ - -#define NEED_ATEXIT - -/* Override parts of m68k.h to fit the SGS-3b1 assembler. */ - -#undef TARGET_VERSION -#undef ASM_OUTPUT_ALIGN -#undef ASM_OUTPUT_SOURCE_FILENAME -#undef ASM_OUTPUT_SOURCE_LINE -#undef PRINT_OPERAND_ADDRESS -#undef ASM_GENERATE_INTERNAL_LABEL -#undef FUNCTION_PROFILER -#undef ASM_OUTPUT_ADDR_VEC_ELT -#undef ASM_OUTPUT_ADDR_DIFF_ELT -#undef ASM_OUTPUT_OPCODE -#undef ASM_OUTPUT_LOCAL -#undef USER_LABEL_PREFIX -#undef ASM_OUTPUT_ASCII - -#define TARGET_VERSION fprintf (stderr, " (68k, SGS/AT&T unixpc syntax)"); - -#define ASM_PN_FORMAT "%s_%%%lu" - -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ -do { \ - if ((LOG) == 1) \ - fprintf (FILE, "\teven\n"); \ - else if ((LOG) != 0) \ - abort (); \ -} while (0) - -/* This is how to output an assembler line - that says to advance the location counter by SIZE bytes. */ - -#undef ASM_OUTPUT_SKIP -#define ASM_OUTPUT_SKIP(FILE,SIZE) \ - fprintf (FILE, "\tspace %d\n", (int)(SIZE)) - -/* Can't use ASM_OUTPUT_SKIP in text section; it doesn't leave 0s. */ - -#define ASM_NO_SKIP_IN_TEXT 1 - -/* The beginnings of sdb support... */ - -#define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \ - do { fprintf (FILE, "\tfile\t"); \ - output_quoted_string (FILE, FILENAME); \ - fprintf (FILE, "\n"); \ - } while (0) - -#define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO) \ - fprintf (FILE, "\tln\t%d\n", \ - (sdb_begin_function_line \ - ? (LINENO) - sdb_begin_function_line : 1)) - -/* Yet another null terminated string format. */ - -#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ - do { register size_t sp = 0, lp = 0, limit = (LEN); \ - fprintf ((FILE), "\tbyte\t"); \ - loop: \ - if ((PTR)[sp] > ' ' && ! ((PTR)[sp] & 0x80) && (PTR)[sp] != '\\') \ - { lp += 3; \ - fprintf ((FILE), "'%c", (PTR)[sp]); } \ - else \ - { lp += 5; \ - fprintf ((FILE), "0x%x", (PTR)[sp]); } \ - if (++sp < limit) \ - { if (lp > 60) \ - { lp = 0; \ - fprintf ((FILE), "\n%s", ASCII_DATA_ASM_OP); } \ - else \ - putc (',', (FILE)); \ - goto loop; } \ - putc ('\n', (FILE)); } while (0) - -/* Note that in the case of the movhi which fetches an element of - an ADDR_DIFF_VEC the offset output is too large by 2. - This is because the 3b1 assembler refuses to subtract 2. - ASM_OUTPUT_CASE_LABEL, below, compensates for this. */ - -#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -{ register rtx reg1, reg2, breg, ireg; \ - register rtx addr = ADDR; \ - rtx offset; \ - switch (GET_CODE (addr)) \ - { \ - case REG: \ - fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \ - break; \ - case PRE_DEC: \ - fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \ - break; \ - case POST_INC: \ - fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \ - break; \ - case PLUS: \ - reg1 = 0; reg2 = 0; \ - ireg = 0; breg = 0; \ - offset = 0; \ - if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ - { \ - offset = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ - { \ - offset = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - if (GET_CODE (addr) != PLUS) ; \ - else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ - { \ - reg1 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ - { \ - reg1 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - else if (GET_CODE (XEXP (addr, 0)) == MULT) \ - { \ - reg1 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == MULT) \ - { \ - reg1 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - else if (GET_CODE (XEXP (addr, 0)) == REG) \ - { \ - reg1 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == REG) \ - { \ - reg1 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ - || GET_CODE (addr) == SIGN_EXTEND) \ - { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ -/* for OLD_INDEXING \ - else if (GET_CODE (addr) == PLUS) \ - { \ - if (GET_CODE (XEXP (addr, 0)) == REG) \ - { \ - reg2 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == REG) \ - { \ - reg2 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - } \ - */ \ - if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ - if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ - || GET_CODE (reg1) == MULT)) \ - || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ - { breg = reg2; ireg = reg1; } \ - else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ - { breg = reg1; ireg = reg2; } \ - if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ - { int scale = 1; \ - if (GET_CODE (ireg) == MULT) \ - { scale = INTVAL (XEXP (ireg, 1)); \ - ireg = XEXP (ireg, 0); } \ - if (GET_CODE (ireg) == SIGN_EXTEND) \ - fprintf (FILE, "LD%%%d(%%pc,%s.w", \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - reg_names[REGNO (XEXP (ireg, 0))]); \ - else \ - fprintf (FILE, "LD%%%d(%%pc,%s.l", \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - reg_names[REGNO (ireg)]); \ - if (scale != 1) fprintf (FILE, "*%d", scale); \ - fprintf (FILE, ")"); \ - break; } \ - if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \ - { fprintf (FILE, "LD%%%d(%%pc,%s.l", \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - reg_names[REGNO (breg)]); \ - putc (')', FILE); \ - break; } \ - if (ireg != 0 || breg != 0) \ - { int scale = 1; \ - if (breg == 0) \ - abort (); \ - if (addr != 0) \ - output_addr_const (FILE, addr); \ - fprintf (FILE, "(%s", reg_names[REGNO (breg)]); \ - if (ireg != 0) \ - putc (',', FILE); \ - if (ireg != 0 && GET_CODE (ireg) == MULT) \ - { scale = INTVAL (XEXP (ireg, 1)); \ - ireg = XEXP (ireg, 0); } \ - if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ - fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \ - else if (ireg != 0) \ - fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \ - if (scale != 1) fprintf (FILE, "*%d", scale); \ - putc (')', FILE); \ - break; \ - } \ - else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ - { fprintf (FILE, "LD%%%d(%%pc,%s.w)", \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - reg_names[REGNO (reg1)]); \ - break; } \ - default: \ - if (GET_CODE (addr) == CONST_INT \ - && INTVAL (addr) < 0x8000 \ - && INTVAL (addr) >= -0x8000) \ - fprintf (FILE, "%d", INTVAL (addr)); \ - else \ - output_addr_const (FILE, addr); \ - }} - -#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ - sprintf ((LABEL), "%s%%%ld", (PREFIX), (long)(NUM)) - -/* Must put address in %a0 , not %d0 . -- LGM, 7/15/88 */ -#define FUNCTION_PROFILER(FILE, LABEL_NO) \ - fprintf (FILE, "\tmov.l &LP%%%d,%%a0\n\tjsr mcount\n", (LABEL_NO)) - -#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ - fprintf (FILE, "\tlong L%%%d\n", (VALUE)) - -#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ - fprintf (FILE, "\tshort L%%%d-L%%%d\n", (VALUE), (REL)) - -/* ihnp4!lmayk!lgm says that `short 0' triggers assembler bug; - `short L%nn-L%nn' supposedly works. */ -#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \ - if (! RTX_INTEGRATED_P (TABLE)) \ - fprintf (FILE, "\tswbeg &%d\n%s%%%d:\n", \ - XVECLEN (PATTERN (TABLE), 1), (PREFIX), (NUM)); \ - else \ - fprintf (FILE, "\tswbeg &%d\n%s%%%d:\n\tshort %s%%%d-%s%%%d\n", \ - XVECLEN (PATTERN (TABLE), 1) + 1, (PREFIX), (NUM), \ - (PREFIX), (NUM), (PREFIX), (NUM)) - -/* At end of a switch table, define LDnnn iff the symbol LInnn was defined. - Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" - fails to assemble. Luckily "LDnnn(pc,d0.l*2)" produces the results - we want. This difference can be accommodated by making the assembler - define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other - string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END - macro. */ - -#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ -{ if (switch_table_difference_label_flag) \ - fprintf (FILE, "\tset LD%%%d,L%%%d-LI%%%d\n", (NUM), (NUM), (NUM)); \ - switch_table_difference_label_flag = 0; } - -int switch_table_difference_label_flag; - -#define ASM_OUTPUT_OPCODE(FILE, PTR) \ -{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ - { ++(PTR); \ - while (*(PTR) != ' ') \ - { putc (*(PTR), (FILE)); ++(PTR); } \ - fprintf ((FILE), ".w"); } \ - else if ((PTR)[0] == 's') \ - { \ - if (!strncmp ((PTR), "swap", 4)) \ - { fprintf ((FILE), "swap.w"); (PTR) += 4; } \ - } \ - else if ((PTR)[0] == 'f') \ - { \ - if (!strncmp ((PTR), "fmove", 5)) \ - { fprintf ((FILE), "fmov"); (PTR) += 5; } \ - else if (!strncmp ((PTR), "fbne", 4)) \ - { fprintf ((FILE), "fbneq"); (PTR) += 4; } \ - } \ -/* MOVE, MOVEA, MOVEQ, MOVEC ==> MOV */ \ - else if ((PTR)[0] == 'm' && (PTR)[1] == 'o' \ - && (PTR)[2] == 'v' && (PTR)[3] == 'e') \ - { fprintf ((FILE), "mov"); (PTR) += 4; \ - if ((PTR)[0] == 'q' || (PTR)[0] == 'a' \ - || (PTR)[0] == 'c') (PTR)++; } \ -/* SUB, SUBQ, SUBA, SUBI ==> SUB */ \ - else if ((PTR)[0] == 's' && (PTR)[1] == 'u' \ - && (PTR)[2] == 'b') \ - { fprintf ((FILE), "sub"); (PTR) += 3; \ - if ((PTR)[0] == 'q' || (PTR)[0] == 'i' \ - || (PTR)[0] == 'a') (PTR)++; } \ -/* CMP, CMPA, CMPI, CMPM ==> CMP */ \ - else if ((PTR)[0] == 'c' && (PTR)[1] == 'm' \ - && (PTR)[2] == 'p') \ - { fprintf ((FILE), "cmp"); (PTR) += 3; \ - if ((PTR)[0] == 'a' || (PTR)[0] == 'i' \ - || (PTR)[0] == 'm') (PTR)++; } \ -} - -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -( fputs ("\tlcomm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%u\n", (int)(ROUNDED))) - -#define USER_LABEL_PREFIX "" - -/* Override usual definitions of SDB output macros. - These definitions differ only in the absence of the period - at the beginning of the name of the directive - and in the use of `~' as the symbol for the current location. */ - -#define PUT_SDB_SCL(a) fprintf(asm_out_file, "\tscl\t%d;", (a)) -#define PUT_SDB_INT_VAL(a) fprintf (asm_out_file, "\tval\t%d;", (a)) -#define PUT_SDB_VAL(a) \ -( fputs ("\tval\t", asm_out_file), \ - output_addr_const (asm_out_file, (a)), \ - fputc (';', asm_out_file)) - -#define PUT_SDB_DEF(a) \ -do { fprintf (asm_out_file, "\tdef\t"); \ - ASM_OUTPUT_LABELREF (asm_out_file, a); \ - fprintf (asm_out_file, ";"); } while (0) - -#define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s;",a) -#define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file) -#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o;", a) -#define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d;", a) -#define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t") - -#define PUT_SDB_TAG(a) \ -do { fprintf (asm_out_file, "\ttag\t"); \ - ASM_OUTPUT_LABELREF (asm_out_file, a); \ - fprintf (asm_out_file, ";"); } while (0) - -#define PUT_SDB_BLOCK_START(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~bb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_BLOCK_END(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~eb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_FUNCTION_START(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~bf;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_FUNCTION_END(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~ef;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_EPILOGUE_END(NAME) \ - fprintf (asm_out_file, \ - "\tdef\t%s;\tval\t~;\tscl\t-1;\tendef\n", \ - (NAME)) - -#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ - sprintf ((BUFFER), "~%dfake", (NUMBER)); - -/* Define subroutines to call to handle multiply, divide, and remainder. - Use the subroutines that the 3b1's library provides. - The `*' prevents an underscore from being prepended by the compiler. */ - -#define DIVSI3_LIBCALL "*ldiv" -#define UDIVSI3_LIBCALL "*uldiv" -#define MODSI3_LIBCALL "*lrem" -#define UMODSI3_LIBCALL "*ulrem" -#define MULSI3_LIBCALL "*lmul" -#define UMULSI3_LIBCALL "*ulmul" - -/* Definitions for collect2. */ - -#define OBJECT_FORMAT_COFF -#define MY_ISCOFF(magic) \ - ((magic) == MC68KWRMAGIC || (magic) == MC68KROMAGIC || (magic) == MC68KPGMAGIC) diff --git a/gcc/config/m68k/3b1g.h b/gcc/config/m68k/3b1g.h deleted file mode 100644 index 5850a8a0d22..00000000000 --- a/gcc/config/m68k/3b1g.h +++ /dev/null @@ -1,61 +0,0 @@ -/* Definitions of target machine for GNU compiler, for a 3b1 using GAS. - Copyright (C) 1987, 1988 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#include "m68k/m68k.h" - -/* See m68k.h. 0 means 68000 with no 68881. */ -#define TARGET_DEFAULT 0 - -/* Don't try using XFmode. */ -#undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* Define __HAVE_68881 in preprocessor only if -m68881 is specified. - This will control the use of inline 68881 insns in certain macros. - Also inform the program which CPU this is for. */ -#define CPP_SPEC "%{m68881:-D__HAVE_68881__} \ -%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}" - -/* -m68020 requires special flags to the assembler. */ -#define ASM_SPEC \ - "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!m68020:-mc68010}}" - -/* Names to predefine in the preprocessor for this target machine. */ -#define CPP_PREDEFINES "-Dmc68000 -Dmc68k -Dunix -Dunixpc -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k" - -/* This is (not really) BSD, so (but) it wants DBX format. */ -#define DBX_DEBUGGING_INFO 1 - -/* Specify how to pad function arguments. - Value should be `upward', `downward' or `none'. - Same as the default, except no padding for large or variable-size args. */ -#define FUNCTION_ARG_PADDING(MODE, TYPE) \ - (((MODE) == BLKmode \ - ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ - && int_size_in_bytes (TYPE) < PARM_BOUNDARY / BITS_PER_UNIT) \ - : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY) \ - ? downward : none) - -/* Every structure or union's size must be a multiple of 2 bytes. */ -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* Generate calls to memcpy, memcmp and memset. */ -#define TARGET_MEM_FUNCTIONS - diff --git a/gcc/config/m68k/amix.h b/gcc/config/m68k/amix.h deleted file mode 100644 index 540cd1d6ec8..00000000000 --- a/gcc/config/m68k/amix.h +++ /dev/null @@ -1,144 +0,0 @@ -/* Definitions of target machine for GNU compiler. - Commodore Amiga A3000UX version. - - Copyright (C) 1991, 1993, 2000 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#include "m68k/m68kv4.h" - -/* rhealey@aggregate.com says dots are no good either. */ -#define NO_DOT_IN_LABEL - -/* Alter assembler syntax for fsgldiv and fsglmul. - It is highly likely that this is a generic SGS m68k assembler dependency. - If so, it should eventually be handled in the m68k/sgs.h ASM_OUTPUT_OPCODE - macro, like the other SGS assembler quirks. -fnf */ - -#define FSGLDIV_USE_S /* Use fsgldiv.s, not fsgldiv.x */ -#define FSGLMUL_USE_S /* Use fsglmul.s, not fsglmul.x */ - -/* Names to predefine in the preprocessor for this target machine. For the - Amiga, these definitions match those of the native AT&T compiler. Note - that we override the definition in m68kv4.h, where SVR4 is defined and - AMIX isn't. */ - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES \ - "-Dm68k -Dunix -DAMIX -D__svr4__ -D__motorola__ \ - -Amachine=m68k -Acpu=m68k -Asystem=unix -Alint=off" - -/* At end of a switch table, define LDnnn iff the symbol LInnn was defined. - Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" - fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results - we want. This difference can be accommodated by making the assembler - define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other - string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END - macro. (the Amiga assembler has this bug) */ - -#undef ASM_OUTPUT_CASE_END -#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ -do { \ - if (switch_table_difference_label_flag) \ - asm_fprintf ((FILE), "%s%LLD%d,%LL%d\n", SET_ASM_OP, (NUM), (NUM));\ - switch_table_difference_label_flag = 0; \ -} while (0) - -int switch_table_difference_label_flag; - -/* This says how to output assembler code to declare an - uninitialized external linkage data object. Under SVR4, - the linker seems to want the alignment of data objects - to depend on their types. We do exactly that here. - [This macro overrides the one in svr4.h because the amix assembler - has a minimum default alignment of 4, and will not accept any - explicit alignment smaller than this. -fnf] */ - -#undef ASM_OUTPUT_ALIGNED_COMMON -#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ -do { \ - fputs ("\t.comm\t", (FILE)); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), ",%u,%u\n", (SIZE), MAX ((ALIGN) / BITS_PER_UNIT, 4)); \ -} while (0) - -/* This says how to output assembler code to declare an - uninitialized internal linkage data object. Under SVR4, - the linker seems to want the alignment of data objects - to depend on their types. We do exactly that here. - [This macro overrides the one in svr4.h because the amix assembler - has a minimum default alignment of 4, and will not accept any - explicit alignment smaller than this. -fnf] */ - -#undef ASM_OUTPUT_ALIGNED_LOCAL -#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ -do { \ - fprintf ((FILE), "%s%s,%u,%u\n", \ - BSS_ASM_OP, (NAME), (int)(SIZE), MAX ((ALIGN) / BITS_PER_UNIT, 4)); \ -} while (0) - -/* This definition of ASM_OUTPUT_ASCII is the same as the one in m68k/sgs.h, - which has been overridden by the one in svr4.h. However, we can't use - the one in svr4.h because the amix assembler croaks on some of the - strings that it emits (such as .string "\"%s\"\n"). */ - -#undef ASM_OUTPUT_ASCII -#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ -do { \ - register size_t sp = 0, limit = (LEN); \ - fputs (integer_asm_op (1, TRUE), (FILE)); \ - do { \ - int ch = (PTR)[sp]; \ - if (ch > ' ' && ! (ch & 0x80) && ch != '\\') \ - { \ - fprintf ((FILE), "'%c", ch); \ - } \ - else \ - { \ - fprintf ((FILE), "0x%x", ch); \ - } \ - if (++sp < limit) \ - { \ - if ((sp % 10) == 0) \ - { \ - fprintf ((FILE), "\n%s", integer_asm_op (1, TRUE)); \ - } \ - else \ - { \ - putc (',', (FILE)); \ - } \ - } \ - } while (sp < limit); \ - putc ('\n', (FILE)); \ -} while (0) - -/* The following should be unnecessary as a result of PIC_CASE_VECTOR_ADDRESS. - But rhealey@aggregate.com says they are still needed. */ - -/* Override these for the sake of an assembler bug: the Amix - assembler can't handle .LC0@GOT syntax. This pollutes the final - table for shared librarys but what's a poor soul to do; sigh... RFH */ - -#undef ASM_GENERATE_INTERNAL_LABEL -#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ -do { \ - if (flag_pic && !strcmp(PREFIX,"LC")) \ - sprintf (LABEL, "*%s%%%ld", PREFIX, (long)(NUM)); \ - else \ - sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)); \ -} while (0) diff --git a/gcc/config/m68k/atari.h b/gcc/config/m68k/atari.h deleted file mode 100644 index 67528c3a7df..00000000000 --- a/gcc/config/m68k/atari.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Definitions of target machine for GNU compiler. - Atari TT ASV version. - Copyright (C) 1994, 1995, 2000 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#include "m68k/m68kv4.h" - -/* Dollars and dots in labels are not allowed. */ - -#define NO_DOLLAR_IN_LABEL -#define NO_DOT_IN_LABEL - -/* Alter assembler syntax for fsgldiv and fsglmul. - It is highly likely that this is a generic SGS m68k assembler dependency. - If so, it should eventually be handled in the m68k/sgs.h ASM_OUTPUT_OPCODE - macro, like the other SGS assembler quirks. -fnf */ - -#define FSGLDIV_USE_S /* Use fsgldiv.s, not fsgldiv.x */ -#define FSGLMUL_USE_S /* Use fsglmul.s, not fsglmul.x */ - -/* At end of a switch table, define LDnnn iff the symbol LInnn was defined. - Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" - fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results - we want. This difference can be accommodated by making the assembler - define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other - string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END - macro. (the Amiga assembler has this bug) */ - -#undef ASM_OUTPUT_CASE_END -#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ -do { \ - if (switch_table_difference_label_flag) \ - asm_fprintf ((FILE), "%s%LLD%d,%LL%d\n", SET_ASM_OP, (NUM), (NUM));\ - switch_table_difference_label_flag = 0; \ -} while (0) - -int switch_table_difference_label_flag; - -/* This definition of ASM_OUTPUT_ASCII is the same as the one in m68k/sgs.h, - which has been overridden by the one in svr4.h. However, we can't use - the one in svr4.h because the ASV assembler croaks on some of the - strings that it emits (such as .string "\"%s\"\n"). */ - -#undef ASM_OUTPUT_ASCII -#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ -{ \ - register size_t sp = 0, limit = (LEN); \ - fputs (integer_asm_op (1, TRUE), (FILE)); \ - do { \ - int ch = (PTR)[sp]; \ - if (ch > ' ' && ! (ch & 0x80) && ch != '\\') \ - { \ - fprintf ((FILE), "'%c", ch); \ - } \ - else \ - { \ - fprintf ((FILE), "0x%x", ch); \ - } \ - if (++sp < limit) \ - { \ - if ((sp % 10) == 0) \ - { \ - fprintf ((FILE), "\n%s", integer_asm_op (1, TRUE)); \ - } \ - else \ - { \ - putc (',', (FILE)); \ - } \ - } \ - } while (sp < limit); \ - putc ('\n', (FILE)); \ -} - -/* Override these for the sake of an assembler bug: the ASV - assembler can't handle .LC0@GOT syntax. This pollutes the final - table for shared librarys but what's a poor soul to do; sigh... RFH */ - -#undef ASM_GENERATE_INTERNAL_LABEL -#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ -do { \ - if (flag_pic && !strcmp(PREFIX,"LC")) \ - sprintf (LABEL, "*%s%%%ld", PREFIX, (long)(NUM)); \ - else \ - sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)); \ -} while (0) diff --git a/gcc/config/m68k/ccur-GAS.h b/gcc/config/m68k/ccur-GAS.h deleted file mode 100644 index 4df5ec4bcd0..00000000000 --- a/gcc/config/m68k/ccur-GAS.h +++ /dev/null @@ -1,129 +0,0 @@ -/* Definitions of target machine for GNU compiler. Concurrent 68k version. - Copyright (C) 1987, 1988, 1995, 1996, 1997 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifndef MASSCOMP -#define MASSCOMP -#endif - -#ifndef CONCURRENT -#define CONCURRENT -#endif - -#ifndef __mc68000__ -#define __mc68000__ -#endif - -#ifndef __mc68020__ -#define __mc68020__ -#endif - -#define USE_GAS -#define MOVE_RATIO 100 - -#define SPACE_AFTER_L_OPTION -#define SWITCHES_NEED_SPACES "oL" - -/* See m68k.h. 7 means 68020 with 68881. */ -#define TARGET_DEFAULT (MASK_68040|MASK_BITFIELD|MASK_68881|MASK_68020) - -#include "m68k/m68k.h" - -#define SIZE_TYPE "int" - -/* for 68k machines this only needs to be TRUE for the 68000 */ - -#undef STRICT_ALIGNMENT -#define STRICT_ALIGNMENT 0 - -/* Names to predefine in the preprocessor for this target machine. */ -#define CPP_PREDEFINES \ - "-Dmc68000 -Dmasscomp -DMASSCOMP -Dunix -DLANGUAGE_C -Dconcurrent -DCONCURRENT" - -#undef TARGET_VERSION -#define TARGET_VERSION fprintf (stderr, " (68k, GNU GAS syntax)"); - -/* Discard internal local symbols beginning with 'L'. */ -#define LINK_SPEC "-X" - -/* Every structure or union's size must be a multiple of 4 bytes. */ -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* No data type wants to be aligned rounder than this. */ -#undef BIGGEST_ALIGNMENT -#define BIGGEST_ALIGNMENT 32 - -/* Allocation boundary (in *bits*) for storing pointers in memory. */ -#undef POINTER_BOUNDARY -#define POINTER_BOUNDARY 32 - -/* Alignment of field after `int : 0' in a structure. */ -#undef EMPTY_FIELD_BOUNDARY -#define EMPTY_FIELD_BOUNDARY 32 - -/* Allocation boundary in bits for the code of a function */ -#undef FUNCTION_BOUNDARY -#define FUNCTION_BOUNDARY 32 - -/* Make strings long-word aligned so dhrystones will run faster. */ -#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ - (TREE_CODE (EXP) == STRING_CST \ - && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) - -/* Make arrays of chars word-aligned for the same reasons. */ -#define DATA_ALIGNMENT(TYPE, ALIGN) \ - (TREE_CODE (TYPE) == ARRAY_TYPE \ - && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ - && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) - -/* This is BSD, so it wants DBX format. */ -#define DBX_DEBUGGING_INFO 1 - -/* Override parts of m68k.h */ - -#undef CALL_USED_REGISTERS -#define CALL_USED_REGISTERS \ - {1, 1, 0, 0, 0, 0, 0, 0, \ - 1, 1, 0, 0, 0, 0, 0, 1, \ - 1, 1, 0, 0, 0, 0, 1, 1 } - -#undef REG_ALLOC_ORDER -#define REG_ALLOC_ORDER \ -{ 0, 1, 2, 3, 4, 5, 6, 7,\ - 8, 9, 10, 11, 12, 13, 14, 15, \ - 16, 17, 22, 23, 18, 19, 20, 21 } - -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) \ - fprintf (FILE, "#NO_APP\n.globl fltused\n"); - -#undef ASM_OUTPUT_ALIGN -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ -{ int _LOG = LOG; \ - if (_LOG == 1) \ - fprintf (FILE, "\t.even\n"); \ - else if (_LOG == 2) \ - fprintf (FILE, "\t.align 4\n"); \ - else if (_LOG != 0) \ - fprintf (FILE, "\t.align %d\n", _LOG);\ -} - -/* crt0.c should use the vax-bsd style of entry, with a dummy arg. */ - -#define CRT0_DUMMIES bogus_fp, diff --git a/gcc/config/m68k/crds.h b/gcc/config/m68k/crds.h deleted file mode 100644 index 94172fa405e..00000000000 --- a/gcc/config/m68k/crds.h +++ /dev/null @@ -1,453 +0,0 @@ -/* Definitions of target machine for GNU compiler; - Charles River Data Systems UNiverse/32. - Copyright (C) 1987, 1993, 1994, 1996, 1997, 1998, 1999, 2000 - Free Software Foundation, Inc. - Contributed by Gary E. Miller (Gary_Edmunds_Miller@cup.portal.com) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#define MOTOROLA /* Use Motorola syntax rather than "MIT" */ -#define SGS /* Uses SGS assembler */ -#define SGS_SWITCH_TABLES /* Different switch table handling */ -#define SGS_NO_LI /* Suppress jump table label usage */ -#define CRDS /* Charles River Data Systems assembler */ - -#include "m68k/m68k.h" - -/* Without STRUCTURE_SIZE_BOUNDARY, we can't ensure that structures are - aligned such that we can correctly extract bitfields from them. - Someone should check whether the usual compiler on the crds machine - provides the equivalent behavior of STRUCTURE_SIZE_BOUNDARY. */ -/* Set to 16 because all other m68k targets have it so */ -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* See m68k.h. 0 means 680[01]0 with no 68881. */ - -#undef TARGET_DEFAULT -#define TARGET_DEFAULT 0 - -/* Don't try using XFmode. */ -#undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* special flags to the unos assembler. */ - -#undef ASM_SPEC -#define ASM_SPEC "-g" - -#undef LIB_SPEC -#define LIB_SPEC "%{!p:%{!pg:-lunos}}%{p:-lc_p}%{pg:-lc_p}" - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC \ - "%{pg:gcrt0.o%s}%{!pg:%{p:mc68rt0.o%s}%{!p:c68rt0.o%s}}" - -/* CC1 spec */ -#if 0 -/* c.sac only used in _s_call_r() in libunos.a and malloc() in libmalloc.a */ -/* so we do not need to bother ! */ -#define CC1_SPEC "-fpcc-struct-return" -#endif - -/* -O2 for MAX optimization */ -#undef CC1_SPEC -#define CC1_SPEC "%{O2:-fstrength-reduce}" - -/* Make output for SDB. */ - -/* #define SDB_DEBUGGING_INFO UNOS casm has no debugging :-( */ - -/* UNOS need stack probe :-( */ - -#if 0 -#define HAVE_probe 1 -#define gen_probe() gen_rtx_ASM_INPUT (VOIDmode, "tstb -2048(sp)\t;probe\n") -#else -#undef NEED_PROBE -#define NEED_PROBE (-2048) -#endif - -/* use memcpy, memset instead of bcopy, etc. */ - -#define TARGET_MEM_FUNCTIONS - -/* Define __HAVE_68881__ in preprocessor if -m68881 is specified. - This will control the use of inline 68881 insns in certain macros. */ - -#undef CPP_SPEC -#define CPP_SPEC "%{m68881:-D__HAVE_68881__}" - -/* Names to predefine in the preprocessor for this target machine. */ - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dmc68k -DM68000 -Dmc68000 -Dunos -Dunix -D__motorola__ -Asystem=unix -Acpu=m68k -Amachine=m68k" - -/* Register in which address to store a structure value - is passed to a function. */ -/* unos uses ".comm c.sac" returns &c.sac in d0 */ -/* make pointer to c.sac ? -#undef STRUCT_VALUE_REGNUM -#define STRUCT_VALUE gen_rtx_MEM (Pmode, gen_rtx( , , ) ) -*/ - -#define BSS_SECTION_ASM_OP "\t.bss" - -/* Specify how to pad function arguments. - Value should be `upward', `downward' or `none'. - Same as the default, except no padding for large or variable-size args. */ - -#define FUNCTION_ARG_PADDING(MODE, TYPE) \ - (((MODE) == BLKmode \ - ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ - && int_size_in_bytes (TYPE) < PARM_BOUNDARY / BITS_PER_UNIT) \ - : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY) \ - ? downward : none) - -/* Override parts of m68k.h to fit the CRuDS assembler. */ - -#undef TARGET_VERSION -#define TARGET_VERSION fprintf (stderr, " (68k, CRDS/UNOS)"); - -/* Specify extra dir to search for include files. */ -#define SYSTEM_INCLUDE_DIR "/include" - -/* Control the assembler format that we output. */ - -/* Output at beginning of assembler file. */ - -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) \ - fprintf (FILE, ";#NO_APP\n"); - -/* Output to assembler file text saying following lines - may contain character constants, extra white space, comments, etc. */ - -#undef ASM_APP_ON -#define ASM_APP_ON ";#APP\n" - -/* Output to assembler file text saying following lines - no longer contain unusual constructs. */ - -#undef ASM_APP_OFF -#define ASM_APP_OFF ";#NO_APP\n" - -/* The prefix for immediate operands. */ - -#undef IMMEDIATE_PREFIX -#define IMMEDIATE_PREFIX "$" - -/*unos has no .skip :-( */ -#undef ASM_OUTPUT_SKIP -#define ASM_OUTPUT_SKIP(FILE,SIZE) \ - fprintf (FILE, "\t. = . + %u\n", (int)(SIZE)); - -/* This says how to output an assembler line - to define a local common symbol. */ -/* should use bss_section instead of data_section but this makes casm die ? */ - -#undef ASM_OUTPUT_LOCAL -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -{ data_section (); \ - if ((SIZE) > 1) fprintf (FILE, "\t.even\n"); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), ":\t. = . + %u\n", (int)(ROUNDED));} - -/* This is how to output an insn to push a register on the stack. - It need not be very fast code. */ - -#undef ASM_OUTPUT_REG_PUSH -#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ - fprintf (FILE, "\tmovel %s,-(sp)\n", reg_names[REGNO]) - -/* This is how to output an insn to pop a register from the stack. - It need not be very fast code. */ - -#undef ASM_OUTPUT_REG_POP -#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ - fprintf (FILE, "\tmovel (sp)+,%s\n", reg_names[REGNO]) - -#undef ASM_OUTPUT_ASCII -#define ASM_OUTPUT_ASCII(FILE, P , SIZE) \ -do { size_t i, limit = (SIZE); \ - fprintf ((FILE), "\t.ascii \""); \ - for (i = 0; i < limit; i++) \ - { \ - register int c = (P)[i]; \ - if (i != 0 && (i / 200) * 200 == i) \ - fprintf ((FILE), "\"\n\t.ascii \""); \ - if (c >= ' ' && c < 0177) { \ - if (c != '\"' && c != '\\') { \ - putc (c, (FILE)); \ - continue; \ - } \ - } \ - /* brain dead asm doesn't understand char escapes */ \ - fprintf ((FILE), "\"\n\t.byte\t%d\n\t.ascii \"", c); \ - } \ - fprintf ((FILE), "\"\n"); \ - } while (0) - - -/* Change all JBxx to Bxx. Also change all DBRA to DBF. - Also change divs.l, etc., to divs, etc. But don't change divsl.l. */ - -#define ASM_OUTPUT_OPCODE(FILE, PTR) \ -{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ - { ++(PTR); } \ - else if ((PTR)[0] == 'd') \ - { \ - if (!strncmp ((PTR), "dbra", 4)) \ - { fprintf ((FILE), "dbf"); (PTR) += 4; } \ - else if (!strncmp ((PTR), "div", 3) && (PTR)[5] == ' ') \ - { fprintf ((FILE), "div%c", (PTR)[3]); (PTR) += 6; } \ - } \ -} - - -#if 0 -/* Print operand X (an rtx) in assembler syntax to file FILE. - CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. - For `%' followed by punctuation, CODE is the punctuation and X is null. - - On the 68000, we use several CODE characters: - '.' for dot needed in Motorola-style opcode names. - '-' for an operand pushing on the stack: - sp@-, -(sp) or -(%sp) depending on the style of syntax. - '+' for an operand pushing on the stack: - sp@+, (sp)+ or (%sp)+ depending on the style of syntax. - '@' for a reference to the top word on the stack: - sp@, (sp) or (%sp) depending on the style of syntax. - '#' for an immediate operand prefix (# in MIT and Motorola syntax - but & in SGS syntax, $ in unos syntax). - '!' for the fpcr register (used in some float-to-fixed conversions). - - 'b' for byte insn (no effect, on the Sun; this is for the ISI). - 'd' to force memory addressing to be absolute, not relative. - 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) - 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather - than directly). Second part of 'y' below. - 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), - or print pair of registers as rx:ry. - 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs - CONST_DOUBLE's as SunFPA constant RAM registers if - possible, so it should not be used except for the SunFPA. */ - -#undef PRINT_OPERAND_PUNCT_VALID_P -#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ - ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ - || (CODE) == '+' || (CODE) == '@' || (CODE) == '!') - -#undef PRINT_OPERAND -#define PRINT_OPERAND(FILE, X, CODE) \ -{ int i; \ - if (CODE == '.') ; \ - else if (CODE == '#') fprintf (FILE, "$"); \ - else if (CODE == '-') fprintf (FILE, "-(sp)"); \ - else if (CODE == '+') fprintf (FILE, "(sp)+"); \ - else if (CODE == '@') fprintf (FILE, "(sp)"); \ - else if (CODE == '!') fprintf (FILE, "fpcr"); \ - else if (CODE == '/') \ - ; \ - else if (GET_CODE (X) == REG) \ - { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode) \ - fprintf (FILE, "%s:%s", reg_names[REGNO (X)], reg_names[REGNO (X)+1]); \ - else \ - fprintf (FILE, "%s", reg_names[REGNO (X)]); \ - } \ - else if (GET_CODE (X) == MEM) \ - { \ - output_address (XEXP (X, 0)); \ - if (CODE == 'd' && ! TARGET_68020 \ - && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ - /* fprintf (FILE, ".l") */; \ - } \ - else if ((CODE == 'y' || CODE == 'w') \ - && GET_CODE(X) == CONST_DOUBLE \ - && (i = standard_sun_fpa_constant_p (X))) \ - fprintf (FILE, "%%%d", i & 0x1ff); \ - else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ - { REAL_VALUE_TYPE r; long l; \ - REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ - if (CODE == 'f') \ - ASM_OUTPUT_FLOAT_OPERAND (CODE, FILE, r); \ - else \ - { REAL_VALUE_TO_TARGET_SINGLE (r, l); \ - fprintf (FILE, "$0x%lx", l); } } \ - else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode) \ - { REAL_VALUE_TYPE r; \ - REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ - ASM_OUTPUT_DOUBLE_OPERAND (FILE, r); } \ - else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode) \ - { REAL_VALUE_TYPE r; \ - REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ - ASM_OUTPUT_LONG_DOUBLE_OPERAND (FILE, r); } \ - else { putc ('$', FILE); output_addr_const (FILE, X); }} -#endif - -/* Note that this contains a kludge that knows that the only reason - we have an address (plus (label_ref...) (reg...)) - is in the insn before a tablejump, and we know that m68k.md - generates a label LInnn: on such an insn. */ -#undef PRINT_OPERAND_ADDRESS -#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -{ register rtx reg1, reg2, breg, ireg; \ - register rtx addr = ADDR; \ - rtx offset; \ - switch (GET_CODE (addr)) \ - { \ - case REG: \ - fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \ - break; \ - case PRE_DEC: \ - fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \ - break; \ - case POST_INC: \ - fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \ - break; \ - case PLUS: \ - reg1 = 0; reg2 = 0; \ - ireg = 0; breg = 0; \ - offset = 0; \ - if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ - { \ - offset = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ - { \ - offset = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - if (GET_CODE (addr) != PLUS) ; \ - else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ - { \ - reg1 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ - { \ - reg1 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - else if (GET_CODE (XEXP (addr, 0)) == MULT) \ - { \ - reg1 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == MULT) \ - { \ - reg1 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - else if (GET_CODE (XEXP (addr, 0)) == REG) \ - { \ - reg1 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == REG) \ - { \ - reg1 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ - || GET_CODE (addr) == SIGN_EXTEND) \ - { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ - if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ - if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ - || GET_CODE (reg1) == MULT)) \ - || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ - { breg = reg2; ireg = reg1; } \ - else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ - { breg = reg1; ireg = reg2; } \ - if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ - { int scale = 1; \ - if (GET_CODE (ireg) == MULT) \ - { scale = INTVAL (XEXP (ireg, 1)); \ - ireg = XEXP (ireg, 0); } \ - if (GET_CODE (ireg) == SIGN_EXTEND) \ - fprintf (FILE, "L%d-LI%d-2(pc,%s.w", \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - reg_names[REGNO (XEXP (ireg, 0))]); \ - else \ - fprintf (FILE, "L%d-LI%d-2(pc,%s.l", \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - reg_names[REGNO (ireg)]); \ - if (scale != 1) fprintf (FILE, ":%d", scale); \ - putc (')', FILE); \ - break; } \ - if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \ - { fprintf (FILE, "L%d-LI%d-2(pc,%s.l", \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - reg_names[REGNO (breg)]); \ - putc (')', FILE); \ - break; } \ - if (ireg != 0 || breg != 0) \ - { int scale = 1; \ - if (breg == 0) \ - abort (); \ - if (addr && GET_CODE (addr) == LABEL_REF) abort (); \ - if (addr != 0) \ - output_addr_const (FILE, addr); \ - fprintf (FILE, "(%s", reg_names[REGNO (breg)]); \ - if (breg != 0 && ireg != 0) \ - putc (',', FILE); \ - if (ireg != 0 && GET_CODE (ireg) == MULT) \ - { scale = INTVAL (XEXP (ireg, 1)); \ - ireg = XEXP (ireg, 0); } \ - if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ - fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \ - else if (ireg != 0) \ - fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \ - if (scale != 1) fprintf (FILE, ":%d", scale); \ - putc (')', FILE); \ - break; \ - } \ - else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ - { fprintf (FILE, "L%d-LI%d-2(pc,%s.l)", \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - CODE_LABEL_NUMBER (XEXP (addr, 0)), \ - reg_names[REGNO (reg1)]); \ - break; } \ - default: \ - if (GET_CODE (addr) == CONST_INT \ - && INTVAL (addr) < 0x8000 \ - && INTVAL (addr) >= -0x8000) \ - fprintf (FILE, "%d", INTVAL (addr)); \ - else \ - output_addr_const (FILE, addr); \ - }} - -#define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \ - do { fprintf (FILE, "\t; file\t"); \ - output_quoted_string (FILE, FILENAME); \ - fprintf (FILE, "\n"); \ - } while (0) - -#define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO) \ - fprintf (FILE, "\t; ln\t%d\n", \ - (sdb_begin_function_line \ - ? (LINENO) - sdb_begin_function_line : 1)) - -/* Must put address in %a0 , not %d0 . -- LGM, 7/15/88 */ -/* UNOS ?? */ -#undef FUNCTION_PROFILER -#define FUNCTION_PROFILER(FILE, LABEL_NO) \ - fprintf (FILE, "\tmovl &LP%%%d,%%a0\n\tjsr mcount\n", (LABEL_NO)) diff --git a/gcc/config/m68k/hp2bsd.h b/gcc/config/m68k/hp2bsd.h deleted file mode 100644 index 5e4501b83c4..00000000000 --- a/gcc/config/m68k/hp2bsd.h +++ /dev/null @@ -1,78 +0,0 @@ -/* Definitions of target machine for GNU compiler. HP 9000/200 68000 version. - Copyright (C) 1987, 1991 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#include "m68k/m68k.h" - -/* See m68k.h. 0 means 68000 with no 68881. */ - -#define TARGET_DEFAULT 0 - -/* Don't try using XFmode. */ -#undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* Define __HAVE_68881 in preprocessor only if -m68881 is specified. - This will control the use of inline 68881 insns in certain macros. - Also inform the program which CPU this is for. */ - -#define CPP_SPEC "%{m68881:-D__HAVE_68881__} \ -%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}" - -/* -m68020 requires special flags to the assembler. */ - -#define ASM_SPEC \ - "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!m68020:-mc68010}}" - -/* Names to predefine in the preprocessor for this target machine. */ - -#define CPP_PREDEFINES "-Dmc68000 -Dmc68010 -Dhp200 -Dunix -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k" - -/* Link with libg.a when debugging, for dbx's sake. */ - -#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} " - -/* Alignment of field after `int : 0' in a structure. */ - -#undef EMPTY_FIELD_BOUNDARY -#define EMPTY_FIELD_BOUNDARY 16 - -/* Every structure or union's size must be a multiple of 2 bytes. */ - -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* This is BSD, so it wants DBX format. */ - -#define DBX_DEBUGGING_INFO 1 - -/* Define subroutines to call to handle multiply, divide, and remainder. - These routines are built into the c-library on the hp200. - XXX What other routines from the c-library could we use? - The `*' prevents an underscore from being prepended by the compiler. */ - -#define DIVSI3_LIBCALL "*ldiv" -#define UDIVSI3_LIBCALL "*uldiv" -#define MODSI3_LIBCALL "*lrem" -#define UMODSI3_LIBCALL "*ulrem" -#define MULSI3_LIBCALL "*lmul" -#define UMULSI3_LIBCALL "*ulmul" - -/* Don't default to pcc-struct-return, because gcc is the only compiler, and - we want to retain compatibility with older gcc versions. */ -#define DEFAULT_PCC_STRUCT_RETURN 0 diff --git a/gcc/config/m68k/hp3bsd.h b/gcc/config/m68k/hp3bsd.h deleted file mode 100644 index 23cc9c71b20..00000000000 --- a/gcc/config/m68k/hp3bsd.h +++ /dev/null @@ -1,44 +0,0 @@ -#include "m68k/m68k.h" - -/* See m68k.h. 7 means 68020 with 68881. */ - -#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020) - -/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified. - This will control the use of inline 68881 insns in certain macros. */ - -#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ -D__HAVE_FPU__}" - -/* Names to predefine in the preprocessor for this target machine. */ - -#define CPP_PREDEFINES "-Dmc68000 -Dmc68020 -Dhp300 -Dhp9000 -Dunix -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k" - -/* Link with libg.a when debugging, for dbx's sake. */ - -#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} " - -/* Every structure or union's size must be a multiple of 2 bytes. */ - -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* This is BSD, so it wants DBX format. */ - -#define DBX_DEBUGGING_INFO 1 - -/* Do not break .stabs pseudos into continuations. */ - -#define DBX_CONTIN_LENGTH 0 - -/* This is the char to use for continuation (in case we need to turn - continuation back on). */ - -#define DBX_CONTIN_CHAR '?' - -/* Don't use the `xsfoo;' construct in DBX output; this system - doesn't support it. */ - -#define DBX_NO_XREFS - -/* Don't default to pcc-struct-return, because gcc is the only compiler, and - we want to retain compatibility with older gcc versions. */ -#define DEFAULT_PCC_STRUCT_RETURN 0 diff --git a/gcc/config/m68k/hp3bsd44.h b/gcc/config/m68k/hp3bsd44.h deleted file mode 100644 index 780a639efa5..00000000000 --- a/gcc/config/m68k/hp3bsd44.h +++ /dev/null @@ -1,53 +0,0 @@ -#include "m68k/m68k.h" - -/* See m68k.h. 7 means 68020 with 68881. */ - -#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020) - -/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified. - This will control the use of inline 68881 insns in certain macros. */ - -#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ -D__HAVE_FPU__}" - -/* Names to predefine in the preprocessor for this target machine. */ - -#define CPP_PREDEFINES "-Dmc68000 -Dmc68020 -Dhp300 -Dhp9000 -Dunix -D__BSD_4_4__ -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k" - -/* No more libg.a */ - -#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" - -/* Make gcc agree with <machine/ansi.h> */ - -#define SIZE_TYPE "unsigned int" -#define PTRDIFF_TYPE "int" -#undef WCHAR_TYPE -#define WCHAR_TYPE "short unsigned int" -#undef WCHAR_TYPE_SIZE -#define WCHAR_TYPE_SIZE 16 - -/* Every structure or union's size must be a multiple of 2 bytes. */ - -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* This is BSD, so it wants DBX format. */ - -#define DBX_DEBUGGING_INFO 1 - -/* Do not break .stabs pseudos into continuations. */ - -#define DBX_CONTIN_LENGTH 0 - -/* This is the char to use for continuation (in case we need to turn - continuation back on). */ - -#define DBX_CONTIN_CHAR '?' - -/* Don't use the `xsfoo;' construct in DBX output; this system - doesn't support it. */ - -#define DBX_NO_XREFS - -/* Don't default to pcc-struct-return, because gcc is the only compiler, and - we want to retain compatibility with older gcc versions. */ -#define DEFAULT_PCC_STRUCT_RETURN 0 diff --git a/gcc/config/m68k/linux-aout.h b/gcc/config/m68k/linux-aout.h deleted file mode 100644 index 2be6da806a2..00000000000 --- a/gcc/config/m68k/linux-aout.h +++ /dev/null @@ -1,75 +0,0 @@ -/* Definitions for Motorola m68k running Linux-based GNU systems. - Copyright (C) 1995, 1996, 1997, 2002 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#include <m68k/m68k.h> -#include <linux-aout.h> - -/* 68020 with 68881 */ -#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020) - -#define DBX_DEBUGGING_INFO 1 - -#define ASM_COMMENT_START "|" - -#define CPP_PREDEFINES \ - "-Dunix -Dmc68000 -Dmc68020 -D__gnu_linux__ -Dlinux -Asystem=unix -Asystem=posix -Acpu=m68k -Amachine=m68k" - -#undef CPP_SPEC -#if TARGET_DEFAULT & MASK_68881 -#define CPP_SPEC \ - "%{!msoft-float:-D__HAVE_68881__} %{posix:-D_POSIX_SOURCE}" -#else -#define CPP_SPEC \ - "%{m68881:-D__HAVE_68881__} %{posix:-D_POSIX_SOURCE}" -#endif - -#undef SUBTARGET_SWITCHES -#define SUBTARGET_SWITCHES {"ieee-fp", 0, \ - N_("Use IEEE math for fp comparisons") }, - -#undef ASM_SPEC -#define ASM_SPEC \ - "%{m68030} %{m68040} %{fpic:-k} %{fPIC:-k}" - -#undef LIB_SPEC -#if 1 -/* We no longer link with libc_p.a or libg.a by default. If you want - to profile or debug the GNU/Linux C library, please add -lc_p or -ggdb - to LDFLAGS at the link time, respectively. */ -#define LIB_SPEC \ - "%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}" -#else -#define LIB_SPEC \ - "%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} %{!p:%{!pg:%{!g*:-lc} %{g*:-lg}}}" -#endif - -/* We want to pass -v to linker */ -#undef LINK_SPEC -#define LINK_SPEC "-m m68klinux %{v:-dll-verbose}" - -#define SIZE_TYPE "unsigned int" -#define PTRDIFF_TYPE "int" - -/* Generate calls to memcpy, memcmp and memset. */ -#define TARGET_MEM_FUNCTIONS - -/* Don't default to pcc-struct-return, because gcc is the only compiler. */ -#undef PCC_STATIC_STRUCT_RETURN -#define DEFAULT_PCC_STRUCT_RETURN 0 diff --git a/gcc/config/m68k/m68k-psos.h b/gcc/config/m68k/m68k-psos.h deleted file mode 100644 index 14f7f68c33f..00000000000 --- a/gcc/config/m68k/m68k-psos.h +++ /dev/null @@ -1,67 +0,0 @@ -/* Definitions of a target machine for the GNU compiler: - 68040 running pSOS, ELF object files, DBX debugging. - Copyright (C) 1996 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - - -/* Use MOTOROLA assembler syntax, as gas is configured that way and - glibc also seems to use it. Must come BEFORE m68k.h! */ - -#define MOTOROLA - -/* Get generic m68k definitions. */ - -#include "m68k/m68k.h" -#include "m68k/m68kemb.h" - -/* Default processor type is a (pure) 68040 with 68881 emulation using - the floating-point support package. */ - -#undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_68040_ONLY|MASK_BITFIELD|MASK_68881|MASK_68020) - -/* Options passed to CPP, GAS, CC1 and CC1PLUS. We override - m68k-none.h for consistency with TARGET_DEFAULT. */ - -#undef CPP_SPEC -#define CPP_SPEC \ -"%{!mc68000:%{!m68000:%{!m68332:%{!msoft-float:-D__HAVE_68881__ }}}}\ -%{!ansi:-Dmc68000 %{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68302:-Dmc68302 }%{m68332:-Dmc68332 }%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-Dmc68040 }}}}}}}}}}}\ --D__mc68000__ -D__mc68000 %{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68302:-D__mc68302__ -D__mc68302 }%{m68332:-D__mc68332__ -D__mc68332 }%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-D__mc68040__ -D__mc68040 }}}}}}}}}}" - -#undef ASM_SPEC -#define ASM_SPEC \ -"%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881 }\ -%{m68000}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040}%{m68302}%{m68332}%{!m68000:%{!mc68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-mc68040}}}}}}}}}}" - -#undef CC1_SPEC -#define CC1_SPEC \ - "%{m68000:%{!m68881:-msoft-float }}%{m68302:-m68000}%{m68332:-m68020 -mnobitfield %{!m68881:-msoft-float}}%{!m68000:%{!mc68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-m68040}}}}}}}}}}" - -#undef CC1PLUS_SPEC -#define CC1PLUS_SPEC \ - "%{m68000:%{!m68881:-msoft-float }}%{m68302:-m68000}%{m68332:-m68020 -mnobitfield %{!m68881:-msoft-float}}%{!m68000:%{!mc68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-m68040}}}}}}}}}}" - - -/* Get processor-independent pSOS definitions. */ - -#include "psos.h" - - -/* end of m68k-psos.h */ diff --git a/gcc/config/m68k/mot3300.h b/gcc/config/m68k/mot3300.h deleted file mode 100644 index c599cc514dd..00000000000 --- a/gcc/config/m68k/mot3300.h +++ /dev/null @@ -1,680 +0,0 @@ -/* Definitions of target machine for GNU compiler, - SysV68 Motorola 3300 Delta Series. - Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2002 - Free Software Foundation, Inc. - Contributed by Abramo and Roberto Bagnara (bagnara@dipisa.di.unipi.it) - based on Alex Crain's 3B1 definitions. - Maintained by Philippe De Muyter (phdm@info.ucl.ac.be). - Support for GAS added by merging mot3300g.h into this file by - Manfred Hollstein (manfred@lts.sel.alcatel.de). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifndef USE_GAS -#define MOTOROLA /* Use Motorola syntax rather than "MIT" */ -#define MOTOROLA_BSR /* Use Span-dependent optimized bsr */ -#define SGS /* Uses SGS assembler */ -#define SGS_CMP_ORDER /* Takes cmp operands in reverse order */ -#define SGS_SWAP_W /* Use swap.w rather than just plain swap */ -#endif /* USE_GAS */ - -#define NO_DOLLAR_IN_LABEL -#define NO_DOT_IN_LABEL - -#include "m68k/m68k.h" - -/* GDB expects a slightly different marker on this target. */ -#define STABS_GCC_MARKER "gcc2_compiled%" - -/* See m68k.h. 0407 means 68020-68040. */ - -#ifndef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_68040|MASK_BITFIELD|MASK_68881|MASK_68020) -#endif - -/* -m[c]6800 requires special flag to the assembler. */ - -#undef ASM_SPEC -#ifndef USE_GAS -#define ASM_SPEC "%{m68000:-p 000}%{mc68000:-p 000}" -#else /* USE_GAS */ -#define ASM_SPEC \ - "%{v:-v} %{m68000:-mc68000}%{mc68000:-mc68000}%{!mc68000:%{!m68000:-mc68020}}" -#endif /* USE_GAS */ - -/* NYI: FP= is equivalent to -msoft-float */ - -/* We use /lib/libp/lib* when profiling. */ - -/* NYI: if FP=M68881U library is -lc881u */ -/* NYI: if FP= library is -lc. */ -/* Default for us: FP=M68881 library is -lc881 */ -#undef LIB_SPEC -#define LIB_SPEC "%{!shlib:%{!msoft-float:-lc881}%{msoft-float:-lc}}" -#ifdef CROSS_COMPILE -#ifndef USE_GLD -#define DEFAULT_A_OUT_NAME "m68ka.out" -#endif -#endif - -#ifdef USE_GLD -#undef LINK_SPEC -#define LINK_SPEC "%{v:-v}" -#endif /* defined (USE_GLD) */ - -#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}\ -%{!mc68000:%{!m68000: -D__mc68020__}}" - -/* Shared libraries need to use crt0s.o */ - -#undef STARTFILE_SPEC -#ifdef CROSS_COMPILE -#define STARTFILE_SPEC \ - "%{!shlib:%{pg:mcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}\ - %{shlib:crt0s.o%s shlib.ifile%s} %{p:-L"TOOLDIR_BASE_PREFIX DEFAULT_TARGET_MACHINE"/lib/libp} %{pg:-L"TOOLDIR_BASE_PREFIX DEFAULT_TARGET_MACHINE"/lib/libp} " -#else /* CROSS_COMPILE */ -#define STARTFILE_SPEC \ - "%{!shlib:%{pg:mcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}\ - %{shlib:crt0s.o%s shlib.ifile%s} %{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp} " -#endif /* CROSS_COMPILE */ - -/* Generate calls to memcpy, memcmp and memset. */ - -#define TARGET_MEM_FUNCTIONS - -/* size_t is unsigned int. */ - -#define SIZE_TYPE "unsigned int" - -/* We need POSIX/XOPEN symbols; otherwise building libio will fail. */ -#define ADD_MISSING_POSIX 1 -#define ADD_MISSING_XOPEN 1 - -/* Every structure or union's size must be a multiple of 2 bytes. */ - -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* Follow sysV68 cc regarding alignment imposed by char:0; */ - -#define PCC_BITFIELD_TYPE_MATTERS 1 - -/* Allocation boundary (in *bits*) for storing arguments in argument list. */ -/* Be compatible with native compiler. */ -#undef PARM_BOUNDARY -#define PARM_BOUNDARY 16 - -/* Make output for SDB. */ - -#define SDB_DEBUGGING_INFO 1 - -#undef REGISTER_PREFIX -#define REGISTER_PREFIX "%" - -#undef LOCAL_LABEL_PREFIX -#ifdef USE_GAS -#define LOCAL_LABEL_PREFIX ".L" -#else -#define LOCAL_LABEL_PREFIX "L%" -#endif - -#undef USER_LABEL_PREFIX - -#undef IMMEDIATE_PREFIX -#define IMMEDIATE_PREFIX "&" - -#undef REGISTER_NAMES -#define REGISTER_NAMES \ -{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ - "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", \ - "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"} - -#undef FUNCTION_EXTRA_EPILOGUE -#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) \ -{ if (current_function_returns_pointer \ - && ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode)) \ - asm_fprintf (FILE, "\tmov.l %Ra0,%Rd0\n"); } - -#undef FUNCTION_PROFILER -#define FUNCTION_PROFILER(FILE, LABEL_NO) \ - asm_fprintf (FILE, "\tmov.l %I%LLP%d,%Ra0\n\tjsr mcount%%\n", (LABEL_NO)) - -/* This is how to output an insn to push a register on the stack. - It need not be very fast code. */ - -#undef ASM_OUTPUT_REG_PUSH -#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ - fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[REGNO]) - -/* This is how to output an insn to pop a register from the stack. - It need not be very fast code. */ - -#undef ASM_OUTPUT_REG_POP -#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ - fprintf (FILE, "\tmov.l (%%sp)+,%s\n", reg_names[REGNO]) - -#ifndef USE_GAS - -#undef ASM_APP_ON -#define ASM_APP_ON "" - -#undef ASM_APP_OFF -#define ASM_APP_OFF "" - -#undef TEXT_SECTION_ASM_OP -#define TEXT_SECTION_ASM_OP "\ttext" -#undef DATA_SECTION_ASM_OP -#define DATA_SECTION_ASM_OP "\tdata" -#undef ASCII_DATA_ASM_OP -#define ASCII_DATA_ASM_OP "\tbyte\t" - -#undef SET_ASM_OP -#define SET_ASM_OP "\tset\t" - -#endif /* USE_GAS */ - -#ifdef USE_GLD -/* Support the ctors and dtors sections for g++. */ - -#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"x\"" -#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"x\"" -#endif /* defined (USE_GLD) */ - -/* The file command should always begin the output. */ - -#undef ASM_FILE_START -#ifndef USE_GAS -#define ASM_FILE_START(FILE) \ - output_file_directive ((FILE), main_input_filename) -#else /* USE_GAS */ -#define ASM_FILE_START(FILE) \ - { \ - fprintf (FILE, "%s", ASM_APP_OFF); \ - output_file_directive ((FILE), main_input_filename); \ - } -#endif /* USE_GAS */ - -/* Names to predefine in the preprocessor for this target machine. */ -/* ihnp4!lmayk!lgm@eddie.mit.edu says mc68000 and m68k should not be here, - on the other hand I don't care what he says. */ - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dm68k -Dunix -DsysV68 -D__motorola__ -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k" - -#undef TARGET_VERSION -#ifndef USE_GAS -#define TARGET_VERSION fprintf (stderr, " (68k, SGS/AT&T sysV68 syntax)"); -#endif /* USE_GAS */ - -/* This will return small structs in d0. */ -#define RETURN_IN_MEMORY(type) \ - ((TYPE_MODE (type) == BLKmode) \ - || (AGGREGATE_TYPE_P (type) \ - && GET_MODE_SIZE (TYPE_MODE (type)) > UNITS_PER_WORD)) - -/* Don't default to pcc-struct-return, because we have already specified - exactly how to return structures in the RETURN_IN_MEMORY macro. */ -#define DEFAULT_PCC_STRUCT_RETURN 0 - -/* If TARGET_68881, return SF and DF values in fp0 instead of d0. */ -/* NYI: If FP=M68881U return SF and DF values in d0. */ -/* NYI: If -mold return pointer in a0 and d0 */ - -#undef FUNCTION_VALUE -/* sysV68 (brain damaged) cc convention support. */ -#define FUNCTION_VALUE(VALTYPE,FUNC) \ - (TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_68881 \ - ? gen_rtx_REG (TYPE_MODE (VALTYPE), 16) \ - : (POINTER_TYPE_P (VALTYPE) \ - ? gen_rtx_REG (TYPE_MODE (VALTYPE), 8) \ - : gen_rtx_REG (TYPE_MODE (VALTYPE), 0))) - -/* If TARGET_68881, SF and DF values are returned in fp0 instead of d0. */ - -/* Is LIBCALL_VALUE never called with a pointer ? */ -#undef LIBCALL_VALUE -#define LIBCALL_VALUE(MODE) \ - gen_rtx_REG ((MODE), \ - ((TARGET_68881 \ - && ((MODE) == SFmode || (MODE) == DFmode \ - || (MODE) == XFmode)) \ - ? 16 : 0)) - -/* 1 if N is a possible register number for a function value. - d0 may be used, and fp0 as well if -msoft-float is not specified. */ - -#undef FUNCTION_VALUE_REGNO_P -/* sysV68 (brain damaged) cc convention support. */ -#define FUNCTION_VALUE_REGNO_P(N) \ - ((N) == 0 || (N) == 8 || (TARGET_68881 && (N) == 16)) - -/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for - more than one register. */ - -#undef NEEDS_UNTYPED_CALL -#define NEEDS_UNTYPED_CALL 1 - -#ifndef USE_GAS -/* This is the command to make the user-level label named NAME - defined for reference from other files. */ - -#undef GLOBAL_ASM_OP -#define GLOBAL_ASM_OP "\tglobal\t" -#endif /* USE_GAS */ - -#define ASM_PN_FORMAT "%s_%%%lu" - -#undef INT_OP_GROUP -#ifdef USE_GAS -#define INT_OP_GROUP INT_OP_STANDARD -#else -#define INT_OP_GROUP INT_OP_NO_DOT -#endif - -/* This is how to output an assembler line - that says to advance the location counter - to a multiple of 2**LOG bytes. */ - -#ifndef USE_GAS -#define ALIGN_ASM_OP "\teven" -#else /* USE_GAS */ -#define ALIGN_ASM_OP "\t.even" -#endif /* USE_GAS */ - -#undef ASM_OUTPUT_ALIGN -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ - if ((LOG) >= 1) \ - fprintf (FILE, "%s\n", ALIGN_ASM_OP); - -#ifndef USE_GAS -#define SKIP_ASM_OP "\tspace\t" -#else /* USE_GAS */ -#define SKIP_ASM_OP "\t.skip\t" -#endif /* USE_GAS */ - -#undef ASM_OUTPUT_SKIP -#define ASM_OUTPUT_SKIP(FILE,SIZE) \ - fprintf (FILE, "%s%u\n", SKIP_ASM_OP, (int)(SIZE)) - -/* Can't use ASM_OUTPUT_SKIP in text section. */ - -#define ASM_NO_SKIP_IN_TEXT 1 - -/* The beginnings of sdb support... */ - -/* Undefining these will allow `output_file_directive' (in toplev.c) - to default to the right thing. */ -#undef ASM_OUTPUT_MAIN_SOURCE_FILENAME -#ifndef USE_GAS -#define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \ - do { fprintf (FILE, "\tfile\t"); \ - output_quoted_string (FILE, FILENAME); \ - fprintf (FILE, "\n"); \ - } while (0) - -#undef ASM_OUTPUT_SOURCE_LINE -#define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO) \ - fprintf (FILE, "\tln\t%d\n", \ - (sdb_begin_function_line \ - ? (LINENO) - sdb_begin_function_line : 1)) - -/* Yet another null terminated string format. */ - -#undef ASM_OUTPUT_ASCII -#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ - do { register size_t sp = 0, lp = 0, limit = (LEN); \ - fputs (integer_asm_op (1, TRUE), (FILE)); \ - loop: \ - if ((PTR)[sp] > ' ' && ! ((PTR)[sp] & 0x80) && (PTR)[sp] != '\\') \ - { lp += 3; \ - fprintf ((FILE), "'%c", (PTR)[sp]); } \ - else \ - { lp += 5; \ - fprintf ((FILE), "0x%x", (PTR)[sp]); } \ - if (++sp < limit) \ - { if (lp > 60) \ - { lp = 0; \ - fprintf ((FILE), "\n%s", ASCII_DATA_ASM_OP); } \ - else \ - putc (',', (FILE)); \ - goto loop; } \ - putc ('\n', (FILE)); } while (0) -#endif /* USE_GAS */ - -#ifndef USE_GAS -/* Output a float value (represented as a C double) as an immediate operand. - This macro is a 68k-specific macro. */ - -#undef ASM_OUTPUT_FLOAT_OPERAND -#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ - do { long l; \ - REAL_VALUE_TO_TARGET_SINGLE (r, l); \ - /* Use hex representation even if CODE is f. as needs it. */ \ - fprintf ((FILE), "&0x%lx", l); \ - } while (0) - -/* Output a double value (represented as a C double) as an immediate operand. - This macro is a 68k-specific macro. */ -#undef ASM_OUTPUT_DOUBLE_OPERAND -#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ - do { long l[2]; \ - REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ - fprintf ((FILE), "&0x%lx%08lx", l[0], l[1]); \ - } while (0) -#endif /* USE_GAS */ - -/* This is how to store into the string LABEL - the symbol_ref name of an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. - This is suitable for output with `assemble_name'. */ - -#undef ASM_GENERATE_INTERNAL_LABEL -#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ - sprintf ((LABEL), "%s%s%ld", LOCAL_LABEL_PREFIX, (PREFIX), (long)(NUM)) - -/* The prefix to add to user-visible assembler symbols. */ - -#undef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "" - -/* This is how to output an element of a case-vector that is absolute. - (The 68000 does not use such vectors, - but we must define this macro anyway.) */ -/* The L after the local prefix is the "L" prefix for the normal labels - generated by gcc; why are ASM_OUTPUT_ADDR_VEC_ELT and - ASM_OUTPUT_ADDR_DIFF_ELT not called with a PREFIX parameter, like - (*targetm.asm_out.internal_label) ? */ - -#undef ASM_OUTPUT_ADDR_VEC_ELT -#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ - asm_fprintf (FILE, "%s%LL%d\n", integer_asm_op (4, TRUE), (VALUE)) - -/* This is how to output an element of a case-vector that is relative. */ - -#undef ASM_OUTPUT_ADDR_DIFF_ELT -#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ - asm_fprintf (FILE, "\t%s %LL%d-%LL%d\n", \ - integer_asm_op (2, TRUE), (VALUE), (REL)) - -#ifndef USE_GAS - -#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \ - asm_fprintf (FILE, "\tswbeg &%d\n%L%s%d:\n", \ - XVECLEN (PATTERN (TABLE), 1), (PREFIX), (NUM)) - -/* sysV68 as cannot handle LD%n(%pc,%reg) */ -#define SGS_NO_LI - -/* labelno is not used here */ -#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\ - asm_fprintf (file, "12(%Rpc,%s.", regname) - -#define ASM_RETURN_CASE_JUMP \ - do { \ - if (TARGET_5200) \ - { \ - if (ADDRESS_REG_P (operands[0])) \ - return "jmp 8(%%pc,%0.l)"; \ - else \ - return "ext%.l %0\n\tjmp 8(%%pc,%0.l)"; \ - } \ - else \ - return "jmp 8(%%pc,%0.w)"; \ - } while (0) - -#else /* USE_GAS */ - -/* labelno is not used here */ -#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\ - asm_fprintf (file, "%Rpc@(6,%s:", regname) - -#define ASM_RETURN_CASE_JUMP return "jmp %%pc@(2,%0:w)" - -#endif /* USE_GAS */ - -#ifndef USE_GAS - -/* Translate some opcodes to fit the sysV68 assembler syntax. */ -/* The opcodes fdmov and fsmov are guesses. */ - -/* cliffm@netcom.com says no need for .w suffix on jumps. */ -#undef ASM_OUTPUT_OPCODE -#define ASM_OUTPUT_OPCODE(FILE, PTR) \ -{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ - { ++(PTR); \ - while (*(PTR) != ' ') \ - { putc (*(PTR), (FILE)); ++(PTR); } \ - } \ - else if ((PTR)[0] == 's') \ - { \ - if (!strncmp ((PTR), "swap", 4)) \ - { fprintf ((FILE), "swap.w"); (PTR) += 4; } \ - } \ - else if ((PTR)[0] == 'f') \ - { \ - if (!strncmp ((PTR), "fmove", 5)) \ - { fprintf ((FILE), "fmov"); (PTR) += 5; } \ - else if (!strncmp ((PTR), "f%$move", 7)) \ - { if (TARGET_68040_ONLY) \ - { fprintf ((FILE), "fsmov"); (PTR) += 7; } \ - else \ - { fprintf ((FILE), "fmov"); (PTR) += 7; } } \ - else if (!strncmp ((PTR), "f%&move", 7)) \ - { if (TARGET_68040_ONLY) \ - { fprintf ((FILE), "fdmov"); (PTR) += 7; } \ - else \ - { fprintf ((FILE), "fmov"); (PTR) += 7; } } \ - else if (!strncmp ((PTR), "ftst", 4)) \ - { fprintf ((FILE), "ftest"); (PTR) += 4; } \ - else if (!strncmp ((PTR), "fbne", 4)) \ - { fprintf ((FILE), "fbneq"); (PTR) += 4; } \ - else if (!strncmp ((PTR), "fsne", 4)) \ - { fprintf ((FILE), "fsneq"); (PTR) += 4; } \ - } \ -/* MOVE, MOVEA, MOVEQ, MOVEC ==> MOV */ \ - else if ((PTR)[0] == 'm' && (PTR)[1] == 'o' \ - && (PTR)[2] == 'v' && (PTR)[3] == 'e') \ - { fprintf ((FILE), "mov"); (PTR) += 4; \ - if ((PTR)[0] == 'q' || (PTR)[0] == 'a' \ - || (PTR)[0] == 'c') (PTR)++; } \ -/* SUB, SUBQ, SUBA, SUBI ==> SUB */ \ - else if ((PTR)[0] == 's' && (PTR)[1] == 'u' \ - && (PTR)[2] == 'b') \ - { fprintf ((FILE), "sub"); (PTR) += 3; \ - if ((PTR)[0] == 'q' || (PTR)[0] == 'i' \ - || (PTR)[0] == 'a') (PTR)++; } \ -/* CMP, CMPA, CMPI, CMPM ==> CMP */ \ - else if ((PTR)[0] == 'c' && (PTR)[1] == 'm' \ - && (PTR)[2] == 'p') \ - { fprintf ((FILE), "cmp"); (PTR) += 3; \ - if ((PTR)[0] == 'a' || (PTR)[0] == 'i' \ - || (PTR)[0] == 'm') (PTR)++; } \ -} -#endif /* USE_GAS */ - -/* phdm@info.ucl.ac.be says to pass SIZE, not ROUNDED. */ - -/* This says how to output an assembler line - to define a global common symbol. */ - -#undef ASM_OUTPUT_COMMON -#ifndef USE_GAS -#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -( fputs ("\tcomm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%u\n", (SIZE))) -#else /* USE_GAS */ -#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -( fputs ("\t.comm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%u\n", (SIZE))) -#endif /* USE_GAS */ - -/* This says how to output an assembler line - to define a local common symbol. */ - -#undef ASM_OUTPUT_LOCAL -#ifndef USE_GAS -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -( fputs ("\tlcomm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%u\n", (int)(SIZE))) -#else /* USE_GAS */ -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -( fputs ("\t.lcomm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%u\n", (int)(SIZE))) -#endif /* USE_GAS */ - -#ifndef USE_GAS -/* Override usual definitions of SDB output macros. - These definitions differ only in the absence of the period - at the beginning of the name of the directive - and in the use of `~' as the symbol for the current location. */ - -#define PUT_SDB_SCL(a) fprintf(asm_out_file, "\tscl\t%d;", (a)) -#define PUT_SDB_INT_VAL(a) fprintf (asm_out_file, "\tval\t%d;", (a)) -#define PUT_SDB_VAL(a) \ -( fputs ("\tval\t", asm_out_file), \ - output_addr_const (asm_out_file, (a)), \ - fputc (';', asm_out_file)) - -#define PUT_SDB_DEF(a) \ -do { fprintf (asm_out_file, "\tdef\t"); \ - ASM_OUTPUT_LABELREF (asm_out_file, a); \ - fprintf (asm_out_file, ";"); } while (0) - -#define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s;",a) -#define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file) -#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o;", a) -#define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d;", a) -#define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t") -#define PUT_SDB_NEXT_DIM(a) fprintf(asm_out_file, "%d,", a) -#define PUT_SDB_LAST_DIM(a) fprintf(asm_out_file, "%d;", a) - -#define PUT_SDB_TAG(a) \ -do { fprintf (asm_out_file, "\ttag\t"); \ - ASM_OUTPUT_LABELREF (asm_out_file, a); \ - fprintf (asm_out_file, ";"); } while (0) - -#define PUT_SDB_BLOCK_START(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~bb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_BLOCK_END(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~eb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_FUNCTION_START(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~bf;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_FUNCTION_END(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~ef;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_EPILOGUE_END(NAME) \ - fprintf (asm_out_file, \ - "\tdef\t%s;\tval\t~;\tscl\t-1;\tendef\n", \ - (NAME)) - -#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ - sprintf ((BUFFER), "~%dfake", (NUMBER)); - -#endif /* USE_GAS */ - -/* Define subroutines to call to handle multiply, divide, and remainder. - Use the subroutines that the sysV68's library provides. - The `*' prevents an underscore from being prepended by the compiler. */ -/* The '*' is also used by INIT_CUMULATIVE_ARGS */ - -#define DIVSI3_LIBCALL "*ldiv%%" -#define UDIVSI3_LIBCALL "*uldiv%%" -#define MODSI3_LIBCALL "*lrem%%" -#define UMODSI3_LIBCALL "*ulrem%%" -#define MULSI3_LIBCALL "*lmul%%" - -struct sysV68_cumulative_args - { - int offset; - int libcall; - }; - -#undef CUMULATIVE_ARGS -#define CUMULATIVE_ARGS struct sysV68_cumulative_args - -#undef INIT_CUMULATIVE_ARGS -#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ -do {(CUM).offset = 0;\ -(CUM).libcall = (LIBNAME) && (*XSTR((LIBNAME), 0) == '*');} while(0) - -#undef FUNCTION_ARG_ADVANCE -#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ - ((CUM).offset += ((MODE) != BLKmode \ - ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ - : (int_size_in_bytes (TYPE) + 3) & ~3)) - -#undef FUNCTION_ARG -#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ -(((CUM).libcall && (CUM).offset == 0) ? gen_rtx_REG ((MODE), 0)\ -: (TARGET_REGPARM && (CUM).offset < 8) ? gen_rtx_REG ((MODE), (CUM).offset / 4) : 0) - -#undef FUNCTION_ARG_PARTIAL_NREGS -#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ -((TARGET_REGPARM && (CUM).offset < 8 \ - && 8 < ((CUM).offset + ((MODE) == BLKmode \ - ? int_size_in_bytes (TYPE) \ - : GET_MODE_SIZE (MODE)))) \ - ? 2 - (CUM).offset / 4 : 0) - -#undef FUNCTION_ARG_REGNO_P -#define FUNCTION_ARG_REGNO_P(N) (TARGET_68020 ? 0 : (N) == 0) - -/* manfred@lts.sel.alcatel.de: I believe that most delta machines are configured to have - a 6888[12] FPU for which we need to link -lm881 instead of -lm; define ALT_LIBM to - tell g++.c about that. */ -#define ALT_LIBM "-lm881" - -#if (TARGET_DEFAULT & MASK_68881) /* The default configuration has a 6888[12] FPU. */ -#define MATH_LIBRARY "-lm881" -#endif - -/* Currently we do not have the atexit() function, - so take that from libgcc2.c */ - -#define NEED_ATEXIT 1 - -#define EXIT_BODY \ - do \ - { \ - __stop_monitor (); \ - _cleanup (); \ - } while (0) - -/* FINALIZE_TRAMPOLINE clears the instruction cache. */ - -#undef FINALIZE_TRAMPOLINE -#define FINALIZE_TRAMPOLINE(TRAMP) \ - if (!TARGET_68040) \ - ; \ - else \ - emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_insn_cache"), \ - 0, VOIDmode, 0) diff --git a/gcc/config/m68k/pbb.h b/gcc/config/m68k/pbb.h deleted file mode 100644 index 68c8d09ead5..00000000000 --- a/gcc/config/m68k/pbb.h +++ /dev/null @@ -1,163 +0,0 @@ -/* Definitions of target machine for GNU compiler. - Citicorp/TTI Unicom PBB version (using GAS with a %-register prefix) - Copyright (C) 1987, 1988, 1990, 1996, 1997, 2002 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* Note: This config uses a version of gas with a postprocessing stage that - converts the output of gas to coff containing stab debug symbols. - (See vasta@apollo.com or mb@soldev.tti.com) */ - -#include "m68k/m68k.h" - -/* See m68k.h. 5 means 68020 without 68881. */ - -#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020) - -/* Don't try using XFmode. */ -#undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* Every structure or union's size must be a multiple of 2 bytes. */ -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* Define __HAVE_68881__ in preprocessor if -m68881 is specified. - This will control the use of inline 68881 insns in certain macros. */ - -#define CPP_SPEC "%{m68881:-D__HAVE_68881__}" - -/* Names to predefine in the preprocessor for this target machine. */ - -#define CPP_PREDEFINES "-Dm68k -Dunix -DUnicomPBB -Dmc68k -Dmc68020 -Dmc68k32 -Asystem=unix -Acpu=m68k -Amachine=m68k" - -/* We want DBX format for use with gdb under COFF. */ - -#define DBX_DEBUGGING_INFO 1 - -/* Generate calls to memcpy, memcmp and memset. */ - -#define TARGET_MEM_FUNCTIONS - -/* -m68000 requires special flags to the assembler. */ - -#define ASM_SPEC \ - " %{m68000:-mc68010}%{mc68000:-mc68010}" - -/* we use /lib/libp/lib* when profiling */ - -#define LIB_SPEC "%{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp} -lc" - - -/* Use crt1.o as a startup file and crtn.o as a closing file. */ -/* - * The loader directive file gcc.ifile defines how to merge the constructor - * sections into the data section. Also, since gas only puts out those - * sections in response to N_SETT stabs, and does not (yet) have a - * ".sections" directive, gcc.ifile also defines the list symbols - * __DTOR_LIST__ and __CTOR_LIST__. - * - * Finally, we must explicitly specify the file from libgcc.a that defines - * exit(), otherwise if the user specifies (for example) "-lc_s" on the - * command line, the wrong exit() will be used and global destructors will - * not get called . - */ - -#define STARTFILE_SPEC \ -"%{!r: gcc.ifile%s} %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} \ -%{!r:_exit.o%s}" - -#define ENDFILE_SPEC "crtn.o%s" - -/* GAS register prefix assembly syntax: */ - -/* User labels have no prefix */ -#undef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "" - -/* local labels are prefixed with ".L" */ -#undef LOCAL_LABEL_PREFIX -#define LOCAL_LABEL_PREFIX "." - -/* registers are prefixed with "%" */ -#undef REGISTER_PREFIX -#define REGISTER_PREFIX "%" - -#undef REGISTER_NAMES -#define REGISTER_NAMES \ -{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ - "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \ - "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"} - -#undef FUNCTION_EXTRA_EPILOGUE -#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) \ -{ if (current_function_returns_pointer \ - && ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode)) \ - asm_fprintf (FILE, "\tmovl %Rd0,%Ra0\n"); } - -#define ASM_RETURN_CASE_JUMP \ - do { \ - if (TARGET_5200) \ - { \ - if (ADDRESS_REG_P (operands[0])) \ - return "jmp %%pc@(2,%0:l)"; \ - else \ - return "ext%.l %0\n\tjmp %%pc@(2,%0:l)"; \ - } \ - else \ - return "jmp %%pc@(2,%0:w)"; \ - } while (0) - -/* Although the gas we use can create .ctor and .dtor sections from N_SETT - stabs, it does not support section directives, so we need to have the loader - define the lists. - */ -#define CTOR_LISTS_DEFINED_EXTERNALLY - -/* similar to default, but allows for the table defined by ld with gcc.ifile. - nptrs is always 0. So we need to instead check that __DTOR_LIST__[1] != 0. - The old check is left in so that the same macro can be used if and when - a future version of gas does support section directives. */ - -#define DO_GLOBAL_DTORS_BODY {int nptrs = *(int *)__DTOR_LIST__; int i; \ - if (nptrs == -1 || (__DTOR_LIST__[0] == 0 && __DTOR_LIST__[1] != 0)) \ - for (nptrs = 0; __DTOR_LIST__[nptrs + 1] != 0; nptrs++); \ - for (i = nptrs; i >= 1; i--) \ - __DTOR_LIST__[i] (); } - -/* - * Here is an example gcc.ifile. I've tested it on PBB 68k and on sco 386 - * systems. The NEXT(0x200000) works on just about all 386 and m68k systems, - * but can be reduced to any power of 2 that is >= NBPS (0x10000 on a pbb). - - SECTIONS { - .text BIND(0x200200) BLOCK (0x200) : - { *(.init) *(.text) vfork = fork; *(.fini) } - - GROUP BIND( NEXT(0x200000) + ADDR(.text) + SIZEOF(.text)): - { .data : { __CTOR_LIST__ = . ; . += 4; *(.ctor) . += 4 ; - __DTOR_LIST__ = . ; . += 4; *(.dtor) . += 4 ; } - .bss : { } - } - } - */ - -/* -Local variables: -version-control: t -End: -*/ diff --git a/gcc/config/m68k/plexus.h b/gcc/config/m68k/plexus.h deleted file mode 100644 index 0fac3e29dc7..00000000000 --- a/gcc/config/m68k/plexus.h +++ /dev/null @@ -1,106 +0,0 @@ -/* Definitions of target machine for GNU compiler, for 680X0 based Plexus - Computers running SYSVR2 - Copyright (C) 1990, 1994, 1996 Free Software Foundation, Inc. - Contributed by Randy Welch (rwelch@netcom.com). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - - -/* The Plexus port of gcc requires you to use gas ( either 1.3X with COFF - patches or 2.X ), If you use gas 2.X you have to use binutils-2.X. - - With using gas-2.X the Plexus gcc port is now capable of generating - output suitable for use by gdb-4.X ( send mail to above address for - info on getting gdb patches or other GNU items for the Plexus ) - - This is configured for label output default by gas as LXXX instead of - plexus cc/as combination requires .LXXX */ - -#include "m68k/m68k.h" - -/* Define __HAVE_68881 in preprocessor only if -m68881 is specified. - This will control the use of inline 68881 insns in certain macros. */ - -#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020) - -/* Don't try using XFmode. */ -#undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 64 - -#define CPP_SPEC "%{m68881:-D__HAVE_68881__}" -#define CPP_PREDEFINES "-Dm68 -Dunix -Dplexus -Asystem=unix -Acpu=m68k -Amachine=m68k" - -#if TARGET_DEFAULT & MASK_68020 -#define ASM_SPEC \ -"%{m68000:-mc68000}%{mc68000:-mc68000}%{!mc68000:%{!m68000:-mc68020}}" -#undef STRICT_ALIGNMENT -#define STRICT_ALIGNMENT 0 -#else -#define ASM_SPEC\ -"%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!mc68020:-mc68000}}" -#endif - -/***************************************************************************/ -/* Un comment the following if you want adb to be able to follow a core */ -/* file if you compile a program with -O */ -/***************************************************************************/ -/* #define FRAME_POINTER_REQUIRED */ - -/* Let's be compatible with the Plexus C compiler by default. Why not? */ -#define PLEXUS_CC_COMPAT - -#ifdef PLEXUS_CC_COMPAT -#define STRUCTURE_SIZE_BOUNDARY 16 /* for compatibility with cc */ -#undef STACK_BOUNDARY -#define STACK_BOUNDARY 32 /* ditto */ -#endif - -#undef NEED_PROBE -#define NEED_PROBE -132 /* plexus needs a stack probe */ - -/***********************************************************************/ -/* if you have binutils-2.X and gas-2.X running you can generate code */ -/* that gdb can understand ( gdb support available for 4.11 ) */ -/* */ -/* If you use gas-1.3X don't define this as the version of the coff */ -/* patches for gas-1.3x ( stabs in coff ) does not generate coff debug */ -/* syms */ -/***********************************************************************/ -#define HAVE_GAS_2_X - -#ifdef HAVE_GAS_2_X -#undef DBX_DEBUGGING_INFO -#define SDB_DEBUGGING_INFO 1 - -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) \ - output_file_directive((FILE), main_input_filename) - -#else -#undef DBX_DEBUGGING_INFO /* no real debugger */ -#undef SDB_DEBUGGING_INFO -#endif -#define TARGET_MEM_FUNCTIONS - -/***********************************************************************/ -/* items for collect2 */ -/***********************************************************************/ - -#define NM_FLAGS "" - -#define SIZE_TYPE "int" diff --git a/gcc/config/m68k/sun2.h b/gcc/config/m68k/sun2.h deleted file mode 100644 index 0f3dde3aeee..00000000000 --- a/gcc/config/m68k/sun2.h +++ /dev/null @@ -1,77 +0,0 @@ -/* Definitions of target machine for GNU compiler. Sun 68010 version. - Copyright (C) 1987, 1988, 1995 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - - -#include "m68k/m68k.h" - -/* See m68k.h. 0 means 68000 with no 68881. */ - -#define TARGET_DEFAULT 0 - -/* Don't try using XFmode. */ -#undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* Define __HAVE_68881 in preprocessor only if -m68881 is specified. - This will control the use of inline 68881 insns in certain macros. - Also inform the program which CPU this is for. */ - -#define CPP_SPEC "%{m68881:-D__HAVE_68881__} \ -%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}" - -/* -m68020 requires special flags to the assembler. */ - -#define ASM_SPEC \ - "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!m68020:-mc68010}} \ - %{fpic:-k} %{fPIC:-k} %{R} %{j} %{J} %{h} %{d2} %{keep-local-as-symbols:-L}" - -/* Names to predefine in the preprocessor for this target machine. */ - -#define CPP_PREDEFINES "-Dmc68000 -Dsun -Dunix -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k" - -/* Prevent error on `-sun2' and `-target sun2' options. */ - -#define CC1_SPEC "%{sun2:} %{target:}" - -/* These compiler options take an argument. We ignore -target for now. */ - -#define WORD_SWITCH_TAKES_ARG(STR) \ - (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ - || !strcmp (STR, "target") || !strcmp (STR, "assert")) - -/* Specify what to link with. */ - -/* Link with libg.a when debugging, for dbx's sake. */ -/* Include the support for -a when appropriate. */ -#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ -%{a:/usr/lib/bb_link.o -lc} " - -/* Alignment of field after `int : 0' in a structure. */ - -#undef EMPTY_FIELD_BOUNDARY -#define EMPTY_FIELD_BOUNDARY 16 - -/* Every structure or union's size must be a multiple of 2 bytes. */ - -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* This is BSD, so it wants DBX format. */ - -#define DBX_DEBUGGING_INFO 1 diff --git a/gcc/config/m68k/sun2o4.h b/gcc/config/m68k/sun2o4.h deleted file mode 100644 index 0601bd07f84..00000000000 --- a/gcc/config/m68k/sun2o4.h +++ /dev/null @@ -1,147 +0,0 @@ -/* Definitions of target machine for GNU compiler. Sun 2 running SunOS 4. - Copyright (C) 1987, 1988, 1993, 1996, 1997 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#include "m68k/sun2.h" - - -/* Define __HAVE_SKY__ in preprocessor, according to the -m flags. - Also inform the program which CPU this is for. */ - -#undef CPP_SPEC - -#undef PTRDIFF_TYPE -#define PTRDIFF_TYPE "int" -#undef SIZE_TYPE -#define SIZE_TYPE "int" -#undef WCHAR_TYPE -#define WCHAR_TYPE "short unsigned int" -#undef WCHAR_TYPE_SIZE -#define WCHAR_TYPE_SIZE 16 - -#if TARGET_DEFAULT & MASK_SKY - -/* -msky is the default */ -#define CPP_SPEC \ -"%{!msoft-float:-D__HAVE_SKY__}\ -%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}" - -#else - -/* -msoft-float is the default */ -#define CPP_SPEC \ -"%{msky:-D__HAVE_SKY__ }\ -%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}" - -#endif - -/* STARTFILE_SPEC to include sun floating point initialization - This is necessary (tr: Sun does it) for the sky routines. - I'm not sure what would happen below if people gave contradictory - arguments (eg. -msoft-float -mfpa) */ - -#undef STARTFILE_SPEC - -#if TARGET_DEFAULT & MASK_SKY -/* -msky is the default */ -#define STARTFILE_SPEC \ - "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} \ - %{msoft-float:Fcrt1.o%s} \ - %{!msoft-float:Scrt1.o%s}" -#else -/* -msoft-float is the default */ -#define STARTFILE_SPEC \ - "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} \ - %{msky:Scrt1.o%s} \ - %{!msky:Fcrt1.o%s}" -#endif - -/* Specify library to handle `-a' basic block profiling. - Control choice of libm.a (if user says -lm) - based on fp arith default and options. */ - -#undef LIB_SPEC - -#if TARGET_DEFAULT & MASK_SKY -/* -msky is the default */ -#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ -%{a:/usr/lib/bb_link.o -lc} %{g:-lg} \ -%{msoft-float:-L/usr/lib/fsoft} \ -%{!msoft_float:-L/usr/lib/fsky}" -#else -/* -msoft-float is the default */ -#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ -%{a:/usr/lib/bb_link.o -lc} %{g:-lg} \ -%{!msky:-L/usr/lib/fsoft} \ -%{msky:-L/usr/lib/ffpa}" -#endif - -#undef LINK_SPEC -#define LINK_SPEC \ - "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic}" - -#undef ASM_OUTPUT_FLOAT_OPERAND -#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ - do { \ - if (CODE != 'f') \ - { \ - long l; \ - REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ - if (sizeof (int) == sizeof (long)) \ - asm_fprintf ((FILE), "%I0x%x", (int) l); \ - else \ - asm_fprintf ((FILE), "%I0x%lx", l); \ - } \ - else if (REAL_VALUE_ISINF (VALUE)) \ - { \ - if (REAL_VALUE_NEGATIVE (VALUE)) \ - fprintf (FILE, "#0r-99e999"); \ - else \ - fprintf (FILE, "#0r99e999"); \ - } \ - else if (REAL_VALUE_MINUS_ZERO (VALUE)) \ - { \ - fprintf (FILE, "#0r-0.0"); \ - } \ - else \ - { char dstr[30]; \ - real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \ - fprintf (FILE, "#0r%s", dstr); \ - } \ - } while (0) - -#undef ASM_OUTPUT_DOUBLE_OPERAND -#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ - do { if (REAL_VALUE_ISINF (VALUE)) \ - { \ - if (REAL_VALUE_NEGATIVE (VALUE)) \ - fprintf (FILE, "#0r-99e999"); \ - else \ - fprintf (FILE, "#0r99e999"); \ - } \ - else if (REAL_VALUE_MINUS_ZERO (VALUE)) \ - { \ - fprintf (FILE, "#0r-0.0"); \ - } \ - else \ - { char dstr[30]; \ - real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ - fprintf (FILE, "#0r%s", dstr); \ - } \ - } while (0) diff --git a/gcc/config/m68k/sun3.h b/gcc/config/m68k/sun3.h deleted file mode 100644 index 1d64599f332..00000000000 --- a/gcc/config/m68k/sun3.h +++ /dev/null @@ -1,234 +0,0 @@ -/* Definitions of target machine for GNU compiler. Sun 68000/68020 version. - Copyright (C) 1987, 1988, 1993, 1995, 1996, 1998, 1999 - Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* This comment is here to see if it will keep Sun's cpp from dying. */ - -/* If you do not need to generate floating point code for the optional - Sun FPA board, you can safely comment out the SUPPORT_SUN_FPA define - to gain a little speed and code size. */ - -#define SUPPORT_SUN_FPA - -#include "m68k/m68k.h" - -/* See m68k.h. 7 means 68020 with 68881. */ - -#ifndef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020) -#endif - -/* Define __HAVE_FPA__ or __HAVE_68881__ in preprocessor, - according to the -m flags. - This will control the use of inline 68881 insns in certain macros. - Also inform the program which CPU this is for. */ - -#if TARGET_DEFAULT & MASK_68881 - -/* -m68881 is the default */ -#define CPP_SPEC \ -"%{!msoft-float:%{mfpa:-D__HAVE_FPA__ }%{!mfpa:-D__HAVE_68881__ }}\ -%{m68000:-D__mc68010__}%{mc68000:-D__mc68010__}%{!mc68000:%{!m68000:-D__mc68020__}} \ -%{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}" - -#else - -/* -msoft-float is the default */ -#define CPP_SPEC \ -"%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }\ -%{m68000:-D__mc68010__}%{mc68000:-D__mc68010__}%{!mc68000:%{!m68000:-D__mc68020__}} \ -%{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}" - -#endif - -/* Prevent error on `-sun3' and `-target sun3' options. */ - -#define CC1_SPEC "%{sun3:} %{target:}" - -#define PTRDIFF_TYPE "int" - -/* We must override m68k.h. */ -#undef WCHAR_TYPE -#undef WCHAR_TYPE_SIZE -#define WCHAR_TYPE "short unsigned int" -#define WCHAR_TYPE_SIZE 16 - -/* These compiler options take an argument. We ignore -target for now. */ - -#define WORD_SWITCH_TAKES_ARG(STR) \ - (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ - || !strcmp (STR, "target") || !strcmp (STR, "assert")) - -/* -m68000 requires special flags to the assembler. */ - -#define ASM_SPEC \ - "%{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}} \ - %{fpic:-k} %{fPIC:-k} %{R} %{j} %{J} %{h} %{d2} %{keep-local-as-symbols:-L}" - -/* Names to predefine in the preprocessor for this target machine. */ -/* For a while, -D_CROSS_TARGET_ARCH=SUN3 was included here, - but it doesn't work, partly because SUN3 etc. aren't defined - (and shouldn't be). It seems that on a native compiler _CROSS_TARGET_ARCH - should not be defined. For cross compilers, let's do things as we - normally do in GCC. -- rms. */ - -#define CPP_PREDEFINES "-Dmc68000 -Dsun -Dunix -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k" - -/* STARTFILE_SPEC to include sun floating point initialization - This is necessary (tr: Sun does it) for both the m68881 and the fpa - routines. - Note that includes knowledge of the default specs for gcc, ie. no - args translates to the same effect as -m68881 - I'm not sure what would happen below if people gave contradictory - arguments (eg. -msoft-float -mfpa) */ - -#if TARGET_DEFAULT & MASK_FPA -/* -mfpa is the default */ -#define STARTFILE_SPEC \ - "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} \ - %{m68881:Mcrt1.o%s} \ - %{msoft-float:Fcrt1.o%s} \ - %{!m68881:%{!msoft-float:Wcrt1.o%s}}" -#else -#if TARGET_DEFAULT & MASK_68881 -/* -m68881 is the default */ -#define STARTFILE_SPEC \ - "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} \ - %{mfpa:Wcrt1.o%s} \ - %{msoft-float:Fcrt1.o%s} \ - %{!mfpa:%{!msoft-float:Mcrt1.o%s}}" -#else -/* -msoft-float is the default */ -#define STARTFILE_SPEC \ - "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} \ - %{m68881:Mcrt1.o%s} \ - %{mfpa:Wcrt1.o%s} \ - %{!m68881:%{!mfpa:Fcrt1.o%s}}" -#endif -#endif - -/* Specify library to handle `-a' basic block profiling. - Control choice of libm.a (if user says -lm) - based on fp arith default and options. */ - -#if TARGET_DEFAULT & MASK_FPA -/* -mfpa is the default */ -#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ -%{g:-lg} \ -%{msoft-float:-L/usr/lib/fsoft}%{m68881:-L/usr/lib/f68881}\ -%{!msoft_float:%{!m68881:-L/usr/lib/ffpa}}" -#else -#if TARGET_DEFAULT & MASK_68881 -/* -m68881 is the default */ -#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ -%{g:-lg} \ -%{msoft-float:-L/usr/lib/fsoft}%{!msoft-float:%{!mfpa:-L/usr/lib/f68881}}\ -%{mfpa:-L/usr/lib/ffpa}" -#else -/* -msoft-float is the default */ -#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ -%{g:-lg} \ -%{!m68881:%{!mfpa:-L/usr/lib/fsoft}}%{m68881:-L/usr/lib/f68881}\ -%{mfpa:-L/usr/lib/ffpa}" -#endif -#endif - -/* Provide required defaults for linker -e and -d switches. */ - -#define LINK_SPEC \ - "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}" - -/* Every structure or union's size must be a multiple of 2 bytes. */ - -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* This is BSD, so it wants DBX format. */ - -#define DBX_DEBUGGING_INFO 1 - -/* Generate calls to memcpy, memcmp and memset. */ -#define TARGET_MEM_FUNCTIONS - -/* This is not a good idea. It prevents interoperation between - files compiled with -m68881 and those compiled with -msoft-float. */ -#if 0 -#define FUNCTION_VALUEX(MODE) \ - gen_rtx_REG ((MODE), \ - ((TARGET_68881 \ - && ((MODE) == SFmode || (MODE) == DFmode \ - || (MODE) == XFmode)) \ - ? 16 : 0)) - -#undef FUNCTION_VALUE -#define FUNCTION_VALUE(VALTYPE,FUNC) FUNCTION_VALUEX (TYPE_MODE (VALTYPE)) -#endif /* 0 */ - -/* This is how to output an assembler lines defining floating operands. - There's no way to output a NaN's fraction, so we lose it. */ - -#undef ASM_OUTPUT_FLOAT_OPERAND -#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ - do { \ - if (CODE != 'f') \ - { \ - long l; \ - REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ - if (sizeof (int) == sizeof (long)) \ - asm_fprintf ((FILE), "%I0x%x", (int) l); \ - else \ - asm_fprintf ((FILE), "%I0x%lx", l); \ - } \ - else if (REAL_VALUE_ISINF (VALUE)) \ - { \ - if (REAL_VALUE_NEGATIVE (VALUE)) \ - asm_fprintf (FILE, "%I0r-99e999"); \ - else \ - asm_fprintf (FILE, "%I0r99e999"); \ - } \ - else if (REAL_VALUE_MINUS_ZERO (VALUE)) \ - { \ - asm_fprintf (FILE, "%I0r-0.0"); \ - } \ - else \ - { char dstr[30]; \ - real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \ - asm_fprintf (FILE, "%I0r%s", dstr); \ - } \ - } while (0) - -#undef ASM_OUTPUT_DOUBLE_OPERAND -#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ - do { if (REAL_VALUE_ISINF (VALUE)) \ - { \ - if (REAL_VALUE_NEGATIVE (VALUE)) \ - asm_fprintf (FILE, "%I0r-99e999"); \ - else \ - asm_fprintf (FILE, "%I0r99e999"); \ - } \ - else if (REAL_VALUE_MINUS_ZERO (VALUE)) \ - { \ - asm_fprintf (FILE, "%I0r-0.0"); \ - } \ - else \ - { char dstr[30]; \ - real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ - asm_fprintf (FILE, "%I0r%s", dstr); \ - } \ - } while (0) diff --git a/gcc/config/m68k/sun3mach.h b/gcc/config/m68k/sun3mach.h deleted file mode 100644 index 6769cfa096d..00000000000 --- a/gcc/config/m68k/sun3mach.h +++ /dev/null @@ -1,15 +0,0 @@ -#include "m68k/sun3.h" - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dmc68000 -Dsun -Dsun3 -Dunix -DMACH -DCMU -DMTXINU -DBIT_MSF -DBYTE_MSF -Asystem=unix -Asystem=mach -Acpu=m68k -Amachine=m68k" - -/* Specify extra dir to search for include files. */ -#define SYSTEM_INCLUDE_DIR "/usr/mach/include" - -/* LINK_SPEC is needed only for SunOS 4. */ - -#undef LINK_SPEC - -/* Don't default to pcc-struct-return, because gcc is the only compiler, and - we want to retain compatibility with older gcc versions. */ -#define DEFAULT_PCC_STRUCT_RETURN 0 diff --git a/gcc/config/m68k/sun3n.h b/gcc/config/m68k/sun3n.h deleted file mode 100644 index 32f5f657dc0..00000000000 --- a/gcc/config/m68k/sun3n.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Define target machine as a Sun 3 with no 68881. */ - -#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020) - -#include "m68k/sun3.h" - -/* Don't try using XFmode. */ -#undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 64 diff --git a/gcc/config/m68k/sun3n3.h b/gcc/config/m68k/sun3n3.h deleted file mode 100644 index 38680d805e2..00000000000 --- a/gcc/config/m68k/sun3n3.h +++ /dev/null @@ -1,5 +0,0 @@ -#include "m68k/sun3n.h" - -/* LINK_SPEC is needed only for SunOS 4. */ - -#undef LINK_SPEC diff --git a/gcc/config/m68k/sun3o3.h b/gcc/config/m68k/sun3o3.h deleted file mode 100644 index 95f1ff65d03..00000000000 --- a/gcc/config/m68k/sun3o3.h +++ /dev/null @@ -1,5 +0,0 @@ -#include "m68k/sun3.h" - -/* LINK_SPEC is needed only for SunOS 4. */ - -#undef LINK_SPEC diff --git a/gcc/config/m68k/t-mot3300 b/gcc/config/m68k/t-mot3300 deleted file mode 100644 index 2fc11858d58..00000000000 --- a/gcc/config/m68k/t-mot3300 +++ /dev/null @@ -1,10 +0,0 @@ -MULTILIB_OPTIONS=m68000/m68020 msoft-float -MULTILIB_DIRNAMES= -MULTILIB_MATCHES=m68000=mc68000 m68000=m68302 m68000=m68332 m68020=mc68020 m68020=m68040 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib - -CRT0_S = $(srcdir)/config/m68k/mot3300-crt0.S -MCRT0_S = $(srcdir)/config/m68k/mot3300Mcrt0.S -CRT0STUFF_T_CFLAGS = -DMOTOROLA -DSGS_CMP_ORDER diff --git a/gcc/config/m68k/t-mot3300-gald b/gcc/config/m68k/t-mot3300-gald deleted file mode 100644 index 1d6cd3d8dd7..00000000000 --- a/gcc/config/m68k/t-mot3300-gald +++ /dev/null @@ -1,27 +0,0 @@ -T_CPPFLAGS = -DUSE_GAS -DUSE_GLD -TARGET_LIBGCC2_CFLAGS = -DUSE_GAS - -LIB1ASMSRC = m68k/lb1sf68.asm -LIB1ASMFUNCS = _mulsi3 _udivsi3 _divsi3 _umodsi3 _modsi3 \ - _double _float _floatex \ - _eqdf2 _nedf2 _gtdf2 _gedf2 _ltdf2 _ledf2 \ - _eqsf2 _nesf2 _gtsf2 _gesf2 _ltsf2 _lesf2 - -LIB2FUNCS_EXTRA = fpgnulib.c xfgnulib.c - -fpgnulib.c: $(srcdir)/config/m68k/fpgnulib.c - cp $(srcdir)/config/m68k/fpgnulib.c fpgnulib.c -xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c - echo '#define EXTFLOAT' > xfgnulib.c - cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c - -MULTILIB_OPTIONS=m68000/m68020 msoft-float -MULTILIB_DIRNAMES= -MULTILIB_MATCHES=m68000=mc68000 m68000=m68302 m68000=m68332 m68020=mc68020 m68020=m68040 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib - -CRT0_S = $(srcdir)/config/m68k/mot3300-crt0.S -MCRT0_S = $(srcdir)/config/m68k/mot3300Mcrt0.S -CRT0STUFF_T_CFLAGS = diff --git a/gcc/config/m68k/t-mot3300-gas b/gcc/config/m68k/t-mot3300-gas deleted file mode 100644 index ba222499084..00000000000 --- a/gcc/config/m68k/t-mot3300-gas +++ /dev/null @@ -1,27 +0,0 @@ -T_CPPFLAGS = -DUSE_GAS -TARGET_LIBGCC2_CFLAGS = -DUSE_GAS - -LIB1ASMSRC = m68k/lb1sf68.asm -LIB1ASMFUNCS = _mulsi3 _udivsi3 _divsi3 _umodsi3 _modsi3 \ - _double _float _floatex \ - _eqdf2 _nedf2 _gtdf2 _gedf2 _ltdf2 _ledf2 \ - _eqsf2 _nesf2 _gtsf2 _gesf2 _ltsf2 _lesf2 - -LIB2FUNCS_EXTRA = fpgnulib.c xfgnulib.c - -fpgnulib.c: $(srcdir)/config/m68k/fpgnulib.c - cp $(srcdir)/config/m68k/fpgnulib.c fpgnulib.c -xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c - echo '#define EXTFLOAT' > xfgnulib.c - cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c - -MULTILIB_OPTIONS=m68000/m68020 msoft-float -MULTILIB_DIRNAMES= -MULTILIB_MATCHES=m68000=mc68000 m68000=m68302 m68000=m68332 m68020=mc68020 m68020=m68040 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib - -CRT0_S = $(srcdir)/config/m68k/mot3300-crt0.S -MCRT0_S = $(srcdir)/config/m68k/mot3300Mcrt0.S -CRT0STUFF_T_CFLAGS = diff --git a/gcc/config/m68k/t-mot3300-gld b/gcc/config/m68k/t-mot3300-gld deleted file mode 100644 index 8cc3ed6f250..00000000000 --- a/gcc/config/m68k/t-mot3300-gld +++ /dev/null @@ -1,12 +0,0 @@ -T_CPPFLAGS = -DUSE_GLD - -MULTILIB_OPTIONS=m68000/m68020 msoft-float -MULTILIB_DIRNAMES= -MULTILIB_MATCHES=m68000=mc68000 m68000=m68302 m68000=m68332 m68020=mc68020 m68020=m68040 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib - -CRT0_S = $(srcdir)/config/m68k/mot3300-crt0.S -MCRT0_S = $(srcdir)/config/m68k/mot3300Mcrt0.S -CRT0STUFF_T_CFLAGS = -DMOTOROLA -DSGS_CMP_ORDER diff --git a/gcc/config/m68k/tower-as.h b/gcc/config/m68k/tower-as.h deleted file mode 100644 index 9675a4dc20d..00000000000 --- a/gcc/config/m68k/tower-as.h +++ /dev/null @@ -1,525 +0,0 @@ -/* Definitions of target machine for GNU compiler. - For NCR Tower 32/4x0 and 32/6x0 running System V Release 3. - Copyright (C) 1990, 1993, 1994, 1996, 1997, 2000, 2002 - Free Software Foundation, Inc. - Contributed by Robert Andersson (ra@intsys.no), International Systems, - Oslo, Norway. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - - -/* This file outputs assembler source suitable for the native Tower as - and with sdb debugging symbols. See tower.h for more comments. - - This file was based on m68k.h, hp320.h and 3b1.h as of the - 1.37.1 version. */ - -#include "m68k/tower.h" - -/* Use default settings for system V.3. */ - -#include "svr3.h" - -/* Names to predefine in the preprocessor for this target machine. */ - -#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_600 -D__motorola__ -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k" - -/* Define __HAVE_68881 in preprocessor only if -m68881 is specified. - This will control the use of inline 68881 insns in certain macros. - Also, define special define used to identify the Tower assembler. */ - -#define CPP_SPEC "-D__TOWER_ASM__ %{m68881:-D__HAVE_68881__}" - -/* We don't want local labels to start with period. - See (*targetm.asm_out.internal_label). */ -#undef LOCAL_LABEL_PREFIX -#define LOCAL_LABEL_PREFIX "" - -/* The prefix to add to user-visible assembler symbols. */ -/* We do not want leading underscores. */ - -#undef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "" - -/* These four macros control how m68k.md is expanded. */ - -#define MOTOROLA /* Use Motorola syntax rather than "MIT" */ -#define SGS /* Uses SGS assembler */ -#define SGS_CMP_ORDER /* Takes cmp operands in reverse order */ -#define SGS_NO_LI /* Suppress jump table label usage */ - -#undef INT_OP_GROUP -#define INT_OP_GROUP INT_OP_NO_DOT - -/* Turn on SDB debugging info. */ - -#define SDB_DEBUGGING_INFO 1 - -/* All the ASM_OUTPUT macros need to conform to the Tower as syntax. */ - -#define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \ - do { \ - fprintf (FILE, "\tfile\t"); \ - output_quoted_string (FILE, FILENAME); \ - fprintf (FILE, "\n"); \ - fprintf (FILE, "section ~init,\"x\"\n"); \ - fprintf (FILE, "section ~fini,\"x\"\n"); \ - fprintf (FILE, "section ~rodata,\"x\"\n"); \ - fprintf (FILE, "text\n"); \ - } while (0) - -#define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO) \ - fprintf (FILE, "\tln\t%d\n", \ - (sdb_begin_function_line > -1 \ - ? (LINENO) - sdb_begin_function_line : 1)) - -#undef ASM_OUTPUT_IDENT -#define ASM_OUTPUT_IDENT(FILE, NAME) \ - fprintf (FILE, "\tident\t\"%s\" \n", NAME) - -#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ - do { register size_t sp = 0, lp = 0, limit = (LEN); \ - fprintf ((FILE), "\tbyte\t"); \ - loop: \ - if ((PTR)[sp] > ' ' && ! ((PTR)[sp] & 0x80) && (PTR)[sp] != '\\') \ - { lp += 3; \ - fprintf ((FILE), "'%c", (PTR)[sp]); } \ - else \ - { lp += 5; \ - fprintf ((FILE), "0x%x", (PTR)[sp]); } \ - if (++sp < limit) \ - { if (lp > 60) \ - { lp = 0; \ - fprintf ((FILE), "\n\tbyte\t"); } \ - else \ - putc (',', (FILE)); \ - goto loop; } \ - putc ('\n', (FILE)); } while (0) - -/* Translate Motorola opcodes such as `jbeq' - into SGS/Tower opcodes such as `beq.w'. - Change `move' to `mov'. - Change `cmpm' to `cmp'. - Change `divsl' to `tdivs'. - Change `divul' to `tdivu'. - Change `ftst' to `ftest'. - Change `fmove' to `fmov'. */ - -#define ASM_OUTPUT_OPCODE(FILE, PTR) \ -{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ - { ++(PTR); \ - while (*(PTR) != ' ') \ - { putc (*(PTR), (FILE)); ++(PTR); } \ - fprintf ((FILE), ".w"); } \ - else if ((PTR)[0] == 'm' && (PTR)[1] == 'o' \ - && (PTR)[2] == 'v' && (PTR)[3] == 'e') \ - { fprintf ((FILE), "mov"); (PTR) += 4; } \ - else if ((PTR)[0] == 'c' && (PTR)[1] == 'm' \ - && (PTR)[2] == 'p' && (PTR)[3] == 'm') \ - { fprintf ((FILE), "cmp"); (PTR) += 4; } \ - else if ((PTR)[0] == 'd' && (PTR)[1] == 'i' \ - && (PTR)[2] == 'v' && (PTR)[3] == 's' \ - && (PTR)[4] == 'l') \ - { fprintf ((FILE), "tdivs"); (PTR) += 5; } \ - else if ((PTR)[0] == 'd' && (PTR)[1] == 'i' \ - && (PTR)[2] == 'v' && (PTR)[3] == 'u' \ - && (PTR)[4] == 'l') \ - { fprintf ((FILE), "tdivu"); (PTR) += 5; } \ - else if ((PTR)[0] == 'f' && (PTR)[1] == 't' \ - && (PTR)[2] == 's' && (PTR)[3] == 't') \ - { fprintf ((FILE), "ftest"); (PTR) += 4; } \ - else if ((PTR)[0] == 'f' && (PTR)[1] == 'm' \ - && (PTR)[2] == 'o' && (PTR)[3] == 'v' \ - && (PTR)[4] == 'e') \ - { fprintf ((FILE), "fmov"); (PTR) += 5; } \ -} - - - -/* Override parts of m68k.h to fit the Tower assembler. - This section needs to track changes done to m68k.h in the future. */ - -#undef TARGET_VERSION -#define TARGET_VERSION fprintf (stderr, " (68k, Motorola/SGS/Tower32 syntax)"); - -#undef FUNCTION_PROFILER -#define FUNCTION_PROFILER(FILE, LABEL_NO) \ - fprintf (FILE, "\tmov.l &LP%%%d,%%a0\n\tjsr mcount%%\n", (LABEL_NO)) - -#undef FUNCTION_EXTRA_EPILOGUE -#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) \ -{ if (current_function_returns_pointer \ - && ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode)) \ - asm_fprintf (FILE, "\tmov.l %Rd0,%Ra0\n"); } - -/* This is how to output an insn to push a register on the stack. - It need not be very fast code. */ - -#undef ASM_OUTPUT_REG_PUSH -#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ - fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[REGNO]) - -/* This is how to output an insn to pop a register from the stack. - It need not be very fast code. */ - -#undef ASM_OUTPUT_REG_POP -#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ - fprintf (FILE, "\tmov.l (%%sp)+,%s\n", reg_names[REGNO]) - -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) \ -( fprintf (FILE, "#NO_APP\n"), \ - output_file_directive ((FILE), main_input_filename)) - -#undef TEXT_SECTION_ASM_OP -#define TEXT_SECTION_ASM_OP "\ttext" - -#undef DATA_SECTION_ASM_OP -#define DATA_SECTION_ASM_OP "\tdata" - -/* This says how to output an assembler line to define a global common symbol. - We use SIZE rather than ROUNDED, as this is what the native cc does. */ - -#undef ASM_OUTPUT_COMMON -#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -( fputs ("\tcomm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%d\n", ((SIZE) == 0) ? (int)(ROUNDED) : (int)(SIZE))) - -/* This says how to output an assembler line to define a local common symbol. - We use SIZE rather than ROUNDED, as this is what the native cc does. */ - -#undef ASM_OUTPUT_LOCAL -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -( fputs ("\tlcomm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%d\n", ((SIZE) == 0) ? (int)(ROUNDED) : (int)(SIZE))) - -#define ASM_PN_FORMAT "%s%%%%%lu" - -/* This is the command to make the user-level label named NAME - defined for reference from other files. */ - -#undef GLOBAL_ASM_OP -#define GLOBAL_ASM_OP "\tglobal\t" - -#undef ASM_GENERATE_INTERNAL_LABEL -#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ - sprintf ((LABEL), "%s%%%ld", (PREFIX), (long)(NUM)) - -#undef ASM_OUTPUT_CASE_LABEL -#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \ - fprintf (FILE, "\tswbeg &%d\n%s%%%d:\n", \ - XVECLEN (PATTERN (TABLE), 1), (PREFIX), (NUM)); \ - -#undef ASM_OUTPUT_ADDR_VEC_ELT -#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ - fprintf (FILE, "\tlong L%%%d\n", (VALUE)) - -#undef ASM_OUTPUT_ADDR_DIFF_ELT -#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ - fprintf (FILE, "\tshort L%%%d-L%%%d\n", (VALUE), (REL)) - -#undef ASM_OUTPUT_ALIGN -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ -do { \ - if ((LOG) == 1) \ - fprintf (FILE, "\teven\n"); \ - else if ((LOG) != 0) \ - abort (); \ -} while (0) - -#undef ASM_OUTPUT_SKIP -#define ASM_OUTPUT_SKIP(FILE,SIZE) \ - fprintf (FILE, "\tspace %d\n", (int)(SIZE)) - -/* Output a float value (represented as a C double) as an immediate operand. - This macro is a 68k-specific macro. */ - -#undef ASM_OUTPUT_FLOAT_OPERAND -#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ - do { long l; \ - REAL_VALUE_TO_TARGET_SINGLE (r, l); \ - /* Use hex representation even if CODE is f. as needs it. */ \ - fprintf ((FILE), "&0x%lx", l); \ - } while (0) - -/* Output a double value (represented as a C double) as an immediate operand. - This macro is a 68k-specific macro. */ -#undef ASM_OUTPUT_DOUBLE_OPERAND -#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ - do { long l[2]; \ - REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ - fprintf ((FILE), "&0x%lx%08lx", l[0], l[1]); \ - } while (0) - -#if 0 -#undef PRINT_OPERAND -#define PRINT_OPERAND(FILE, X, CODE) \ -{ if (CODE == '.') fprintf (FILE, "."); \ - else if (CODE == '#') fprintf (FILE, "&"); \ - else if (CODE == '-') fprintf (FILE, "-(%%sp)"); \ - else if (CODE == '+') fprintf (FILE, "(%%sp)+"); \ - else if (CODE == '@') fprintf (FILE, "(%%sp)"); \ - else if (CODE == '!') fprintf (FILE, "%%fpcr"); \ - else if (CODE == '/') \ - fprintf (FILE, "%%"); \ - else if (CODE == '$') { if (TARGET_68040_ONLY) fprintf (FILE, "s"); } \ - else if (CODE == '&') { if (TARGET_68040_ONLY) fprintf (FILE, "d"); } \ - else if (GET_CODE (X) == REG) \ - fprintf (FILE, "%s", reg_names[REGNO (X)]); \ - else if (GET_CODE (X) == MEM) \ - output_address (XEXP (X, 0)); \ - else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ - { REAL_VALUE_TYPE r; long l; \ - REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ - REAL_VALUE_TO_TARGET_SINGLE (r, l); \ - fprintf (FILE, "&0x%lx", l); } \ - else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode) \ - { REAL_VALUE_TYPE r; int i[2]; \ - REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ - REAL_VALUE_TO_TARGET_DOUBLE (r, i); \ - fprintf (FILE, "&0x%x%08x", i[0], i[1]); } \ - else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode) \ - { REAL_VALUE_TYPE r; \ - REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ - ASM_OUTPUT_LONG_DOUBLE_OPERAND (FILE, r); } \ - else { putc ('&', FILE); output_addr_const (FILE, X); }} -#endif - -/* Note that this contains a kludge that knows that the only reason - we have an address (plus (label_ref...) (reg...)) - is in the insn before a tablejump, and we know that the table is - exactly 10 bytes away. */ - -#undef PRINT_OPERAND_ADDRESS -#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -{ register rtx reg1, reg2, breg, ireg; \ - register rtx addr = ADDR; \ - rtx offset; \ - switch (GET_CODE (addr)) \ - { \ - case REG: \ - fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \ - break; \ - case PRE_DEC: \ - fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \ - break; \ - case POST_INC: \ - fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \ - break; \ - case PLUS: \ - reg1 = 0; reg2 = 0; \ - ireg = 0; breg = 0; \ - offset = 0; \ - if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ - { \ - offset = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ - { \ - offset = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - if (GET_CODE (addr) != PLUS) ; \ - else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ - { \ - reg1 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ - { \ - reg1 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - else if (GET_CODE (XEXP (addr, 0)) == MULT) \ - { \ - reg1 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == MULT) \ - { \ - reg1 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - else if (GET_CODE (XEXP (addr, 0)) == REG) \ - { \ - reg1 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == REG) \ - { \ - reg1 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ - || GET_CODE (addr) == SIGN_EXTEND) \ - { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ -/* for OLD_INDEXING \ - else if (GET_CODE (addr) == PLUS) \ - { \ - if (GET_CODE (XEXP (addr, 0)) == REG) \ - { \ - reg2 = XEXP (addr, 0); \ - addr = XEXP (addr, 1); \ - } \ - else if (GET_CODE (XEXP (addr, 1)) == REG) \ - { \ - reg2 = XEXP (addr, 1); \ - addr = XEXP (addr, 0); \ - } \ - } \ - */ \ - if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ - if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ - || GET_CODE (reg1) == MULT)) \ - || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ - { breg = reg2; ireg = reg1; } \ - else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ - { breg = reg1; ireg = reg2; } \ - if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ - { int scale = 1; \ - if (GET_CODE (ireg) == MULT) \ - { scale = INTVAL (XEXP (ireg, 1)); \ - ireg = XEXP (ireg, 0); } \ - if (GET_CODE (ireg) == SIGN_EXTEND) \ - fprintf (FILE, "10(%%pc,%s.w", \ - reg_names[REGNO (XEXP (ireg, 0))]); \ - else \ - fprintf (FILE, "10(%%pc,%s.l", \ - reg_names[REGNO (ireg)]); \ - if (scale != 1) fprintf (FILE, "*%d", scale); \ - putc (')', FILE); \ - break; } \ - if (ireg != 0 || breg != 0) \ - { int scale = 1; \ - if (breg == 0) \ - abort (); \ - if (addr != 0) \ - output_addr_const (FILE, addr); \ - fprintf (FILE, "(%s", reg_names[REGNO (breg)]); \ - if (ireg != 0) \ - putc (',', FILE); \ - if (ireg != 0 && GET_CODE (ireg) == MULT) \ - { scale = INTVAL (XEXP (ireg, 1)); \ - ireg = XEXP (ireg, 0); } \ - if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ - fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \ - else if (ireg != 0) \ - fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \ - if (scale != 1) fprintf (FILE, "*%d", scale); \ - putc (')', FILE); \ - break; \ - } \ - else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ - { fprintf (FILE, "10(%%pc,%s.w)", \ - reg_names[REGNO (reg1)]); \ - break; } \ - default: \ - output_addr_const (FILE, addr); \ - }} - - - -/* Override usual definitions of SDB output macros. - These definitions differ only in the absence of the period - at the beginning of the name of the directive - and in the use of `~' as the symbol for the current location. */ - -#define PUT_SDB_SCL(a) fprintf(asm_out_file, "\tscl\t%d;", (a)) -#define PUT_SDB_INT_VAL(a) fprintf (asm_out_file, "\tval\t%d;", (a)) -#define PUT_SDB_VAL(a) \ -( fputs ("\tval\t", asm_out_file), \ - output_addr_const (asm_out_file, (a)), \ - fputc (';', asm_out_file)) - -#define PUT_SDB_DEF(a) \ -do { fprintf (asm_out_file, "\tdef\t"); \ - ASM_OUTPUT_LABELREF (asm_out_file, a); \ - fprintf (asm_out_file, ";"); } while (0) - -#define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s;",a) -#define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file) -#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o;", a) -#define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d;", a) -#define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t") -#define PUT_SDB_NEXT_DIM(a) fprintf(asm_out_file, "%d,", a) -#define PUT_SDB_LAST_DIM(a) fprintf(asm_out_file, "%d;", a) - -#define PUT_SDB_TAG(a) \ -do { fprintf (asm_out_file, "\ttag\t"); \ - ASM_OUTPUT_LABELREF (asm_out_file, a); \ - fprintf (asm_out_file, ";"); } while (0) - -#define PUT_SDB_BLOCK_START(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~bb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_BLOCK_END(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~eb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_FUNCTION_START(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~bf;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_FUNCTION_END(LINE) \ - fprintf (asm_out_file, \ - "\tdef\t~ef;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ - (LINE)) - -#define PUT_SDB_EPILOGUE_END(NAME) \ - fprintf (asm_out_file, \ - "\tdef\t%s;\tval\t~;\tscl\t-1;\tendef\n", \ - (NAME)) - -#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ - sprintf ((BUFFER), "~%dfake", (NUMBER)); - -#define NO_DOLLAR_IN_LABEL -#define NO_DOT_IN_LABEL - -/* The usual definitions don't work because neither $ nor . is allowed. */ -#define CONSTRUCTOR_NAME_FORMAT "_GLOBAL_%%I\%%%s" - -/* Define a few machine-specific details - of the implementation of constructors. - - The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN - and CTOR_LIST_END to contribute to the .init section an instruction to - push a word containing 0 (or some equivalent of that). */ - -#undef INIT_SECTION_ASM_OP -#define INIT_SECTION_ASM_OP "\tsection\t~init" -#undef FINI_SECTION_ASM_OP -#define FINI_SECTION_ASM_OP "\tsection\t~fini" -#undef READONLY_DATA_SECTION_ASM_OP -#define READONLY_DATA_SECTION_ASM_OP "\tsection\t~rodata" - -#define CTOR_LIST_BEGIN \ - asm (INIT_SECTION_ASM_OP); \ - asm ("clr.l -(%sp)") -#define CTOR_LIST_END CTOR_LIST_BEGIN - -#define BSS_SECTION_ASM_OP "\tsection\t~bss" - -#define TARGET_ASM_CONSTRUCTOR m68k_svr3_asm_out_constructor diff --git a/gcc/config/m68k/tower.h b/gcc/config/m68k/tower.h deleted file mode 100644 index 7ae1a9ec282..00000000000 --- a/gcc/config/m68k/tower.h +++ /dev/null @@ -1,104 +0,0 @@ -/* Definitions of target machine for GNU compiler. - Copyright (C) 1990, 1994, 1996 Free Software Foundation, Inc. - Contributed by Robert Andersson, International Systems, Oslo, ra@intsys.no. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* For NCR Tower 32/4x0 and 32/6x0 running System V Release 3. I don't have - access to 200/700/800/850 machines, so I don't know if it works on those - as well. It shouldn't be far from it however. The hardware floating point - support is completely untested, as I do not have access to a machine with - a 6888x FPU in it. It does not work on the System V Release 2 based OS - releases. Making it work will not be easy, due to the silly way in which - stack expansion is implemented in the OS. - - This file is included in tower-as.h. - Do *NOT* include this file directly. */ - - -#include "m68k/m68k.h" - -#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020) - -/* Don't try using XFmode. */ -#undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* Names to predefine in the preprocessor for this target machine. */ - -#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_200 -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k" - -#if 0 /* It is incorrect to test these symbols. - They describe the host, not the target. - It should not matter which model is specified. */ -#ifdef tower32_600 -#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_600 -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k" -#endif -#ifdef tower32_700 -#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_700 -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k" -#endif -#ifdef tower32_800 -#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_800 -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k" -#endif -#ifdef tower32_850 -#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_850 -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k" -#endif -#endif - -/* The startfiles and libraries depend on the -p and -m68881 options. - The Tower does not support the -pg option. */ - -#define LINK_SPEC \ -"%{p:%{m68881:-L/usr/lib/fp/libp} -L/usr/lib/libp} \ - %{m68881:-L/usr/lib/fp}" - -#define LIB_SPEC \ -"%{shlib:-lc_s} -lc crtend.o%s crtn.o%s" - -#define STARTFILE_SPEC \ -"%{p:mcrt1.o%s} %{!p:crt1.o%s} crtbegin.o%s" - -/* Use mem* functions, recognize #ident lines. */ - -#define TARGET_MEM_FUNCTIONS -#define IDENT_DIRECTIVE - -/* Every structure and union's size must be a multiple of two bytes. */ - -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* All register names should have a leading % character. */ - -#undef REGISTER_NAMES -#define REGISTER_NAMES \ -{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ - "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \ - "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"} - -#undef REGISTER_PREFIX -#define REGISTER_PREFIX "%" - -#undef IMMEDIATE_PREFIX -#define IMMEDIATE_PREFIX "&" - -/* The prefix to add to user-visible assembler symbols. */ - -/* We do not want leading underscores. */ - -#undef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "" diff --git a/gcc/config/m88k/aout-dbx.h b/gcc/config/m88k/aout-dbx.h deleted file mode 100644 index 4eef7d685ba..00000000000 --- a/gcc/config/m88k/aout-dbx.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Configuration fragment for an m88k OpenBSD target. - Copyright (C) 2000 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - - -/* a.out with DBX. */ -#define DBX_DEBUGGING_INFO 1 -#define DEFAULT_GDB_EXTENSIONS 0 - diff --git a/gcc/config/m88k/m88k-aout.h b/gcc/config/m88k/m88k-aout.h deleted file mode 100644 index 50ea8dd3da7..00000000000 --- a/gcc/config/m88k/m88k-aout.h +++ /dev/null @@ -1,32 +0,0 @@ -/* Definitions for "naked" Motorola 88k using a.out object format files - and stabs debugging info. - - Copyright (C) 1994 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#undef SDB_DEBUGGING_INFO -#define DBX_DEBUGGING_INFO 1 - -#include "m88k/m88k.h" -#include "aoutos.h" - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dm88000 -Dm88k -Acpu=m88k -Amachine=m88k" - -/* end of m88k-aout.h */ diff --git a/gcc/config/m88k/m88k-modes.def b/gcc/config/m88k/m88k-modes.def deleted file mode 100644 index b5edc6cb82e..00000000000 --- a/gcc/config/m88k/m88k-modes.def +++ /dev/null @@ -1,27 +0,0 @@ -/* Definitions of target machine for GNU compiler for Motorola m88100. - Copyright (C) 2002 Free Software Foundation, Inc. - Contributed by Michael Tiemann (tiemann@cygnus.com). - Currently maintained by (gcc@dg-rtp.dg.com) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* Extra machine modes to represent the condition code. */ - -CC (CCEVEN) - - diff --git a/gcc/config/m88k/m88k-move.sh b/gcc/config/m88k/m88k-move.sh deleted file mode 100755 index 874bc364ae5..00000000000 --- a/gcc/config/m88k/m88k-move.sh +++ /dev/null @@ -1,306 +0,0 @@ -#!/bin/sh -# -# If your shell doesn't support functions (true for some BSD users), -# you might try using GNU's bash. -# -#ident "@(#) m88k-move.sh 1-Sep-92" -# -# This file provided by Data General, February 1990. -# -# This script generates the necessary movstr library functions -# for the m88100. These functions are called from the expansion -# of movstrsi. There are eight modules created by this script, -# each with multiple entry points. One module, moveSI64n -# implements a word aligned loop; the other modules, moveXINx -# implement a straight line copy of N bytes in mode XI. -# -# By analysis of the best memcpy function, it can be determined -# what appear to be certain magic numbers. For example, a -# memcpy of 13 bytes, where the pointers are determined at run -# time to be word aligned takes 28 cycles. A call to -# __movstrQI13x13 also takes 28 cycles. The break even point -# for a HImode copy is 38 bytes. Just to be on the safe side, -# these are bumped to 16 and 48 respectively. -# -# The smaller, odd-remainder modules are provided to help -# mitigate the overhead of copying the last bytes. -# -# Changes to these functions should not be taken lightly if you -# want to be able to link programs built with older movstr -# parameters. -# -#.Revision History -# -# 1-Sep-92 Stan Cox Added moveDI96x, moveDI41x through moveDI47x. -# 2-Jan-92 Tom Wood Renamed files to comply with SVR3 14 char limit. -# 26-Oct-90 Tom Wood Delete movstr.h; moved to out-m88k.c. -# 17-Oct-90 Tom Wood Files are named *.asm rather than *.s. -# 11-Sep-90 Jeffrey Friedl -# On my BSD 4.3 awk and my GNU-awk, only the -# first character of an argument to -F is passed -# through, so I can't get this to work. -# 5-Sep-90 Ray Essick/Tom Wood -# Added a -no-tdesc option. -# 27-Aug-90 Vince Guarna/Tom Wood -# Version 3 assembler syntax (-abi). -# 16-Aug-90 Ron Guilmette -# Avoid problems on a SPARC. The common -# denominator among shells seems to be '...\' -# rather than '...\\'. -# 15-Aug-90 Ron Guilmette -# Avoid awk syntax errors on a Sun by not using -# the `!' operator. -# 22-Feb-90 Tom Wood Created. -# 20-Jun-90 Tom Wood Emit file directives. -# -#.End]=--------------------------------------------------------------*/ - -usage() { - echo "usage: $0 [ -abi ] [ -no-tdesc ]" 1>&2 - exit 1 -} - -awk_flag="-F:"; -awk_begin="BEGIN { " -ps=""; us="_"; tf="x"; la="@L"; fb="8"; nt=""; -do_file() { - echo " file $1"; -} - -while [ $# -gt 0 ] ; do - case $1 in - -no-tdesc) awk_begin="$awk_begin no_tdesc=1;" - nt=";";; - -abi) awk_begin="$awk_begin abi=1;" - ps="#"; us=""; tf="a"; la=".L"; fb="16"; - do_file() { - echo ' version "03.00"'; - echo " file $1"; - };; - *) usage;; - esac - shift -done - -rm -f move?I*[xn].s move?I*[xn].asm - -#.Implementation_continued[=----------------------------------------------- -# -# This generates the word aligned loop. The loop is entered -# from the callable entry points ___movstrSI64nN, where at -# least N bytes will be copied. r2 is the destination pointer -# offset by 4, r3 is the source pointer offset by 4, r6 is the -# loop count. Thus, the total bytes moved is 64 * r6 + N. The -# first value is preloaded into r4 or r5 (r4 if N/4 is odd; -# r5 if N/4 is even). Upon returning, r2 and r3 have been -# updated and may be used for the remainder bytes to move. -# -# The code for this loop is generated by the awk program -# following. Edit *it*, not what it generates! -# -#.End]=------------------------------------------------------------------*/ - -gen_movstrN() { - awk $awk_flag "$awk_begin"' - if (abi) { - ps="#"; us=""; tf="a"; la=".L"; fb=16; - } else { - ps=""; us="_"; tf="x"; la="@L"; fb=8; - } - } - NR == 1 && NF == 4 { - mode = $1; suffix = $2; align = $3; count = $4; - ld = align; st = 0; - - printf "; The following was calculated using awk.\n"; - printf "\ttext\n"; - printf "\talign\t%d\n", fb; - printf "%sloop%s%d:\n", la, mode, count * align; - printf "\taddu\t%sr3,%sr3,%d\n", ps, ps, count * align; - printf "\taddu\t%sr2,%sr2,%d\n", ps, ps, count * align; - printf "\tsubu\t%sr6,%sr6,1\n", ps, ps; - for (r = count + 1; r >= 1; r--) { - evenp = r % 2; - name = sprintf("__%smovstr%s%dn%d", us, mode, count * align, r * align); - if (r > 1) { - printf "\tglobal\t%s\n", name; - printf "%s:\n", name; - } - if (r > 2) { - printf "\tld%s\t%sr%d,%sr3,%d\n", suffix, ps, 4 + evenp, ps, ld; - printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, 5 - evenp, ps, st; - } else if (r == 2) { - printf "\tld%s\t%sr%d,%sr3,%d\n", suffix, ps, 4 + evenp, ps, ld; - printf "\tbcnd.n\t%sgt0,%sr6,%sloop%s%d\n", ps, ps, la, mode, count * align; - printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, 5 - evenp, ps, st; - printf "\tjmp.n\t%sr1\n", ps; - } else { - printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, 5 - evenp, ps, st; - } - ld += align; st += align; - } - if (!no_tdesc) { - printf "%send%s%d:\n", la, mode, count * align; - printf "\tsection\t.tdesc,\"%s\"\n", tf; - printf "\tword\t0x42,1,%sloop%s%d", la, mode, count * align; - printf ",%send%s%d\n", la, mode, count * align; - printf "\tword\t0x0100001f,0,1,0\n"; - printf "\ttext\n"; - } - printf "; End of awk generated code.\n"; - exit; - }' -} - -(do_file '"movstrSI64n.s"'; - echo 'SI::4:16' | gen_movstrN) > moveSI64n.asm - -#.Implementation_continued[=----------------------------------------------- -# -# This generates the even-remainder, straight-line modules. -# The code is entered from the callable entry points -# ___movstrXINxM, where exactly M bytes will be copied in XI -# mode. r2 is the destination pointer, r3 is the source -# pointer, neither being offset. The first value is preloaded -# into r4 or r5 (r4 if M-N/B is even; r5 if M-N/B is odd, where -# B is the mode size of XI). Upon returning, r2 and r3 have not -# been changed. -# -# The code for these cases is generated by the awk program -# following. Edit *it*, not what it generates! -# -#.End]=------------------------------------------------------------------*/ - -gen_movstrX0() { - awk $awk_flag "$awk_begin"' - if (abi) { - ps="#"; us=""; tf="a"; la=".L"; fb=16; - } else { - ps=""; us="_"; tf="x"; la="@L"; fb=8; - } - } - NR == 1 && NF == 4 { - mode = $1; suffix = $2; align = $3; bytes = $4; - ld = align; st = 0; count = bytes / align; - reg[0] = 4; if (align == 8) reg[1] = 6; else reg[1] = 5; - printf "; The following was calculated using awk.\n"; - printf "\ttext\n"; - printf "\talign\t%d\n", fb; - for (r = count; r >= 1; r--) { - evenp = r % 2; - name = sprintf("__%smovstr%s%dx%d", us, mode, count * align, r * align); - if (r > 1) { - printf "\tglobal\t%s\n", name; - printf "%s:\n", name; - } - if (r == 1) - printf "\tjmp.n\t%sr1\n", ps; - else - printf "\tld%s\t%sr%d,%sr3,%d\n", suffix, ps, reg[evenp], ps, ld; - printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, reg[1-evenp], ps, st; - ld += align; st += align; - } - if (!no_tdesc) { - printf "%send%s%dx:\n", la, mode, count * align; - printf "\tsection\t.tdesc,\"%s\"\n", tf; - printf "\tword\t0x42,1,__%smovstr%s%dx%d", us, mode, count * align, count * align; - printf ",%send%s%dx\n", la, mode, count * align; - printf "\tword\t0x0100001f,0,1,0\n"; - printf "\ttext\n"; - } - printf "; End of awk generated code.\n" - exit; - }' -} - -(do_file '"movstrQI16x.s"'; - echo 'QI:.b:1:16' | gen_movstrX0) > moveQI16x.asm -(do_file '"movstrHI48x.s"'; - echo 'HI:.h:2:48' | gen_movstrX0) > moveHI48x.asm -(do_file '"movstrSI96x.s"'; - echo 'SI::4:96' | gen_movstrX0) > moveSI96x.asm -(do_file '"movstrDI96x.s"'; - echo 'DI:.d:8:96' | gen_movstrX0) > moveDI96x.asm - -#.Implementation_continued[=----------------------------------------------- -# -# This generates the odd-remainder, straight-line modules. The -# interface is the same as that for the even-remainder modules. -# -#.End]=------------------------------------------------------------------*/ - -gen_movstrXr() { - awk $awk_flag "$awk_begin"' - if (abi) { - ps="#"; us=""; tf="a"; la=".L"; fb=16; - } else { - ps=""; us="_"; tf="x"; la="@L"; fb=8; - } - } - NR == 1 && NF == 4 { - mode = $1; rem = $2; most = $3; count = $4; - suffix[1] = ".b"; suffix[2] = ".h"; suffix[4] = ""; suffix[8] = ".d"; - - prev = align = most; - ld = align; st = 0; total = count - rem - most; - evenp = int(total/align) % 2; - reg[0] = 4; if (align == 8) reg[1] = 6; else reg[1] = 5; - printf "; The following was calculated using awk.\n"; - printf "\ttext\n"; - printf "\talign\t%d\n", fb; - for (bytes = total; bytes >= 0; bytes -= align) { - if (bytes < align) { - if (bytes >= 4) align = 4; - else if (bytes >= 2) align = 2; - else align = 1; - } - name = sprintf("__%smovstr%s%dx%d", us, mode, total + most, bytes + most); - if (bytes > most) { - printf "\tglobal\t%s\n", name; - printf "%s:\n", name; - } - if (bytes == 0) - printf "\tjmp.n\t%sr1\n", ps; - else - printf "\tld%s\t%sr%d,%sr3,%d\n", suffix[align], ps, reg[evenp], ps, ld; - printf "\tst%s\t%sr%d,%sr2,%d\n", suffix[prev], ps, reg[1-evenp], ps, st; - ld += align; st += prev; prev = align; - evenp = 1 - evenp; - } - if (!no_tdesc) { - printf "%send%s%dx:\n", la, mode, total + most; - printf "\tsection\t.tdesc,\"%s\"\n", tf; - printf "\tword\t0x42,1,__%smovstr%s%dx%d", us, mode, total + most, total + most; - printf ",%send%s%dx\n", la, mode, total + most; - printf "\tword\t0x0100001f,0,1,0\n"; - printf "\ttext\n"; - } - printf "; End of awk generated code.\n" - exit; - }' -} - -(do_file '"movstrDI47x.s"'; - echo 'DI:1:8:48' | gen_movstrXr) > moveDI47x.asm -(do_file '"movstrDI46x.s"'; - echo 'DI:2:8:48' | gen_movstrXr) > moveDI46x.asm -(do_file '"movstrDI45x.s"'; - echo 'DI:3:8:48' | gen_movstrXr) > moveDI45x.asm -(do_file '"movstrDI44x.s"'; - echo 'DI:4:8:48' | gen_movstrXr) > moveDI44x.asm -(do_file '"movstrDI43x.s"'; - echo 'DI:5:8:48' | gen_movstrXr) > moveDI43x.asm -(do_file '"movstrDI42x.s"'; - echo 'DI:6:8:48' | gen_movstrXr) > moveDI42x.asm -(do_file '"movstrDI41x.s"'; - echo 'DI:7:8:48' | gen_movstrXr) > moveDI41x.asm - -(do_file '"movstrSI47x.s"'; - echo 'SI:1:4:48' | gen_movstrXr) > moveSI47x.asm -(do_file '"movstrSI46x.s"'; - echo 'SI:2:4:48' | gen_movstrXr) > moveSI46x.asm -(do_file '"movstrSI45x.s"'; - echo 'SI:3:4:48' | gen_movstrXr) > moveSI45x.asm - -(do_file '"movstrHI15x.s"'; - echo 'HI:1:2:16' | gen_movstrXr) > moveHI15x.asm diff --git a/gcc/config/m88k/m88k-protos.h b/gcc/config/m88k/m88k-protos.h deleted file mode 100644 index b7bba671916..00000000000 --- a/gcc/config/m88k/m88k-protos.h +++ /dev/null @@ -1,102 +0,0 @@ -/* Definitions of target machine for GNU compiler for - Motorola m88100 in an 88open OCS/BCS environment. - Copyright (C) 2000 Free Software Foundation, Inc. - Contributed by Michael Tiemann (tiemann@cygnus.com). - Currently maintained by (gcc@dg-rtp.dg.com) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifdef RTX_CODE -extern int m88k_debugger_offset PARAMS ((rtx, int)); -extern void emit_bcnd PARAMS ((enum rtx_code, rtx)); -extern void expand_block_move PARAMS ((rtx, rtx, rtx *)); -extern void print_operand PARAMS ((FILE *, rtx, int)); -extern void print_operand_address PARAMS ((FILE *, rtx)); -extern const char *output_load_const_int PARAMS ((enum machine_mode, rtx *)); -extern const char *output_load_const_float PARAMS ((rtx *)); -extern const char *output_load_const_double PARAMS ((rtx *)); -extern const char *output_load_const_dimode PARAMS ((rtx *)); -extern const char *output_and PARAMS ((rtx[])); -extern const char *output_ior PARAMS ((rtx[])); -extern const char *output_xor PARAMS ((rtx[])); -extern const char *output_call PARAMS ((rtx[], rtx)); - -extern struct rtx_def *emit_test PARAMS ((enum rtx_code, enum machine_mode)); -extern struct rtx_def *legitimize_address PARAMS ((int, rtx, rtx, rtx)); -extern struct rtx_def *legitimize_operand PARAMS ((rtx, enum machine_mode)); - -extern int pic_address_needs_scratch PARAMS ((rtx)); -extern int symbolic_address_p PARAMS ((rtx)); -extern int condition_value PARAMS ((rtx)); -extern int emit_move_sequence PARAMS ((rtx *, enum machine_mode, rtx)); -extern int mostly_false_jump PARAMS ((rtx, rtx)); -extern int real_power_of_2_operand PARAMS ((rtx, enum machine_mode)); -extern int move_operand PARAMS ((rtx, enum machine_mode)); -extern int call_address_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_0_operand PARAMS ((rtx, enum machine_mode)); -extern int arith_operand PARAMS ((rtx, enum machine_mode)); -extern int arith5_operand PARAMS ((rtx, enum machine_mode)); -extern int arith32_operand PARAMS ((rtx, enum machine_mode)); -extern int arith64_operand PARAMS ((rtx, enum machine_mode)); -extern int int5_operand PARAMS ((rtx, enum machine_mode)); -extern int int32_operand PARAMS ((rtx, enum machine_mode)); -extern int add_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_bbx_mask_operand PARAMS ((rtx, enum machine_mode)); -extern int real_or_0_operand PARAMS ((rtx, enum machine_mode)); -extern int partial_ccmode_register_operand PARAMS ((rtx, enum machine_mode)); -extern int relop PARAMS ((rtx, enum machine_mode)); -extern int even_relop PARAMS ((rtx, enum machine_mode)); -extern int odd_relop PARAMS ((rtx, enum machine_mode)); -extern int relop_no_unsigned PARAMS ((rtx, enum machine_mode)); -extern int equality_op PARAMS ((rtx, enum machine_mode)); -extern int pc_or_label_ref PARAMS ((rtx, enum machine_mode)); -extern int symbolic_operand PARAMS ((rtx, enum machine_mode)); -#ifdef TREE_CODE -extern void m88k_va_start PARAMS ((tree, rtx)); -#endif /* TREE_CODE */ -#endif /* RTX_CODE */ - -#ifdef ANSI_PROTOTYPES -struct m88k_lang_independent_options; -#endif -extern void output_file_start PARAMS ((FILE *, - const struct m88k_lang_independent_options *, - int, - const struct m88k_lang_independent_options *, - int)); - -extern int null_prologue PARAMS ((void)); -extern int integer_ok_for_set PARAMS ((unsigned)); -extern void m88k_layout_frame PARAMS ((void)); -extern void m88k_expand_prologue PARAMS ((void)); -extern void m88k_expand_epilogue PARAMS ((void)); -extern void output_function_profiler PARAMS ((FILE *, int, const char *, int)); -extern void output_ascii PARAMS ((FILE *, const char *, int, - const char *, int)); -extern void output_label PARAMS ((int)); -extern struct rtx_def *m88k_builtin_saveregs PARAMS ((void)); -extern enum m88k_instruction classify_integer PARAMS ((enum machine_mode, int)); -extern int mak_mask_p PARAMS ((int)); - -#ifdef TREE_CODE -extern struct rtx_def *m88k_function_arg PARAMS ((CUMULATIVE_ARGS, - enum machine_mode, tree, - int)); -extern struct rtx_def *m88k_va_arg PARAMS ((tree, tree)); -extern tree m88k_build_va_list PARAMS ((void)); -#endif /* TREE_CODE */ diff --git a/gcc/config/m88k/m88k.c b/gcc/config/m88k/m88k.c deleted file mode 100644 index a27d8a3acbe..00000000000 --- a/gcc/config/m88k/m88k.c +++ /dev/null @@ -1,3457 +0,0 @@ -/* Subroutines for insn-output.c for Motorola 88000. - Copyright (C) 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, - 2001, 2002, 2003 Free Software Foundation, Inc. - Contributed by Michael Tiemann (tiemann@mcc.com) - Currently maintained by (gcc@dg-rtp.dg.com) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#include "config.h" -#include "system.h" -#include "coretypes.h" -#include "tm.h" -#include "rtl.h" -#include "regs.h" -#include "hard-reg-set.h" -#include "real.h" -#include "insn-config.h" -#include "conditions.h" -#include "output.h" -#include "insn-attr.h" -#include "tree.h" -#include "function.h" -#include "expr.h" -#include "libfuncs.h" -#include "c-tree.h" -#include "flags.h" -#include "recog.h" -#include "toplev.h" -#include "tm_p.h" -#include "target.h" -#include "target-def.h" - -extern FILE *asm_out_file; - -const char *m88k_pound_sign = ""; /* Either # for SVR4 or empty for SVR3 */ -const char *m88k_short_data; -const char *m88k_version; -char m88k_volatile_code; - -unsigned m88k_gp_threshold = 0; -int m88k_prologue_done = 0; /* Ln directives can now be emitted */ -int m88k_function_number = 0; /* Counter unique to each function */ -int m88k_fp_offset = 0; /* offset of frame pointer if used */ -int m88k_stack_size = 0; /* size of allocated stack (including frame) */ -int m88k_case_index; - -rtx m88k_compare_reg; /* cmp output pseudo register */ -rtx m88k_compare_op0; /* cmpsi operand 0 */ -rtx m88k_compare_op1; /* cmpsi operand 1 */ - -enum processor_type m88k_cpu; /* target cpu */ - -static void m88k_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); -static void m88k_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); -static void m88k_output_function_end_prologue PARAMS ((FILE *)); -static void m88k_output_function_begin_epilogue PARAMS ((FILE *)); -#if defined (CTOR_LIST_BEGIN) && !defined (OBJECT_FORMAT_ELF) -static void m88k_svr3_asm_out_constructor PARAMS ((rtx, int)); -static void m88k_svr3_asm_out_destructor PARAMS ((rtx, int)); -#endif -static void m88k_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT)); -static int m88k_adjust_cost PARAMS ((rtx, rtx, rtx, int)); -static void m88k_encode_section_info PARAMS ((tree, rtx, int)); -#ifdef AS_BUG_DOT_LABELS -static void m88k_internal_label PARAMS ((FILE *, const char *, unsigned long)); -#endif -static bool m88k_rtx_costs PARAMS ((rtx, int, int, int *)); -static int m88k_address_cost PARAMS ((rtx)); - -/* Initialize the GCC target structure. */ -#undef TARGET_ASM_BYTE_OP -#define TARGET_ASM_BYTE_OP "\tbyte\t" -#undef TARGET_ASM_ALIGNED_HI_OP -#define TARGET_ASM_ALIGNED_HI_OP "\thalf\t" -#undef TARGET_ASM_ALIGNED_SI_OP -#define TARGET_ASM_ALIGNED_SI_OP "\tword\t" -#undef TARGET_ASM_UNALIGNED_HI_OP -#define TARGET_ASM_UNALIGNED_HI_OP "\tuahalf\t" -#undef TARGET_ASM_UNALIGNED_SI_OP -#define TARGET_ASM_UNALIGNED_SI_OP "\tuaword\t" - -#undef TARGET_ASM_FUNCTION_PROLOGUE -#define TARGET_ASM_FUNCTION_PROLOGUE m88k_output_function_prologue -#undef TARGET_ASM_FUNCTION_END_PROLOGUE -#define TARGET_ASM_FUNCTION_END_PROLOGUE m88k_output_function_end_prologue -#undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE -#define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE m88k_output_function_begin_epilogue -#undef TARGET_ASM_FUNCTION_EPILOGUE -#define TARGET_ASM_FUNCTION_EPILOGUE m88k_output_function_epilogue - -#undef TARGET_SCHED_ADJUST_COST -#define TARGET_SCHED_ADJUST_COST m88k_adjust_cost - -#undef TARGET_ENCODE_SECTION_INFO -#define TARGET_ENCODE_SECTION_INFO m88k_encode_section_info -#ifdef AS_BUG_DOT_LABELS -#undef TARGET_ASM_INTERNAL_LABEL -#define TARGET_ASM_INTERNAL_LABEL m88k_internal_label -#endif - -#undef TARGET_RTX_COSTS -#define TARGET_RTX_COSTS m88k_rtx_costs -#undef TARGET_ADDRESS_COST -#define TARGET_ADDRESS_COST m88k_address_cost - -struct gcc_target targetm = TARGET_INITIALIZER; - -/* Determine what instructions are needed to manufacture the integer VALUE - in the given MODE. */ - -enum m88k_instruction -classify_integer (mode, value) - enum machine_mode mode; - register int value; -{ - if (value == 0) - return m88k_zero; - else if (SMALL_INTVAL (value)) - return m88k_or; - else if (SMALL_INTVAL (-value)) - return m88k_subu; - else if (mode == HImode) - return m88k_or_lo16; - else if (mode == QImode) - return m88k_or_lo8; - else if ((value & 0xffff) == 0) - return m88k_oru_hi16; - else if (integer_ok_for_set (value)) - return m88k_set; - else - return m88k_oru_or; -} - -/* Return the bit number in a compare word corresponding to CONDITION. */ - -int -condition_value (condition) - rtx condition; -{ - switch (GET_CODE (condition)) - { - case EQ: return 2; - case NE: return 3; - case GT: return 4; - case LE: return 5; - case LT: return 6; - case GE: return 7; - case GTU: return 8; - case LEU: return 9; - case LTU: return 10; - case GEU: return 11; - default: abort (); - } -} - -int -integer_ok_for_set (value) - register unsigned value; -{ - /* All the "one" bits must be contiguous. If so, MASK + 1 will be - a power of two or zero. */ - register unsigned mask = (value | (value - 1)); - return (value && POWER_OF_2_or_0 (mask + 1)); -} - -const char * -output_load_const_int (mode, operands) - enum machine_mode mode; - rtx *operands; -{ - static const char *const patterns[] = - { "or %0,%#r0,0", - "or %0,%#r0,%1", - "subu %0,%#r0,%n1", - "or %0,%#r0,%h1", - "or %0,%#r0,%q1", - "set %0,%#r0,%s1", - "or.u %0,%#r0,%X1", - "or.u %0,%#r0,%X1\n\tor %0,%0,%x1", - }; - - if (! REG_P (operands[0]) - || GET_CODE (operands[1]) != CONST_INT) - abort (); - return patterns[classify_integer (mode, INTVAL (operands[1]))]; -} - -/* These next two routines assume that floating point numbers are represented - in a manner which is consistent between host and target machines. */ - -const char * -output_load_const_float (operands) - rtx *operands; -{ - /* These can return 0 under some circumstances when cross-compiling. */ - operands[0] = operand_subword (operands[0], 0, 0, SFmode); - operands[1] = operand_subword (operands[1], 0, 0, SFmode); - - return output_load_const_int (SImode, operands); -} - -const char * -output_load_const_double (operands) - rtx *operands; -{ - rtx latehalf[2]; - - /* These can return zero on some cross-compilers, but there's nothing - we can do about it. */ - latehalf[0] = operand_subword (operands[0], 1, 0, DFmode); - latehalf[1] = operand_subword (operands[1], 1, 0, DFmode); - - operands[0] = operand_subword (operands[0], 0, 0, DFmode); - operands[1] = operand_subword (operands[1], 0, 0, DFmode); - - output_asm_insn (output_load_const_int (SImode, operands), operands); - - operands[0] = latehalf[0]; - operands[1] = latehalf[1]; - - return output_load_const_int (SImode, operands); -} - -const char * -output_load_const_dimode (operands) - rtx *operands; -{ - rtx latehalf[2]; - - latehalf[0] = operand_subword (operands[0], 1, 0, DImode); - latehalf[1] = operand_subword (operands[1], 1, 0, DImode); - - operands[0] = operand_subword (operands[0], 0, 0, DImode); - operands[1] = operand_subword (operands[1], 0, 0, DImode); - - output_asm_insn (output_load_const_int (SImode, operands), operands); - - operands[0] = latehalf[0]; - operands[1] = latehalf[1]; - - return output_load_const_int (SImode, operands); -} - -/* Emit insns to move operands[1] into operands[0]. - - Return 1 if we have written out everything that needs to be done to - do the move. Otherwise, return 0 and the caller will emit the move - normally. - - SCRATCH if nonzero can be used as a scratch register for the move - operation. It is provided by a SECONDARY_RELOAD_* macro if needed. */ - -int -emit_move_sequence (operands, mode, scratch) - rtx *operands; - enum machine_mode mode; - rtx scratch; -{ - register rtx operand0 = operands[0]; - register rtx operand1 = operands[1]; - - if (CONSTANT_P (operand1) && flag_pic - && pic_address_needs_scratch (operand1)) - operands[1] = operand1 = legitimize_address (1, operand1, 0, 0); - - /* Handle most common case first: storing into a register. */ - if (register_operand (operand0, mode)) - { - if (register_operand (operand1, mode) - || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1)) - || GET_CODE (operand1) == HIGH - /* Only `general_operands' can come here, so MEM is ok. */ - || GET_CODE (operand1) == MEM) - { - /* Run this case quickly. */ - emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); - return 1; - } - } - else if (GET_CODE (operand0) == MEM) - { - if (register_operand (operand1, mode) - || (operand1 == const0_rtx && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)) - { - /* Run this case quickly. */ - emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); - return 1; - } - if (! reload_in_progress && ! reload_completed) - { - operands[0] = validize_mem (operand0); - operands[1] = operand1 = force_reg (mode, operand1); - } - } - - /* Simplify the source if we need to. */ - if (GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) - { - if (GET_CODE (operand1) != CONST_INT - && GET_CODE (operand1) != CONST_DOUBLE) - { - rtx temp = ((reload_in_progress || reload_completed) - ? operand0 : 0); - operands[1] = legitimize_address (flag_pic - && symbolic_address_p (operand1), - operand1, temp, scratch); - if (mode != SImode) - operands[1] = gen_rtx_SUBREG (mode, operands[1], 0); - } - } - - /* Now have insn-emit do whatever it normally does. */ - return 0; -} - -/* Return a legitimate reference for ORIG (either an address or a MEM) - using the register REG. If PIC and the address is already - position-independent, use ORIG. Newly generated position-independent - addresses go into a reg. This is REG if nonzero, otherwise we - allocate register(s) as necessary. If this is called during reload, - and we need a second temp register, then we use SCRATCH, which is - provided via the SECONDARY_INPUT_RELOAD_CLASS mechanism. */ - -struct rtx_def * -legitimize_address (pic, orig, reg, scratch) - int pic; - rtx orig; - rtx reg; - rtx scratch; -{ - rtx addr = (GET_CODE (orig) == MEM ? XEXP (orig, 0) : orig); - rtx new = orig; - rtx temp, insn; - - if (pic) - { - if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) - { - if (reg == 0) - { - if (reload_in_progress || reload_completed) - abort (); - else - reg = gen_reg_rtx (Pmode); - } - - if (flag_pic == 2) - { - /* If not during reload, allocate another temp reg here for - loading in the address, so that these instructions can be - optimized properly. */ - temp = ((reload_in_progress || reload_completed) - ? reg : gen_reg_rtx (Pmode)); - - emit_insn (gen_rtx_SET - (VOIDmode, temp, - gen_rtx_HIGH (SImode, - gen_rtx_UNSPEC (SImode, - gen_rtvec (1, addr), - 0)))); - - emit_insn (gen_rtx_SET - (VOIDmode, temp, - gen_rtx_LO_SUM (SImode, temp, - gen_rtx_UNSPEC (SImode, - gen_rtvec (1, addr), - 0)))); - addr = temp; - } - - new = gen_rtx_MEM (Pmode, - gen_rtx_PLUS (SImode, - pic_offset_table_rtx, addr)); - - current_function_uses_pic_offset_table = 1; - RTX_UNCHANGING_P (new) = 1; - insn = emit_move_insn (reg, new); - /* Put a REG_EQUAL note on this insn, so that it can be optimized - by loop. */ - REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, - REG_NOTES (insn)); - new = reg; - } - else if (GET_CODE (addr) == CONST) - { - rtx base; - - if (GET_CODE (XEXP (addr, 0)) == PLUS - && XEXP (XEXP (addr, 0), 0) == pic_offset_table_rtx) - return orig; - - if (reg == 0) - { - if (reload_in_progress || reload_completed) - abort (); - else - reg = gen_reg_rtx (Pmode); - } - - if (GET_CODE (XEXP (addr, 0)) != PLUS) abort (); - - base = legitimize_address (1, XEXP (XEXP (addr, 0), 0), reg, 0); - addr = legitimize_address (1, XEXP (XEXP (addr, 0), 1), - base == reg ? 0 : reg, 0); - - if (GET_CODE (addr) == CONST_INT) - { - if (ADD_INT (addr)) - return plus_constant (base, INTVAL (addr)); - else if (! reload_in_progress && ! reload_completed) - addr = force_reg (Pmode, addr); - /* We can't create any new registers during reload, so use the - SCRATCH reg provided by the reload_insi pattern. */ - else if (scratch) - { - emit_move_insn (scratch, addr); - addr = scratch; - } - else - /* If we reach here, then the SECONDARY_INPUT_RELOAD_CLASS - macro needs to be adjusted so that a scratch reg is provided - for this address. */ - abort (); - } - new = gen_rtx_PLUS (SImode, base, addr); - /* Should we set special REG_NOTEs here? */ - } - } - else if (! SHORT_ADDRESS_P (addr, temp)) - { - if (reg == 0) - { - if (reload_in_progress || reload_completed) - abort (); - else - reg = gen_reg_rtx (Pmode); - } - - emit_insn (gen_rtx_SET (VOIDmode, - reg, gen_rtx_HIGH (SImode, addr))); - new = gen_rtx_LO_SUM (SImode, reg, addr); - } - - if (new != orig - && GET_CODE (orig) == MEM) - { - new = gen_rtx_MEM (GET_MODE (orig), new); - MEM_COPY_ATTRIBUTES (new, orig); - } - return new; -} - -/* Support functions for code to emit a block move. There are four methods - used to perform the block move: - + call memcpy - + call the looping library function, e.g. __movstrSI64n8 - + call a non-looping library function, e.g. __movstrHI15x11 - + produce an inline sequence of ld/st instructions - - The parameters below describe the library functions produced by - movstr-m88k.sh. */ - -#define MOVSTR_LOOP 64 /* __movstrSI64n68 .. __movstrSI64n8 */ -#define MOVSTR_QI 16 /* __movstrQI16x16 .. __movstrQI16x2 */ -#define MOVSTR_HI 48 /* __movstrHI48x48 .. __movstrHI48x4 */ -#define MOVSTR_SI 96 /* __movstrSI96x96 .. __movstrSI96x8 */ -#define MOVSTR_DI 96 /* __movstrDI96x96 .. __movstrDI96x16 */ -#define MOVSTR_ODD_HI 16 /* __movstrHI15x15 .. __movstrHI15x5 */ -#define MOVSTR_ODD_SI 48 /* __movstrSI47x47 .. __movstrSI47x11, - __movstrSI46x46 .. __movstrSI46x10, - __movstrSI45x45 .. __movstrSI45x9 */ -#define MOVSTR_ODD_DI 48 /* __movstrDI47x47 .. __movstrDI47x23, - __movstrDI46x46 .. __movstrDI46x22, - __movstrDI45x45 .. __movstrDI45x21, - __movstrDI44x44 .. __movstrDI44x20, - __movstrDI43x43 .. __movstrDI43x19, - __movstrDI42x42 .. __movstrDI42x18, - __movstrDI41x41 .. __movstrDI41x17 */ - -/* Limits for using the non-looping movstr functions. For the m88100 - processor, we assume the source and destination are word aligned. - The QImode and HImode limits are the break even points where memcpy - does just as well and beyond which memcpy does better. For the - m88110, we tend to assume double word alignment, but also analyze - the word aligned cases. The analysis is complicated because memcpy - may use the cache control instructions for better performance. */ - -#define MOVSTR_QI_LIMIT_88100 13 -#define MOVSTR_HI_LIMIT_88100 38 -#define MOVSTR_SI_LIMIT_88100 MOVSTR_SI -#define MOVSTR_DI_LIMIT_88100 MOVSTR_SI - -#define MOVSTR_QI_LIMIT_88000 16 -#define MOVSTR_HI_LIMIT_88000 38 -#define MOVSTR_SI_LIMIT_88000 72 -#define MOVSTR_DI_LIMIT_88000 72 - -#define MOVSTR_QI_LIMIT_88110 16 -#define MOVSTR_HI_LIMIT_88110 38 -#define MOVSTR_SI_LIMIT_88110 72 -#define MOVSTR_DI_LIMIT_88110 72 - -static const enum machine_mode mode_from_align[] = - {VOIDmode, QImode, HImode, VOIDmode, SImode, - VOIDmode, VOIDmode, VOIDmode, DImode}; -static const int max_from_align[] = {0, MOVSTR_QI, MOVSTR_HI, 0, MOVSTR_SI, - 0, 0, 0, MOVSTR_DI}; -static const int all_from_align[] = {0, MOVSTR_QI, MOVSTR_ODD_HI, 0, - MOVSTR_ODD_SI, 0, 0, 0, MOVSTR_ODD_DI}; - -static const int best_from_align[3][9] = { - {0, MOVSTR_QI_LIMIT_88100, MOVSTR_HI_LIMIT_88100, 0, MOVSTR_SI_LIMIT_88100, - 0, 0, 0, MOVSTR_DI_LIMIT_88100}, - {0, MOVSTR_QI_LIMIT_88110, MOVSTR_HI_LIMIT_88110, 0, MOVSTR_SI_LIMIT_88110, - 0, 0, 0, MOVSTR_DI_LIMIT_88110}, - {0, MOVSTR_QI_LIMIT_88000, MOVSTR_HI_LIMIT_88000, 0, MOVSTR_SI_LIMIT_88000, - 0, 0, 0, MOVSTR_DI_LIMIT_88000} -}; - -static void block_move_loop PARAMS ((rtx, rtx, rtx, rtx, int, int)); -static void block_move_no_loop PARAMS ((rtx, rtx, rtx, rtx, int, int)); -static void block_move_sequence PARAMS ((rtx, rtx, rtx, rtx, int, int, int)); -static void output_short_branch_defs PARAMS ((FILE *)); -static int output_option PARAMS ((FILE *, const char *, const char *, - const char *, const char *, int, int)); - -/* Emit code to perform a block move. Choose the best method. - - OPERANDS[0] is the destination. - OPERANDS[1] is the source. - OPERANDS[2] is the size. - OPERANDS[3] is the alignment safe to use. */ - -void -expand_block_move (dest_mem, src_mem, operands) - rtx dest_mem; - rtx src_mem; - rtx *operands; -{ - int align = INTVAL (operands[3]); - int constp = (GET_CODE (operands[2]) == CONST_INT); - int bytes = (constp ? INTVAL (operands[2]) : 0); - int target = (int) m88k_cpu; - - if (! (PROCESSOR_M88100 == 0 - && PROCESSOR_M88110 == 1 - && PROCESSOR_M88000 == 2)) - abort (); - - if (constp && bytes <= 0) - return; - - /* Determine machine mode to do move with. */ - if (align > 4 && !TARGET_88110) - align = 4; - else if (align <= 0 || align == 3) - abort (); /* block move invalid alignment. */ - - if (constp && bytes <= 3 * align) - block_move_sequence (operands[0], dest_mem, operands[1], src_mem, - bytes, align, 0); - - else if (constp && bytes <= best_from_align[target][align]) - block_move_no_loop (operands[0], dest_mem, operands[1], src_mem, - bytes, align); - - else if (constp && align == 4 && TARGET_88100) - block_move_loop (operands[0], dest_mem, operands[1], src_mem, - bytes, align); - - else - { -#ifdef TARGET_MEM_FUNCTIONS - emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0, - VOIDmode, 3, - operands[0], Pmode, - operands[1], Pmode, - convert_to_mode (TYPE_MODE (sizetype), operands[2], - TREE_UNSIGNED (sizetype)), - TYPE_MODE (sizetype)); -#else - emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0, - VOIDmode, 3, - operands[1], Pmode, - operands[0], Pmode, - convert_to_mode (TYPE_MODE (integer_type_node), - operands[2], - TREE_UNSIGNED (integer_type_node)), - TYPE_MODE (integer_type_node)); -#endif - } -} - -/* Emit code to perform a block move by calling a looping movstr library - function. SIZE and ALIGN are known constants. DEST and SRC are - registers. */ - -static void -block_move_loop (dest, dest_mem, src, src_mem, size, align) - rtx dest, dest_mem; - rtx src, src_mem; - int size; - int align; -{ - enum machine_mode mode; - int count; - int units; - int remainder; - rtx offset_rtx; - rtx value_rtx; - char entry[30]; - tree entry_name; - - /* Determine machine mode to do move with. */ - if (align != 4) - abort (); - - /* Determine the structure of the loop. */ - count = size / MOVSTR_LOOP; - units = (size - count * MOVSTR_LOOP) / align; - - if (units < 2) - { - count--; - units += MOVSTR_LOOP / align; - } - - if (count <= 0) - { - block_move_no_loop (dest, dest_mem, src, src_mem, size, align); - return; - } - - remainder = size - count * MOVSTR_LOOP - units * align; - - mode = mode_from_align[align]; - sprintf (entry, "__movstr%s%dn%d", - GET_MODE_NAME (mode), MOVSTR_LOOP, units * align); - entry_name = get_identifier (entry); - - offset_rtx = GEN_INT (MOVSTR_LOOP + (1 - units) * align); - - value_rtx = gen_rtx_MEM (MEM_IN_STRUCT_P (src_mem) ? mode : BLKmode, - gen_rtx_PLUS (Pmode, - gen_rtx_REG (Pmode, 3), - offset_rtx)); - MEM_COPY_ATTRIBUTES (value_rtx, src_mem); - - emit_insn (gen_call_movstrsi_loop - (gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name)), - dest, src, offset_rtx, value_rtx, - gen_rtx_REG (mode, ((units & 1) ? 4 : 5)), - GEN_INT (count))); - - if (remainder) - block_move_sequence (gen_rtx_REG (Pmode, 2), dest_mem, - gen_rtx_REG (Pmode, 3), src_mem, - remainder, align, MOVSTR_LOOP + align); -} - -/* Emit code to perform a block move by calling a non-looping library - function. SIZE and ALIGN are known constants. DEST and SRC are - registers. OFFSET is the known starting point for the output pattern. */ - -static void -block_move_no_loop (dest, dest_mem, src, src_mem, size, align) - rtx dest, dest_mem; - rtx src, src_mem; - int size; - int align; -{ - enum machine_mode mode = mode_from_align[align]; - int units = size / align; - int remainder = size - units * align; - int most; - int value_reg; - rtx offset_rtx; - rtx value_rtx; - char entry[30]; - tree entry_name; - - if (remainder && size <= all_from_align[align]) - { - most = all_from_align[align] - (align - remainder); - remainder = 0; - } - else - { - most = max_from_align[align]; - } - - sprintf (entry, "__movstr%s%dx%d", - GET_MODE_NAME (mode), most, size - remainder); - entry_name = get_identifier (entry); - - offset_rtx = GEN_INT (most - (size - remainder)); - - value_rtx = gen_rtx_MEM (MEM_IN_STRUCT_P (src_mem) ? mode : BLKmode, - gen_rtx_PLUS (Pmode, - gen_rtx_REG (Pmode, 3), - offset_rtx)); - - MEM_COPY_ATTRIBUTES (value_rtx, src_mem); - - value_reg = ((((most - (size - remainder)) / align) & 1) == 0 - ? (align == 8 ? 6 : 5) : 4); - - emit_insn (gen_call_block_move - (gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name)), - dest, src, offset_rtx, value_rtx, - gen_rtx_REG (mode, value_reg))); - - if (remainder) - block_move_sequence (gen_rtx_REG (Pmode, 2), dest_mem, - gen_rtx_REG (Pmode, 3), src_mem, - remainder, align, most); -} - -/* Emit code to perform a block move with an offset sequence of ld/st - instructions (..., ld 0, st 1, ld 1, st 0, ...). SIZE and ALIGN are - known constants. DEST and SRC are registers. OFFSET is the known - starting point for the output pattern. */ - -static void -block_move_sequence (dest, dest_mem, src, src_mem, size, align, offset) - rtx dest, dest_mem; - rtx src, src_mem; - int size; - int align; - int offset; -{ - rtx temp[2]; - enum machine_mode mode[2]; - int amount[2]; - int active[2]; - int phase = 0; - int next; - int offset_ld = offset; - int offset_st = offset; - - active[0] = active[1] = FALSE; - - /* Establish parameters for the first load and for the second load if - it is known to be the same mode as the first. */ - amount[0] = amount[1] = align; - mode[0] = mode_from_align[align]; - temp[0] = gen_reg_rtx (mode[0]); - if (size >= 2 * align) - { - mode[1] = mode[0]; - temp[1] = gen_reg_rtx (mode[1]); - } - - do - { - rtx srcp, dstp; - next = phase; - phase = !phase; - - if (size > 0) - { - /* Change modes as the sequence tails off. */ - if (size < amount[next]) - { - amount[next] = (size >= 4 ? 4 : (size >= 2 ? 2 : 1)); - mode[next] = mode_from_align[amount[next]]; - temp[next] = gen_reg_rtx (mode[next]); - } - size -= amount[next]; - srcp = gen_rtx_MEM (MEM_IN_STRUCT_P (src_mem) ? mode[next] : BLKmode, - plus_constant (src, offset_ld)); - - MEM_COPY_ATTRIBUTES (srcp, src_mem); - emit_insn (gen_rtx_SET (VOIDmode, temp[next], srcp)); - offset_ld += amount[next]; - active[next] = TRUE; - } - - if (active[phase]) - { - active[phase] = FALSE; - dstp - = gen_rtx_MEM (MEM_IN_STRUCT_P (dest_mem) ? mode[phase] : BLKmode, - plus_constant (dest, offset_st)); - - MEM_COPY_ATTRIBUTES (dstp, dest_mem); - emit_insn (gen_rtx_SET (VOIDmode, dstp, temp[phase])); - offset_st += amount[phase]; - } - } - while (active[next]); -} - -/* Emit the code to do an AND operation. */ - -const char * -output_and (operands) - rtx operands[]; -{ - unsigned int value; - - if (REG_P (operands[2])) - return "and %0,%1,%2"; - - value = INTVAL (operands[2]); - if (SMALL_INTVAL (value)) - return "mask %0,%1,%2"; - else if ((value & 0xffff0000) == 0xffff0000) - return "and %0,%1,%x2"; - else if ((value & 0xffff) == 0xffff) - return "and.u %0,%1,%X2"; - else if ((value & 0xffff) == 0) - return "mask.u %0,%1,%X2"; - else if (integer_ok_for_set (~value)) - return "clr %0,%1,%S2"; - else - return "and.u %0,%1,%X2\n\tand %0,%0,%x2"; -} - -/* Emit the code to do an inclusive OR operation. */ - -const char * -output_ior (operands) - rtx operands[]; -{ - unsigned int value; - - if (REG_P (operands[2])) - return "or %0,%1,%2"; - - value = INTVAL (operands[2]); - if (SMALL_INTVAL (value)) - return "or %0,%1,%2"; - else if ((value & 0xffff) == 0) - return "or.u %0,%1,%X2"; - else if (integer_ok_for_set (value)) - return "set %0,%1,%s2"; - else - return "or.u %0,%1,%X2\n\tor %0,%0,%x2"; -} - -/* Emit the instructions for doing an XOR. */ - -const char * -output_xor (operands) - rtx operands[]; -{ - unsigned int value; - - if (REG_P (operands[2])) - return "xor %0,%1,%2"; - - value = INTVAL (operands[2]); - if (SMALL_INTVAL (value)) - return "xor %0,%1,%2"; - else if ((value & 0xffff) == 0) - return "xor.u %0,%1,%X2"; - else - return "xor.u %0,%1,%X2\n\txor %0,%0,%x2"; -} - -/* Output a call. Normally this is just bsr or jsr, but this also deals with - accomplishing a branch after the call by incrementing r1. This requires - that various assembler bugs be accommodated. The 4.30 DG/UX assembler - requires that forward references not occur when computing the difference of - two labels. The [version?] Motorola assembler computes a word difference. - No doubt there's more to come! - - It would seem the same idea could be used to tail call, but in this case, - the epilogue will be non-null. */ - -static rtx sb_name = 0; -static rtx sb_high = 0; -static rtx sb_low = 0; - -const char * -output_call (operands, addr) - rtx operands[]; - rtx addr; -{ - operands[0] = addr; - if (final_sequence) - { - rtx jump; - rtx seq_insn; - - /* This can be generalized, but there is currently no need. */ - if (XVECLEN (final_sequence, 0) != 2) - abort (); - - /* The address of interior insns is not computed, so use the sequence. */ - seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); - jump = XVECEXP (final_sequence, 0, 1); - if (GET_CODE (jump) == JUMP_INSN) - { -#ifndef USE_GAS - rtx low, high; -#endif - const char *last; - rtx dest = XEXP (SET_SRC (PATTERN (jump)), 0); - int delta = 4 * (INSN_ADDRESSES (INSN_UID (dest)) - - INSN_ADDRESSES (INSN_UID (seq_insn)) - - 2); -#if (MONITOR_GCC & 0x2) /* How often do long branches happen? */ - if ((unsigned) (delta + 0x8000) >= 0x10000) - warning ("internal gcc monitor: short-branch(%x)", delta); -#endif - - /* Delete the jump. */ - PUT_CODE (jump, NOTE); - NOTE_LINE_NUMBER (jump) = NOTE_INSN_DELETED; - NOTE_SOURCE_FILE (jump) = 0; - - /* We only do this optimization if -O2, modifying the value of - r1 in the delay slot confuses debuggers and profilers on some - systems. - - If we loose, we must use the non-delay form. This is unlikely - to ever happen. If it becomes a problem, claim that a call - has two delay slots and only the second can be filled with - a jump. - - The 88110 can lose when a jsr.n r1 is issued and a page fault - occurs accessing the delay slot. So don't use jsr.n form when - jumping thru r1. - */ -#ifdef AS_BUG_IMMEDIATE_LABEL /* The assembler restricts immediate values. */ - if (optimize < 2 - || ! ADD_INTVAL (delta * 2) -#else - if (optimize < 2 - || ! ADD_INTVAL (delta) -#endif - || (REG_P (addr) && REGNO (addr) == 1)) - { - operands[1] = dest; - return (REG_P (addr) - ? "jsr %0\n\tbr %l1" - : (flag_pic - ? "bsr %0#plt\n\tbr %l1" - : "bsr %0\n\tbr %l1")); - } - - /* Output the short branch form. */ - output_asm_insn ((REG_P (addr) - ? "jsr.n %0" - : (flag_pic ? "bsr.n %0#plt" : "bsr.n %0")), - operands); - -#ifdef USE_GAS - last = (delta < 0 - ? "subu %#r1,%#r1,.-%l0+4" - : "addu %#r1,%#r1,%l0-.-4"); - operands[0] = dest; -#else - operands[0] = gen_label_rtx (); - operands[1] = gen_label_rtx (); - if (delta < 0) - { - low = dest; - high = operands[1]; - last = "subu %#r1,%#r1,%l0\n%l1:"; - } - else - { - low = operands[1]; - high = dest; - last = "addu %#r1,%#r1,%l0\n%l1:"; - } - - /* Record the values to be computed later as "def name,high-low". */ - sb_name = gen_rtx_EXPR_LIST (VOIDmode, operands[0], sb_name); - sb_high = gen_rtx_EXPR_LIST (VOIDmode, high, sb_high); - sb_low = gen_rtx_EXPR_LIST (VOIDmode, low, sb_low); -#endif /* Don't USE_GAS */ - - return last; - } - } - return (REG_P (addr) - ? "jsr%. %0" - : (flag_pic ? "bsr%. %0#plt" : "bsr%. %0")); -} - -static void -output_short_branch_defs (stream) - FILE *stream; -{ - char name[256], high[256], low[256]; - - for (; sb_name && sb_high && sb_low; - sb_name = XEXP (sb_name, 1), - sb_high = XEXP (sb_high, 1), - sb_low = XEXP (sb_low, 1)) - { - ASM_GENERATE_INTERNAL_LABEL - (name, "L", CODE_LABEL_NUMBER (XEXP (sb_name, 0))); - ASM_GENERATE_INTERNAL_LABEL - (high, "L", CODE_LABEL_NUMBER (XEXP (sb_high, 0))); - ASM_GENERATE_INTERNAL_LABEL - (low, "L", CODE_LABEL_NUMBER (XEXP (sb_low, 0))); - /* This will change as the assembler requirements become known. */ - fprintf (stream, "%s%s,%s-%s\n", - SET_ASM_OP, &name[1], &high[1], &low[1]); - } - if (sb_name || sb_high || sb_low) - abort (); -} - -/* Return truth value of the statement that this conditional branch is likely - to fall through. CONDITION, is the condition that JUMP_INSN is testing. */ - -int -mostly_false_jump (jump_insn, condition) - rtx jump_insn, condition; -{ - rtx target_label = JUMP_LABEL (jump_insn); - rtx insnt, insnj; - - /* Much of this isn't computed unless we're optimizing. */ - if (optimize == 0) - return 0; - - /* Determine if one path or the other leads to a return. */ - for (insnt = NEXT_INSN (target_label); - insnt; - insnt = NEXT_INSN (insnt)) - { - if (GET_CODE (insnt) == JUMP_INSN) - break; - else if (GET_CODE (insnt) == INSN - && GET_CODE (PATTERN (insnt)) == SEQUENCE - && GET_CODE (XVECEXP (PATTERN (insnt), 0, 0)) == JUMP_INSN) - { - insnt = XVECEXP (PATTERN (insnt), 0, 0); - break; - } - } - if (insnt - && (GET_CODE (PATTERN (insnt)) == RETURN - || (GET_CODE (PATTERN (insnt)) == SET - && GET_CODE (SET_SRC (PATTERN (insnt))) == REG - && REGNO (SET_SRC (PATTERN (insnt))) == 1))) - insnt = 0; - - for (insnj = NEXT_INSN (jump_insn); - insnj; - insnj = NEXT_INSN (insnj)) - { - if (GET_CODE (insnj) == JUMP_INSN) - break; - else if (GET_CODE (insnj) == INSN - && GET_CODE (PATTERN (insnj)) == SEQUENCE - && GET_CODE (XVECEXP (PATTERN (insnj), 0, 0)) == JUMP_INSN) - { - insnj = XVECEXP (PATTERN (insnj), 0, 0); - break; - } - } - if (insnj - && (GET_CODE (PATTERN (insnj)) == RETURN - || (GET_CODE (PATTERN (insnj)) == SET - && GET_CODE (SET_SRC (PATTERN (insnj))) == REG - && REGNO (SET_SRC (PATTERN (insnj))) == 1))) - insnj = 0; - - /* Predict to not return. */ - if ((insnt == 0) != (insnj == 0)) - return (insnt == 0); - - /* Predict loops to loop. */ - for (insnt = PREV_INSN (target_label); - insnt && GET_CODE (insnt) == NOTE; - insnt = PREV_INSN (insnt)) - if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_END) - return 1; - else if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_BEG) - return 0; - else if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_CONT) - return 0; - - /* Predict backward branches usually take. */ - if (final_sequence) - insnj = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); - else - insnj = jump_insn; - if (INSN_ADDRESSES (INSN_UID (insnj)) - > INSN_ADDRESSES (INSN_UID (target_label))) - return 0; - - /* EQ tests are usually false and NE tests are usually true. Also, - most quantities are positive, so we can make the appropriate guesses - about signed comparisons against zero. Consider unsigned comparisons - to be a range check and assume quantities to be in range. */ - switch (GET_CODE (condition)) - { - case CONST_INT: - /* Unconditional branch. */ - return 0; - case EQ: - return 1; - case NE: - return 0; - case LE: - case LT: - case GEU: - case GTU: /* Must get casesi right at least. */ - if (XEXP (condition, 1) == const0_rtx) - return 1; - break; - case GE: - case GT: - case LEU: - case LTU: - if (XEXP (condition, 1) == const0_rtx) - return 0; - break; - default: - break; - } - - return 0; -} - -/* Return true if the operand is a power of two and is a floating - point type (to optimize division by power of two into multiplication). */ - -int -real_power_of_2_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - REAL_VALUE_TYPE d; - union { - long l[2]; - struct { /* IEEE double precision format */ - unsigned sign : 1; - unsigned exponent : 11; - unsigned mantissa1 : 20; - unsigned mantissa2; - } s; - struct { /* IEEE double format to quick check */ - unsigned sign : 1; /* if it fits in a float */ - unsigned exponent1 : 4; - unsigned exponent2 : 7; - unsigned mantissa1 : 20; - unsigned mantissa2; - } s2; - } u; - - if (GET_MODE (op) != DFmode && GET_MODE (op) != SFmode) - return 0; - - if (GET_CODE (op) != CONST_DOUBLE) - return 0; - - REAL_VALUE_FROM_CONST_DOUBLE (d, op); - REAL_VALUE_TO_TARGET_DOUBLE (d, u.l); - - if (u.s.mantissa1 != 0 || u.s.mantissa2 != 0 /* not a power of two */ - || u.s.exponent == 0 /* constant 0.0 */ - || u.s.exponent == 0x7ff /* NAN */ - || (u.s2.exponent1 != 0x8 && u.s2.exponent1 != 0x7)) - return 0; /* const won't fit in float */ - - return 1; -} - -/* Make OP legitimate for mode MODE. Currently this only deals with DFmode - operands, putting them in registers and making CONST_DOUBLE values - SFmode where possible. */ - -struct rtx_def * -legitimize_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - rtx temp; - REAL_VALUE_TYPE r; - union { - long l[2]; - struct { /* IEEE double precision format */ - unsigned sign : 1; - unsigned exponent : 11; - unsigned mantissa1 : 20; - unsigned mantissa2; - } d; - struct { /* IEEE double format to quick check */ - unsigned sign : 1; /* if it fits in a float */ - unsigned exponent1 : 4; - unsigned exponent2 : 7; - unsigned mantissa1 : 20; - unsigned mantissa2; - } s; - } u; - - if (GET_CODE (op) == REG || mode != DFmode) - return op; - - if (GET_CODE (op) == CONST_DOUBLE) - { - REAL_VALUE_FROM_CONST_DOUBLE (r, op); - REAL_VALUE_TO_TARGET_DOUBLE (r, u.l); - if (u.d.exponent != 0x7ff /* NaN */ - && u.d.mantissa2 == 0 /* Mantissa fits */ - && (u.s.exponent1 == 0x8 || u.s.exponent1 == 0x7) /* Exponent fits */ - && (temp = simplify_unary_operation (FLOAT_TRUNCATE, SFmode, - op, mode)) != 0) - return gen_rtx_FLOAT_EXTEND (mode, force_reg (SFmode, temp)); - } - else if (register_operand (op, mode)) - return op; - - return force_reg (mode, op); -} - -/* Return true if OP is a suitable input for a move insn. */ - -int -move_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - if (register_operand (op, mode)) - return 1; - if (GET_CODE (op) == CONST_INT) - return (classify_integer (mode, INTVAL (op)) < m88k_oru_hi16); - if (GET_MODE (op) != mode) - return 0; - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - if (GET_CODE (op) != MEM) - return 0; - - op = XEXP (op, 0); - if (GET_CODE (op) == LO_SUM) - return (REG_P (XEXP (op, 0)) - && symbolic_address_p (XEXP (op, 1))); - return memory_address_p (mode, op); -} - -/* Return true if OP is suitable for a call insn. */ - -int -call_address_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return (REG_P (op) || symbolic_address_p (op)); -} - -/* Returns true if OP is either a symbol reference or a sum of a symbol - reference and a constant. */ - -int -symbolic_address_p (op) - register rtx op; -{ - switch (GET_CODE (op)) - { - case SYMBOL_REF: - case LABEL_REF: - return 1; - - case CONST: - op = XEXP (op, 0); - return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF - || GET_CODE (XEXP (op, 0)) == LABEL_REF) - && GET_CODE (XEXP (op, 1)) == CONST_INT); - - default: - return 0; - } -} - -/* Return true if OP is a register or const0_rtx. */ - -int -reg_or_0_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (op == const0_rtx || register_operand (op, mode)); -} - -/* Nonzero if OP is a valid second operand for an arithmetic insn. */ - -int -arith_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (register_operand (op, mode) - || (GET_CODE (op) == CONST_INT && SMALL_INT (op))); -} - -/* Return true if OP is a register or 5 bit integer. */ - -int -arith5_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (register_operand (op, mode) - || (GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 32)); -} - -int -arith32_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (register_operand (op, mode) || GET_CODE (op) == CONST_INT); -} - -int -arith64_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (register_operand (op, mode) - || GET_CODE (op) == CONST_INT - || (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)); -} - -int -int5_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return (GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 32); -} - -int -int32_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return (GET_CODE (op) == CONST_INT); -} - -/* Return true if OP is a register or a valid immediate operand for - addu or subu. */ - -int -add_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (register_operand (op, mode) - || (GET_CODE (op) == CONST_INT && ADD_INT (op))); -} - -/* Nonzero if this is a bitmask filling the bottom bits, for optimizing and + - shift left combinations into a single mak instruction. */ - -int -mak_mask_p (value) - int value; -{ - return (value && POWER_OF_2_or_0 (value + 1)); -} - -int -reg_or_bbx_mask_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - int value; - if (register_operand (op, mode)) - return 1; - if (GET_CODE (op) != CONST_INT) - return 0; - - value = INTVAL (op); - if (POWER_OF_2 (value)) - return 1; - - return 0; -} - -/* Return true if OP is valid to use in the context of a floating - point operation. Special case 0.0, since we can use r0. */ - -int -real_or_0_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - if (mode != SFmode && mode != DFmode) - return 0; - - return (register_operand (op, mode) - || (GET_CODE (op) == CONST_DOUBLE - && op == CONST0_RTX (mode))); -} - -/* Return true if OP is valid to use in the context of logic arithmetic - on condition codes. */ - -int -partial_ccmode_register_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return register_operand (op, CCmode) || register_operand (op, CCEVENmode); -} - -/* Return true if OP is a relational operator. */ - -int -relop (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - switch (GET_CODE (op)) - { - case EQ: - case NE: - case LT: - case LE: - case GE: - case GT: - case LTU: - case LEU: - case GEU: - case GTU: - return 1; - default: - return 0; - } -} - -int -even_relop (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - switch (GET_CODE (op)) - { - case EQ: - case LT: - case GT: - case LTU: - case GTU: - return 1; - default: - return 0; - } -} - -int -odd_relop (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - switch (GET_CODE (op)) - { - case NE: - case LE: - case GE: - case LEU: - case GEU: - return 1; - default: - return 0; - } -} - -/* Return true if OP is a relational operator, and is not an unsigned - relational operator. */ - -int -relop_no_unsigned (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - switch (GET_CODE (op)) - { - case EQ: - case NE: - case LT: - case LE: - case GE: - case GT: - /* @@ What is this test doing? Why not use `mode'? */ - if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT - || GET_MODE (op) == DImode - || GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_FLOAT - || GET_MODE (XEXP (op, 0)) == DImode - || GET_MODE_CLASS (GET_MODE (XEXP (op, 1))) == MODE_FLOAT - || GET_MODE (XEXP (op, 1)) == DImode) - return 0; - return 1; - default: - return 0; - } -} - -/* Return true if the code of this rtx pattern is EQ or NE. */ - -int -equality_op (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return (GET_CODE (op) == EQ || GET_CODE (op) == NE); -} - -/* Return true if the code of this rtx pattern is pc or label_ref. */ - -int -pc_or_label_ref (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF); -} - -/* Output to FILE the start of the assembler file. */ - -/* This definition must match lang_independent_options from toplev.c. */ -struct m88k_lang_independent_options -{ - const char *const string; - int *const variable; - const int on_value; - const char *const description; -}; - -static void output_options PARAMS ((FILE *, - const struct m88k_lang_independent_options *, - int, - const struct m88k_lang_independent_options *, - int, int, int, const char *, const char *, - const char *)); - -static int -output_option (file, sep, type, name, indent, pos, max) - FILE *file; - const char *sep; - const char *type; - const char *name; - const char *indent; - int pos; - int max; -{ - if ((long)(strlen (sep) + strlen (type) + strlen (name) + pos) > max) - { - fprintf (file, indent); - return fprintf (file, "%s%s", type, name); - } - return pos + fprintf (file, "%s%s%s", sep, type, name); -} - -static const struct { const char *const name; const int value; } m_options[] = -TARGET_SWITCHES; - -static void -output_options (file, f_options, f_len, W_options, W_len, - pos, max, sep, indent, term) - FILE *file; - const struct m88k_lang_independent_options *f_options; - const struct m88k_lang_independent_options *W_options; - int f_len, W_len; - int pos; - int max; - const char *sep; - const char *indent; - const char *term; -{ - register int j; - - if (optimize) - pos = output_option (file, sep, "-O", "", indent, pos, max); - if (write_symbols != NO_DEBUG) - pos = output_option (file, sep, "-g", "", indent, pos, max); - if (profile_flag) - pos = output_option (file, sep, "-p", "", indent, pos, max); - for (j = 0; j < f_len; j++) - if (*f_options[j].variable == f_options[j].on_value) - pos = output_option (file, sep, "-f", f_options[j].string, - indent, pos, max); - - for (j = 0; j < W_len; j++) - if (*W_options[j].variable == W_options[j].on_value) - pos = output_option (file, sep, "-W", W_options[j].string, - indent, pos, max); - - for (j = 0; j < (long) ARRAY_SIZE (m_options); j++) - if (m_options[j].name[0] != '\0' - && m_options[j].value > 0 - && ((m_options[j].value & target_flags) - == m_options[j].value)) - pos = output_option (file, sep, "-m", m_options[j].name, - indent, pos, max); - - if (m88k_short_data) - pos = output_option (file, sep, "-mshort-data-", m88k_short_data, - indent, pos, max); - - fprintf (file, term); -} - -void -output_file_start (file, f_options, f_len, W_options, W_len) - FILE *file; - const struct m88k_lang_independent_options *f_options; - const struct m88k_lang_independent_options *W_options; - int f_len, W_len; -{ - register int pos; - - ASM_FIRST_LINE (file); - if (TARGET_88110 - && TARGET_SVR4) - fprintf (file, "%s\n", REQUIRES_88110_ASM_OP); - output_file_directive (file, main_input_filename); - /* Switch to the data section so that the coffsem symbol - isn't in the text section. */ - ASM_COFFSEM (file); - - if (TARGET_IDENTIFY_REVISION) - { - char indent[256]; - - time_t now = time ((time_t *)0); - sprintf (indent, "]\"\n%s\"@(#)%s [", IDENT_ASM_OP, main_input_filename); - fprintf (file, indent+3); - pos = fprintf (file, "gcc %s, %.24s,", version_string, ctime (&now)); -#if 1 - /* ??? It would be nice to call print_switch_values here (and thereby - let us delete output_options) but this is kept in until it is known - whether the change in content format matters. */ - output_options (file, f_options, f_len, W_options, W_len, - pos, 150 - strlen (indent), " ", indent, "]\"\n\n"); -#else - fprintf (file, "]\"\n"); - print_switch_values (file, 0, 150 - strlen (indent), - indent + 3, " ", "]\"\n"); -#endif - } -} - -/* Output an ascii string. */ - -void -output_ascii (file, opcode, max, p, size) - FILE *file; - const char *opcode; - int max; - const char *p; - int size; -{ - int i; - int in_escape = 0; - - register int num = 0; - - fprintf (file, "%s\"", opcode); - for (i = 0; i < size; i++) - { - register int c = (unsigned char) p[i]; - - if (num > max) - { - fprintf (file, "\"\n%s\"", opcode); - num = 0; - } - - if (c == '\"' || c == '\\') - { - escape: - putc ('\\', file); - putc (c, file); - num += 2; - in_escape = 0; - } - else if (in_escape && ISDIGIT (c)) - { - /* If a digit follows an octal-escape, the VAX assembler fails - to stop reading the escape after three digits. Continue to - output the values as an octal-escape until a non-digit is - found. */ - fprintf (file, "\\%03o", c); - num += 4; - } - else if ((c >= ' ' && c < 0177) || (c == '\t')) - { - putc (c, file); - num++; - in_escape = 0; - } - else - { - switch (c) - { - /* Some assemblers can't handle \a, \v, or \?. */ - case '\f': c = 'f'; goto escape; - case '\b': c = 'b'; goto escape; - case '\r': c = 'r'; goto escape; - case '\n': c = 'n'; goto escape; - } - - fprintf (file, "\\%03o", c); - num += 4; - in_escape = 1; - } - } - fprintf (file, "\"\n"); -} - -/* Output a label (allows insn-output.c to be compiled without including - m88k.c or needing to include stdio.h). */ - -void -output_label (label_number) - int label_number; -{ - (*targetm.asm_out.internal_label) (asm_out_file, "L", label_number); -} - -/* Generate the assembly code for function entry. - - The prologue is responsible for setting up the stack frame, - initializing the frame pointer register, saving registers that must be - saved, and allocating SIZE additional bytes of storage for the - local variables. SIZE is an integer. FILE is a stdio - stream to which the assembler code should be output. - - The label for the beginning of the function need not be output by this - macro. That has already been done when the macro is run. - - To determine which registers to save, the macro can refer to the array - `regs_ever_live': element R is nonzero if hard register - R is used anywhere within the function. This implies the - function prologue should save register R, but not if it is one - of the call-used registers. - - On machines where functions may or may not have frame-pointers, the - function entry code must vary accordingly; it must set up the frame - pointer if one is wanted, and not otherwise. To determine whether a - frame pointer is in wanted, the macro can refer to the variable - `frame_pointer_needed'. The variable's value will be 1 at run - time in a function that needs a frame pointer. - - On machines where an argument may be passed partly in registers and - partly in memory, this macro must examine the variable - `current_function_pretend_args_size', and allocate that many bytes - of uninitialized space on the stack just underneath the first argument - arriving on the stack. (This may not be at the very end of the stack, - if the calling sequence has pushed anything else since pushing the stack - arguments. But usually, on such machines, nothing else has been pushed - yet, because the function prologue itself does all the pushing.) - - If `ACCUMULATE_OUTGOING_ARGS' is defined, the variable - `current_function_outgoing_args_size' contains the size in bytes - required for the outgoing arguments. This macro must add that - amount of uninitialized space to very bottom of the stack. - - The stack frame we use looks like this: - - caller callee - |==============================================| - | caller's frame | - |==============================================| - | [caller's outgoing memory arguments] | - |==============================================| - | caller's outgoing argument area (32 bytes) | - sp -> |==============================================| <- ap - | [local variable space] | - |----------------------------------------------| - | [return address (r1)] | - |----------------------------------------------| - | [previous frame pointer (r30)] | - |==============================================| <- fp - | [preserved registers (r25..r14)] | - |----------------------------------------------| - | [preserved registers (x29..x22)] | - |==============================================| - | [dynamically allocated space (alloca)] | - |==============================================| - | [callee's outgoing memory arguments] | - |==============================================| - | [callee's outgoing argument area (32 bytes)] | - |==============================================| <- sp - - Notes: - - r1 and r30 must be saved if debugging. - - fp (if present) is located two words down from the local - variable space. - */ - -static void emit_add PARAMS ((rtx, rtx, int)); -static void preserve_registers PARAMS ((int, int)); -static void emit_ldst PARAMS ((int, int, enum machine_mode, int)); -static void output_tdesc PARAMS ((FILE *, int)); -static int uses_arg_area_p PARAMS ((void)); - -static int nregs; -static int nxregs; -static char save_regs[FIRST_PSEUDO_REGISTER]; -static int frame_laid_out; -static int frame_size; -static int variable_args_p; -static int epilogue_marked; -static int prologue_marked; - -#define FIRST_OCS_PRESERVE_REGISTER 14 -#define LAST_OCS_PRESERVE_REGISTER 30 - -#define FIRST_OCS_EXTENDED_PRESERVE_REGISTER (32 + 22) -#define LAST_OCS_EXTENDED_PRESERVE_REGISTER (32 + 31) - -#define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT) -#define ROUND_CALL_BLOCK_SIZE(BYTES) \ - (((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1)) - -/* Establish the position of the FP relative to the SP. This is done - either during output_function_prologue() or by - INITIAL_ELIMINATION_OFFSET. */ - -void -m88k_layout_frame () -{ - int regno, sp_size; - - frame_laid_out++; - - memset ((char *) &save_regs[0], 0, sizeof (save_regs)); - sp_size = nregs = nxregs = 0; - frame_size = get_frame_size (); - - /* Since profiling requires a call, make sure r1 is saved. */ - if (current_function_profile) - save_regs[1] = 1; - - /* If we are producing debug information, store r1 and r30 where the - debugger wants to find them (r30 at r30+0, r1 at r30+4). Space has - already been reserved for r1/r30 in STARTING_FRAME_OFFSET. */ - if (write_symbols != NO_DEBUG && !TARGET_OCS_FRAME_POSITION) - save_regs[1] = 1; - - /* If there is a call, alloca is used, __builtin_alloca is used, or - a dynamic-sized object is defined, add the 8 additional words - for the callee's argument area. The common denominator is that the - FP is required. may_call_alloca only gets calls to alloca; - current_function_calls_alloca gets alloca and __builtin_alloca. */ - if (regs_ever_live[1] || frame_pointer_needed) - { - save_regs[1] = 1; - sp_size += REG_PARM_STACK_SPACE (0); - } - - /* If we are producing PIC, save the addressing base register and r1. */ - if (flag_pic && current_function_uses_pic_offset_table) - { - save_regs[PIC_OFFSET_TABLE_REGNUM] = 1; - nregs++; - } - - /* If a frame is requested, save the previous FP, and the return - address (r1), so that a traceback can be done without using tdesc - information. Otherwise, simply save the FP if it is used as - a preserve register. */ - if (frame_pointer_needed) - save_regs[FRAME_POINTER_REGNUM] = save_regs[1] = 1; - else if (regs_ever_live[FRAME_POINTER_REGNUM]) - save_regs[FRAME_POINTER_REGNUM] = 1; - - /* Figure out which extended register(s) needs to be saved. */ - for (regno = FIRST_EXTENDED_REGISTER + 1; regno < FIRST_PSEUDO_REGISTER; - regno++) - if (regs_ever_live[regno] && ! call_used_regs[regno]) - { - save_regs[regno] = 1; - nxregs++; - } - - /* Figure out which normal register(s) needs to be saved. */ - for (regno = 2; regno < FRAME_POINTER_REGNUM; regno++) - if (regs_ever_live[regno] && ! call_used_regs[regno]) - { - save_regs[regno] = 1; - nregs++; - } - - /* Achieve greatest use of double memory ops. Either we end up saving - r30 or we use that slot to align the registers we do save. */ - if (nregs >= 2 && save_regs[1] && !save_regs[FRAME_POINTER_REGNUM]) - sp_size += 4; - - nregs += save_regs[1] + save_regs[FRAME_POINTER_REGNUM]; - /* if we need to align extended registers, add a word */ - if (nxregs > 0 && (nregs & 1) != 0) - sp_size +=4; - sp_size += 4 * nregs; - sp_size += 8 * nxregs; - sp_size += current_function_outgoing_args_size; - - /* The first two saved registers are placed above the new frame pointer - if any. In the only case this matters, they are r1 and r30. */ - if (frame_pointer_needed || sp_size) - m88k_fp_offset = ROUND_CALL_BLOCK_SIZE (sp_size - STARTING_FRAME_OFFSET); - else - m88k_fp_offset = -STARTING_FRAME_OFFSET; - m88k_stack_size = m88k_fp_offset + STARTING_FRAME_OFFSET; - - /* First, combine m88k_stack_size and size. If m88k_stack_size is - nonzero, align the frame size to 8 mod 16; otherwise align the - frame size to 0 mod 16. (If stacks are 8 byte aligned, this ends - up as a NOP. */ - { - int need - = ((m88k_stack_size ? STACK_UNIT_BOUNDARY - STARTING_FRAME_OFFSET : 0) - - (frame_size % STACK_UNIT_BOUNDARY)); - if (need < 0) - need += STACK_UNIT_BOUNDARY; - m88k_stack_size - = ROUND_CALL_BLOCK_SIZE (m88k_stack_size + frame_size + need - + current_function_pretend_args_size); - } -} - -/* Return true if this function is known to have a null prologue. */ - -int -null_prologue () -{ - if (! reload_completed) - return 0; - if (! frame_laid_out) - m88k_layout_frame (); - return (! frame_pointer_needed - && nregs == 0 - && nxregs == 0 - && m88k_stack_size == 0); -} - -/* Determine if the current function has any references to the arg pointer. - This is done indirectly by examining the DECL_ARGUMENTS' DECL_RTL. - It is OK to return TRUE if there are no references, but FALSE must be - correct. */ - -static int -uses_arg_area_p () -{ - register tree parm; - - if (current_function_decl == 0 - || variable_args_p) - return 1; - - for (parm = DECL_ARGUMENTS (current_function_decl); - parm; - parm = TREE_CHAIN (parm)) - { - if (DECL_RTL (parm) == 0 - || GET_CODE (DECL_RTL (parm)) == MEM) - return 1; - - if (DECL_INCOMING_RTL (parm) == 0 - || GET_CODE (DECL_INCOMING_RTL (parm)) == MEM) - return 1; - } - return 0; -} - -static void -m88k_output_function_prologue (stream, size) - FILE *stream ATTRIBUTE_UNUSED; - HOST_WIDE_INT size ATTRIBUTE_UNUSED; -{ - if (TARGET_OMIT_LEAF_FRAME_POINTER && ! quiet_flag && leaf_function_p ()) - fprintf (stderr, "$"); - - m88k_prologue_done = 1; /* it's ok now to put out ln directives */ -} - -static void -m88k_output_function_end_prologue (stream) - FILE *stream; -{ - if (TARGET_OCS_DEBUG_INFO && !prologue_marked) - { - PUT_OCS_FUNCTION_START (stream); - prologue_marked = 1; - - /* If we've already passed the start of the epilogue, say that - it starts here. This marks the function as having a null body, - but at a point where the return address is in a known location. - - Originally, I thought this couldn't happen, but the pic prologue - for leaf functions ends with the instruction that restores the - return address from the temporary register. If the temporary - register is never used, that instruction can float all the way - to the end of the function. */ - if (epilogue_marked) - PUT_OCS_FUNCTION_END (stream); - } -} - -void -m88k_expand_prologue () -{ - m88k_layout_frame (); - - if (TARGET_OPTIMIZE_ARG_AREA - && m88k_stack_size - && ! uses_arg_area_p ()) - { - /* The incoming argument area is used for stack space if it is not - used (or if -mno-optimize-arg-area is given). */ - if ((m88k_stack_size -= REG_PARM_STACK_SPACE (0)) < 0) - m88k_stack_size = 0; - } - - if (m88k_stack_size) - emit_add (stack_pointer_rtx, stack_pointer_rtx, -m88k_stack_size); - - if (nregs || nxregs) - preserve_registers (m88k_fp_offset + 4, 1); - - if (frame_pointer_needed) - emit_add (frame_pointer_rtx, stack_pointer_rtx, m88k_fp_offset); - - if (flag_pic && save_regs[PIC_OFFSET_TABLE_REGNUM]) - { - rtx return_reg = gen_rtx_REG (SImode, 1); - rtx label = gen_label_rtx (); - rtx temp_reg = NULL_RTX; - - if (! save_regs[1]) - { - temp_reg = gen_rtx_REG (SImode, TEMP_REGNUM); - emit_move_insn (temp_reg, return_reg); - } - emit_insn (gen_locate1 (pic_offset_table_rtx, label)); - emit_insn (gen_locate2 (pic_offset_table_rtx, label)); - emit_insn (gen_addsi3 (pic_offset_table_rtx, - pic_offset_table_rtx, return_reg)); - if (! save_regs[1]) - emit_move_insn (return_reg, temp_reg); - } - if (current_function_profile) - emit_insn (gen_blockage ()); -} - -/* This function generates the assembly code for function exit, - on machines that need it. - - The function epilogue should not depend on the current stack pointer! - It should use the frame pointer only, if there is a frame pointer. - This is mandatory because of alloca; we also take advantage of it to - omit stack adjustments before returning. */ - -static void -m88k_output_function_begin_epilogue (stream) - FILE *stream; -{ - if (TARGET_OCS_DEBUG_INFO && !epilogue_marked && prologue_marked) - { - PUT_OCS_FUNCTION_END (stream); - } - epilogue_marked = 1; -} - -static void -m88k_output_function_epilogue (stream, size) - FILE *stream; - HOST_WIDE_INT size ATTRIBUTE_UNUSED; -{ - rtx insn = get_last_insn (); - - if (TARGET_OCS_DEBUG_INFO && !epilogue_marked) - PUT_OCS_FUNCTION_END (stream); - - /* If the last insn isn't a BARRIER, we must write a return insn. This - should only happen if the function has no prologue and no body. */ - if (GET_CODE (insn) == NOTE) - insn = prev_nonnote_insn (insn); - if (insn == 0 || GET_CODE (insn) != BARRIER) - fprintf (stream, "\tjmp\t %s\n", reg_names[1]); - - /* If the last insn is a barrier, and the insn before that is a call, - then add a nop instruction so that tdesc can walk the stack correctly - even though there is no epilogue. (Otherwise, the label for the - end of the tdesc region ends up at the start of the next function. */ - if (insn && GET_CODE (insn) == BARRIER) - { - insn = prev_nonnote_insn (insn); - if (insn && GET_CODE (insn) == CALL_INSN) - fprintf (stream, "\tor\t %s,%s,%s\n",reg_names[0],reg_names[0],reg_names[0]); - } - - output_short_branch_defs (stream); - - fprintf (stream, "\n"); - - if (TARGET_OCS_DEBUG_INFO) - output_tdesc (stream, m88k_fp_offset + 4); - - m88k_function_number++; - m88k_prologue_done = 0; /* don't put out ln directives */ - variable_args_p = 0; /* has variable args */ - frame_laid_out = 0; - epilogue_marked = 0; - prologue_marked = 0; -} - -void -m88k_expand_epilogue () -{ -#if (MONITOR_GCC & 0x4) /* What are interesting prologue/epilogue values? */ - fprintf (stream, "; size = %d, m88k_fp_offset = %d, m88k_stack_size = %d\n", - size, m88k_fp_offset, m88k_stack_size); -#endif - - if (frame_pointer_needed) - emit_add (stack_pointer_rtx, frame_pointer_rtx, -m88k_fp_offset); - - if (nregs || nxregs) - preserve_registers (m88k_fp_offset + 4, 0); - - if (m88k_stack_size) - emit_add (stack_pointer_rtx, stack_pointer_rtx, m88k_stack_size); -} - -/* Emit insns to set DSTREG to SRCREG + AMOUNT during the prologue or - epilogue. */ - -static void -emit_add (dstreg, srcreg, amount) - rtx dstreg; - rtx srcreg; - int amount; -{ - rtx incr = GEN_INT (abs (amount)); - - if (! ADD_INTVAL (amount)) - { - rtx temp = gen_rtx_REG (SImode, TEMP_REGNUM); - emit_move_insn (temp, incr); - incr = temp; - } - emit_insn ((amount < 0 ? gen_subsi3 : gen_addsi3) (dstreg, srcreg, incr)); -} - -/* Save/restore the preserve registers. base is the highest offset from - r31 at which a register is stored. store_p is true if stores are to - be done; otherwise loads. */ - -static void -preserve_registers (base, store_p) - int base; - int store_p; -{ - int regno, offset; - struct mem_op { - int regno; - int nregs; - int offset; - } mem_op[FIRST_PSEUDO_REGISTER]; - struct mem_op *mo_ptr = mem_op; - - /* The 88open OCS mandates that preserved registers be stored in - increasing order. For compatibility with current practice, - the order is r1, r30, then the preserve registers. */ - - offset = base; - if (save_regs[1]) - { - /* An extra word is given in this case to make best use of double - memory ops. */ - if (nregs > 2 && !save_regs[FRAME_POINTER_REGNUM]) - offset -= 4; - emit_ldst (store_p, 1, SImode, offset); - offset -= 4; - base = offset; - } - - /* Walk the registers to save recording all single memory operations. */ - for (regno = FRAME_POINTER_REGNUM; regno > 1; regno--) - if (save_regs[regno]) - { - if ((offset & 7) != 4 || (regno & 1) != 1 || !save_regs[regno-1]) - { - mo_ptr->nregs = 1; - mo_ptr->regno = regno; - mo_ptr->offset = offset; - mo_ptr++; - offset -= 4; - } - else - { - regno--; - offset -= 2*4; - } - } - - /* Walk the registers to save recording all double memory operations. - This avoids a delay in the epilogue (ld.d/ld). */ - offset = base; - for (regno = FRAME_POINTER_REGNUM; regno > 1; regno--) - if (save_regs[regno]) - { - if ((offset & 7) != 4 || (regno & 1) != 1 || !save_regs[regno-1]) - { - offset -= 4; - } - else - { - mo_ptr->nregs = 2; - mo_ptr->regno = regno-1; - mo_ptr->offset = offset-4; - mo_ptr++; - regno--; - offset -= 2*4; - } - } - - /* Walk the extended registers to record all memory operations. */ - /* Be sure the offset is double word aligned. */ - offset = (offset - 1) & ~7; - for (regno = FIRST_PSEUDO_REGISTER - 1; regno > FIRST_EXTENDED_REGISTER; - regno--) - if (save_regs[regno]) - { - mo_ptr->nregs = 2; - mo_ptr->regno = regno; - mo_ptr->offset = offset; - mo_ptr++; - offset -= 2*4; - } - - mo_ptr->regno = 0; - - /* Output the memory operations. */ - for (mo_ptr = mem_op; mo_ptr->regno; mo_ptr++) - { - if (mo_ptr->nregs) - emit_ldst (store_p, mo_ptr->regno, - (mo_ptr->nregs > 1 ? DImode : SImode), - mo_ptr->offset); - } -} - -static void -emit_ldst (store_p, regno, mode, offset) - int store_p; - int regno; - enum machine_mode mode; - int offset; -{ - rtx reg = gen_rtx_REG (mode, regno); - rtx mem; - - if (SMALL_INTVAL (offset)) - { - mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset)); - } - else - { - /* offset is too large for immediate index must use register */ - - rtx disp = GEN_INT (offset); - rtx temp = gen_rtx_REG (SImode, TEMP_REGNUM); - rtx regi = gen_rtx_PLUS (SImode, stack_pointer_rtx, temp); - - emit_move_insn (temp, disp); - mem = gen_rtx_MEM (mode, regi); - } - - if (store_p) - emit_move_insn (mem, reg); - else - emit_move_insn (reg, mem); -} - -/* Convert the address expression REG to a CFA offset. */ - -int -m88k_debugger_offset (reg, offset) - register rtx reg; - register int offset; -{ - if (GET_CODE (reg) == PLUS) - { - offset = INTVAL (XEXP (reg, 1)); - reg = XEXP (reg, 0); - } - - /* Put the offset in terms of the CFA (arg pointer). */ - if (reg == frame_pointer_rtx) - offset += m88k_fp_offset - m88k_stack_size; - else if (reg == stack_pointer_rtx) - offset -= m88k_stack_size; - else if (reg != arg_pointer_rtx) - { -#if (MONITOR_GCC & 0x10) /* Watch for suspicious symbolic locations. */ - if (! (GET_CODE (reg) == REG - && REGNO (reg) >= FIRST_PSEUDO_REGISTER)) - warning ("internal gcc error: Can't express symbolic location"); -#endif - return 0; - } - - return offset; -} - -/* Output the 88open OCS proscribed text description information. - The information is: - 0 8: zero - 0 22: info-byte-length (16 or 20 bytes) - 0 2: info-alignment (word 2) - 1 32: info-protocol (version 1 or 2(pic)) - 2 32: starting-address (inclusive, not counting prologue) - 3 32: ending-address (exclusive, not counting epilog) - 4 8: info-variant (version 1 or 3(extended registers)) - 4 17: register-save-mask (from register 14 to 30) - 4 1: zero - 4 1: return-address-info-discriminant - 4 5: frame-address-register - 5 32: frame-address-offset - 6 32: return-address-info - 7 32: register-save-offset - 8 16: extended-register-save-mask (x16 - x31) - 8 16: extended-register-save-offset (WORDS from register-save-offset) */ - -static void -output_tdesc (file, offset) - FILE *file; - int offset; -{ - int regno, i, j; - long mask, return_address_info, register_save_offset; - long xmask, xregister_save_offset; - char buf[256]; - - for (mask = 0, i = 0, regno = FIRST_OCS_PRESERVE_REGISTER; - regno <= LAST_OCS_PRESERVE_REGISTER; - regno++) - { - mask <<= 1; - if (save_regs[regno]) - { - mask |= 1; - i++; - } - } - - for (xmask = 0, j = 0, regno = FIRST_OCS_EXTENDED_PRESERVE_REGISTER; - regno <= LAST_OCS_EXTENDED_PRESERVE_REGISTER; - regno++) - { - xmask <<= 1; - if (save_regs[regno]) - { - xmask |= 1; - j++; - } - } - - if (save_regs[1]) - { - if ((nxregs > 0 || nregs > 2) && !save_regs[FRAME_POINTER_REGNUM]) - offset -= 4; - return_address_info = - m88k_stack_size + offset; - register_save_offset = return_address_info - i*4; - } - else - { - return_address_info = 1; - register_save_offset = - m88k_stack_size + offset + 4 - i*4; - } - - xregister_save_offset = - (j * 2 + ((register_save_offset >> 2) & 1)); - - tdesc_section (); - - /* 8:0,22:(20 or 16),2:2 */ - fprintf (file, "%s%d,%d", integer_asm_op (4, TRUE), - (((xmask != 0) ? 20 : 16) << 2) | 2, - flag_pic ? 2 : 1); - - ASM_GENERATE_INTERNAL_LABEL (buf, OCS_START_PREFIX, m88k_function_number); - fprintf (file, ",%s%s", buf+1, flag_pic ? "#rel" : ""); - ASM_GENERATE_INTERNAL_LABEL (buf, OCS_END_PREFIX, m88k_function_number); - fprintf (file, ",%s%s", buf+1, flag_pic ? "#rel" : ""); - - fprintf (file, ",0x%x,0x%x,0x%lx,0x%lx", - /* 8:1,17:0x%.3x,1:0,1:%d,5:%d */ - (int)(((xmask ? 3 : 1) << (17+1+1+5)) - | (mask << (1+1+5)) - | ((!!save_regs[1]) << 5) - | (frame_pointer_needed - ? FRAME_POINTER_REGNUM - : STACK_POINTER_REGNUM)), - (m88k_stack_size - (frame_pointer_needed ? m88k_fp_offset : 0)), - return_address_info, - register_save_offset); - if (xmask) - fprintf (file, ",0x%lx%04lx", xmask, (0xffff & xregister_save_offset)); - fputc ('\n', file); - - text_section (); -} - -/* Output assembler code to FILE to increment profiler label # LABELNO - for profiling a function entry. NAME is the mcount function name - (varies), SAVEP indicates whether the parameter registers need to - be saved and restored. */ - -void -output_function_profiler (file, labelno, name, savep) - FILE *file; - int labelno; - const char *name; - int savep; -{ - char label[256]; - char dbi[256]; - const char *const temp = (savep ? reg_names[2] : reg_names[10]); - - /* Remember to update FUNCTION_PROFILER_LENGTH. */ - - if (savep) - { - fprintf (file, "\tsubu\t %s,%s,64\n", reg_names[31], reg_names[31]); - fprintf (file, "\tst.d\t %s,%s,32\n", reg_names[2], reg_names[31]); - fprintf (file, "\tst.d\t %s,%s,40\n", reg_names[4], reg_names[31]); - fprintf (file, "\tst.d\t %s,%s,48\n", reg_names[6], reg_names[31]); - fprintf (file, "\tst.d\t %s,%s,56\n", reg_names[8], reg_names[31]); - } - - ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno); - if (flag_pic == 2) - { - fprintf (file, "\tor.u\t %s,%s,%shi16(%s#got_rel)\n", - temp, reg_names[0], m88k_pound_sign, &label[1]); - fprintf (file, "\tor\t %s,%s,%slo16(%s#got_rel)\n", - temp, temp, m88k_pound_sign, &label[1]); - sprintf (dbi, "\tld\t %s,%s,%s\n", temp, - reg_names[PIC_OFFSET_TABLE_REGNUM], temp); - } - else if (flag_pic) - { - sprintf (dbi, "\tld\t %s,%s,%s#got_rel\n", temp, - reg_names[PIC_OFFSET_TABLE_REGNUM], &label[1]); - } - else - { - fprintf (file, "\tor.u\t %s,%s,%shi16(%s)\n", - temp, reg_names[0], m88k_pound_sign, &label[1]); - sprintf (dbi, "\tor\t %s,%s,%slo16(%s)\n", - temp, temp, m88k_pound_sign, &label[1]); - } - - if (flag_pic) - fprintf (file, "\tbsr.n\t %s#plt\n", name); - else - fprintf (file, "\tbsr.n\t %s\n", name); - fputs (dbi, file); - - if (savep) - { - fprintf (file, "\tld.d\t %s,%s,32\n", reg_names[2], reg_names[31]); - fprintf (file, "\tld.d\t %s,%s,40\n", reg_names[4], reg_names[31]); - fprintf (file, "\tld.d\t %s,%s,48\n", reg_names[6], reg_names[31]); - fprintf (file, "\tld.d\t %s,%s,56\n", reg_names[8], reg_names[31]); - fprintf (file, "\taddu\t %s,%s,64\n", reg_names[31], reg_names[31]); - } -} - -/* Determine whether a function argument is passed in a register, and - which register. - - The arguments are CUM, which summarizes all the previous - arguments; MODE, the machine mode of the argument; TYPE, - the data type of the argument as a tree node or 0 if that is not known - (which happens for C support library functions); and NAMED, - which is 1 for an ordinary argument and 0 for nameless arguments that - correspond to `...' in the called function's prototype. - - The value of the expression should either be a `reg' RTX for the - hard register in which to pass the argument, or zero to pass the - argument on the stack. - - On the m88000 the first eight words of args are normally in registers - and the rest are pushed. Double precision floating point must be - double word aligned (and if in a register, starting on an even - register). Structures and unions which are not 4 byte, and word - aligned are passed in memory rather than registers, even if they - would fit completely in the registers under OCS rules. - - Note that FUNCTION_ARG and FUNCTION_INCOMING_ARG were different. - For structures that are passed in memory, but could have been - passed in registers, we first load the structure into the - register, and then when the last argument is passed, we store - the registers into the stack locations. This fixes some bugs - where GCC did not expect to have register arguments, followed - by stack arguments, followed by register arguments. */ - -struct rtx_def * -m88k_function_arg (args_so_far, mode, type, named) - CUMULATIVE_ARGS args_so_far; - enum machine_mode mode; - tree type; - int named ATTRIBUTE_UNUSED; -{ - int bytes, words; - - if (type != 0 /* undo putting struct in register */ - && (TREE_CODE (type) == RECORD_TYPE || TREE_CODE (type) == UNION_TYPE)) - mode = BLKmode; - - if (mode == BLKmode && TARGET_WARN_PASS_STRUCT) - warning ("argument #%d is a structure", args_so_far + 1); - - if ((args_so_far & 1) != 0 - && (mode == DImode || mode == DFmode - || (type != 0 && TYPE_ALIGN (type) > 32))) - args_so_far++; - -#ifdef ESKIT - if (no_reg_params) - return (rtx) 0; /* don't put args in registers */ -#endif - - if (type == 0 && mode == BLKmode) - abort (); /* m88k_function_arg argument `type' is NULL for BLKmode. */ - - bytes = (mode != BLKmode) ? GET_MODE_SIZE (mode) : int_size_in_bytes (type); - words = (bytes + 3) / 4; - - if (args_so_far + words > 8) - return (rtx) 0; /* args have exhausted registers */ - - else if (mode == BLKmode - && (TYPE_ALIGN (type) != BITS_PER_WORD - || bytes != UNITS_PER_WORD)) - return (rtx) 0; - - return gen_rtx_REG (((mode == BLKmode) ? TYPE_MODE (type) : mode), - 2 + args_so_far); -} - -/* Do what is necessary for `va_start'. We look at the current function - to determine if stdargs or varargs is used and spill as necessary. - We return a pointer to the spill area. */ - -struct rtx_def * -m88k_builtin_saveregs () -{ - rtx addr; - tree fntype = TREE_TYPE (current_function_decl); - int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 - && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) - != void_type_node))) - ? -UNITS_PER_WORD : 0) + UNITS_PER_WORD - 1; - int fixed; - - variable_args_p = 1; - - fixed = 0; - if (GET_CODE (current_function_arg_offset_rtx) == CONST_INT) - fixed = ((INTVAL (current_function_arg_offset_rtx) + argadj) - / UNITS_PER_WORD); - - /* Allocate the register space, and store it as the __va_reg member. */ - addr = assign_stack_local (BLKmode, 8 * UNITS_PER_WORD, -1); - set_mem_alias_set (addr, get_varargs_alias_set ()); - RTX_UNCHANGING_P (addr) = 1; - RTX_UNCHANGING_P (XEXP (addr, 0)) = 1; - - /* Now store the incoming registers. */ - if (fixed < 8) - move_block_from_reg (2 + fixed, - adjust_address (addr, Pmode, fixed * UNITS_PER_WORD), - 8 - fixed); - - /* Return the address of the save area, but don't put it in a - register. This fails when not optimizing and produces worse code - when optimizing. */ - return XEXP (addr, 0); -} - -/* Define the `__builtin_va_list' type for the ABI. */ - -tree -m88k_build_va_list () -{ - tree field_reg, field_stk, field_arg, int_ptr_type_node, record; - - int_ptr_type_node = build_pointer_type (integer_type_node); - - record = make_node (RECORD_TYPE); - - field_arg = build_decl (FIELD_DECL, get_identifier ("__va_arg"), - integer_type_node); - field_stk = build_decl (FIELD_DECL, get_identifier ("__va_stk"), - int_ptr_type_node); - field_reg = build_decl (FIELD_DECL, get_identifier ("__va_reg"), - int_ptr_type_node); - - DECL_FIELD_CONTEXT (field_arg) = record; - DECL_FIELD_CONTEXT (field_stk) = record; - DECL_FIELD_CONTEXT (field_reg) = record; - - TYPE_FIELDS (record) = field_arg; - TREE_CHAIN (field_arg) = field_stk; - TREE_CHAIN (field_stk) = field_reg; - - layout_type (record); - return record; -} - -/* Implement `va_start' for varargs and stdarg. */ - -void -m88k_va_start (valist, nextarg) - tree valist; - rtx nextarg ATTRIBUTE_UNUSED; -{ - tree field_reg, field_stk, field_arg; - tree reg, stk, arg, t; - - field_arg = TYPE_FIELDS (va_list_type_node); - field_stk = TREE_CHAIN (field_arg); - field_reg = TREE_CHAIN (field_stk); - - arg = build (COMPONENT_REF, TREE_TYPE (field_arg), valist, field_arg); - stk = build (COMPONENT_REF, TREE_TYPE (field_stk), valist, field_stk); - reg = build (COMPONENT_REF, TREE_TYPE (field_reg), valist, field_reg); - - /* Fill in the ARG member. */ - { - tree fntype = TREE_TYPE (current_function_decl); - int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 - && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) - != void_type_node))) - ? -UNITS_PER_WORD : 0) + UNITS_PER_WORD - 1; - tree argsize; - - if (CONSTANT_P (current_function_arg_offset_rtx)) - { - int fixed = (INTVAL (current_function_arg_offset_rtx) - + argadj) / UNITS_PER_WORD; - - argsize = build_int_2 (fixed, 0); - } - else - { - argsize = make_tree (integer_type_node, - current_function_arg_offset_rtx); - argsize = fold (build (PLUS_EXPR, integer_type_node, argsize, - build_int_2 (argadj, 0))); - argsize = fold (build (RSHIFT_EXPR, integer_type_node, argsize, - build_int_2 (2, 0))); - } - - t = build (MODIFY_EXPR, TREE_TYPE (arg), arg, argsize); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); - } - - /* Store the arg pointer in the __va_stk member. */ - t = make_tree (TREE_TYPE (stk), virtual_incoming_args_rtx); - t = build (MODIFY_EXPR, TREE_TYPE (stk), stk, t); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); - - /* Tuck the return value from __builtin_saveregs into __va_reg. */ - t = make_tree (TREE_TYPE (reg), expand_builtin_saveregs ()); - t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, t); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); -} - -/* Implement `va_arg'. */ - -rtx -m88k_va_arg (valist, type) - tree valist, type; -{ - tree field_reg, field_stk, field_arg; - tree reg, stk, arg, arg_align, base, t; - int size, wsize, align, reg_p; - rtx addr_rtx; - - field_arg = TYPE_FIELDS (va_list_type_node); - field_stk = TREE_CHAIN (field_arg); - field_reg = TREE_CHAIN (field_stk); - - arg = build (COMPONENT_REF, TREE_TYPE (field_arg), valist, field_arg); - stk = build (COMPONENT_REF, TREE_TYPE (field_stk), valist, field_stk); - reg = build (COMPONENT_REF, TREE_TYPE (field_reg), valist, field_reg); - - size = int_size_in_bytes (type); - wsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; - align = 1 << ((TYPE_ALIGN (type) / BITS_PER_UNIT) >> 3); - reg_p = (AGGREGATE_TYPE_P (type) - ? size == UNITS_PER_WORD && TYPE_ALIGN (type) == BITS_PER_WORD - : size <= 2*UNITS_PER_WORD); - - /* Align __va_arg to the (doubleword?) boundary above. */ - t = build (PLUS_EXPR, TREE_TYPE (arg), arg, build_int_2 (align - 1, 0)); - arg_align = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1)); - arg_align = save_expr (arg_align); - - /* Decide if we should read from stack or regs. */ - t = build (LT_EXPR, integer_type_node, arg_align, build_int_2 (8, 0)); - base = build (COND_EXPR, TREE_TYPE (reg), t, reg, stk); - - /* Find the final address. */ - t = build (PLUS_EXPR, TREE_TYPE (base), base, arg_align); - addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL); - addr_rtx = copy_to_reg (addr_rtx); - - /* Increment __va_arg. */ - t = build (PLUS_EXPR, TREE_TYPE (arg), arg_align, build_int_2 (wsize, 0)); - t = build (MODIFY_EXPR, TREE_TYPE (arg), arg, t); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); - - return addr_rtx; -} - -/* If cmpsi has not been generated, emit code to do the test. Return the - expression describing the test of operator OP. */ - -rtx -emit_test (op, mode) - enum rtx_code op; - enum machine_mode mode; -{ - if (m88k_compare_reg == 0) - emit_insn (gen_test (m88k_compare_op0, m88k_compare_op1)); - return (gen_rtx (op, mode, m88k_compare_reg, const0_rtx)); -} - -/* Determine how to best perform cmpsi/bxx, where cmpsi has a constant - operand. All tests with zero (albeit swapped) and all equality tests - with a constant are done with bcnd. The remaining cases are swapped - as needed. */ - -void -emit_bcnd (op, label) - enum rtx_code op; - rtx label; -{ - if (m88k_compare_op1 == const0_rtx) - emit_jump_insn (gen_bcnd - (gen_rtx (op, VOIDmode,m88k_compare_op0, const0_rtx), - label)); - else if (m88k_compare_op0 == const0_rtx) - emit_jump_insn (gen_bcnd - (gen_rtx (swap_condition (op), - VOIDmode, m88k_compare_op1, const0_rtx), - label)); - else if (op != EQ && op != NE) - emit_jump_insn (gen_bxx (emit_test (op, VOIDmode), label)); - else - { - rtx zero = gen_reg_rtx (SImode); - rtx reg, constant; - int value; - - if (GET_CODE (m88k_compare_op1) == CONST_INT) - { - reg = force_reg (SImode, m88k_compare_op0); - constant = m88k_compare_op1; - } - else - { - reg = force_reg (SImode, m88k_compare_op1); - constant = m88k_compare_op0; - } - value = INTVAL (constant); - - /* Perform an arithmetic computation to make the compared-to value - zero, but avoid loosing if the bcnd is later changed into sxx. */ - if (SMALL_INTVAL (value)) - emit_jump_insn (gen_bxx (emit_test (op, VOIDmode), label)); - else - { - if (SMALL_INTVAL (-value)) - emit_insn (gen_addsi3 (zero, reg, - GEN_INT (-value))); - else - emit_insn (gen_xorsi3 (zero, reg, constant)); - - emit_jump_insn (gen_bcnd (gen_rtx (op, VOIDmode, - zero, const0_rtx), - label)); - } - } -} - -/* Print an operand. Recognize special options, documented below. */ - -void -print_operand (file, x, code) - FILE *file; - rtx x; - int code; -{ - enum rtx_code xc = (x ? GET_CODE (x) : UNKNOWN); - register int value = (xc == CONST_INT ? INTVAL (x) : 0); - static int sequencep; - static int reversep; - - if (sequencep) - { - if (code < 'B' || code > 'E') - output_operand_lossage ("%%R not followed by %%B/C/D/E"); - if (reversep) - xc = reverse_condition (xc); - sequencep = 0; - } - - switch (code) - { - case '*': /* addressing base register for PIC */ - fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file); return; - - case '#': /* SVR4 pound-sign syntax character (empty if SVR3) */ - fputs (m88k_pound_sign, file); return; - - case 'V': /* Output a serializing instruction as needed if the operand - (assumed to be a MEM) is a volatile load. */ - case 'v': /* ditto for a volatile store. */ - if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE) - { - /* The m88110 implements two FIFO queues, one for loads and - one for stores. These queues mean that loads complete in - their issue order as do stores. An interaction between the - history buffer and the store reservation station ensures - that a store will not bypass load. Finally, a load will not - bypass store, but only when they reference the same address. - - To avoid this reordering (a load bypassing a store) for - volatile references, a serializing instruction is output. - We choose the fldcr instruction as it does not serialize on - the m88100 so that -m88000 code will not be degraded. - - The mechanism below is completed by having CC_STATUS_INIT set - the code to the unknown value. */ - - /* - hassey 6/30/93 - A problem with 88110 4.1 & 4.2 makes the use of fldcr for - this purpose undesirable. Instead we will use tb1, this will - cause serialization on the 88100 but such is life. - */ - - static rtx last_addr = 0; - if (code == 'V' /* Only need to serialize before a load. */ - && m88k_volatile_code != 'V' /* Loads complete in FIFO order. */ - && !(m88k_volatile_code == 'v' - && GET_CODE (XEXP (x, 0)) == LO_SUM - && rtx_equal_p (XEXP (XEXP (x, 0), 1), last_addr))) - fprintf (file, -#if 0 -#ifdef AS_BUG_FLDCR - "fldcr\t %s,%scr63\n\t", -#else - "fldcr\t %s,%sfcr63\n\t", -#endif - reg_names[0], m88k_pound_sign); -#else /* 0 */ - "tb1\t 1,%s,0xff\n\t", reg_names[0]); -#endif /* 0 */ - m88k_volatile_code = code; - last_addr = (GET_CODE (XEXP (x, 0)) == LO_SUM - ? XEXP (XEXP (x, 0), 1) : 0); - } - return; - - case 'X': /* print the upper 16 bits... */ - value >>= 16; - case 'x': /* print the lower 16 bits of the integer constant in hex */ - if (xc != CONST_INT) - output_operand_lossage ("invalid %%x/X value"); - fprintf (file, "0x%x", value & 0xffff); return; - - case 'H': /* print the low 16 bits of the negated integer constant */ - if (xc != CONST_INT) - output_operand_lossage ("invalid %%H value"); - value = -value; - case 'h': /* print the register or low 16 bits of the integer constant */ - if (xc == REG) - goto reg; - if (xc != CONST_INT) - output_operand_lossage ("invalid %%h value"); - fprintf (file, "%d", value & 0xffff); - return; - - case 'Q': /* print the low 8 bits of the negated integer constant */ - if (xc != CONST_INT) - output_operand_lossage ("invalid %%Q value"); - value = -value; - case 'q': /* print the register or low 8 bits of the integer constant */ - if (xc == REG) - goto reg; - if (xc != CONST_INT) - output_operand_lossage ("invalid %%q value"); - fprintf (file, "%d", value & 0xff); - return; - - case 'w': /* print the integer constant (X == 32 ? 0 : 32 - X) */ - if (xc != CONST_INT) - output_operand_lossage ("invalid %%o value"); - fprintf (file, "%d", value == 32 ? 0 : 32 - value); - return; - - case 'p': /* print the logarithm of the integer constant */ - if (xc != CONST_INT - || (value = exact_log2 (value)) < 0) - output_operand_lossage ("invalid %%p value"); - fprintf (file, "%d", value); - return; - - case 'S': /* complement the value and then... */ - value = ~value; - case 's': /* print the width and offset values forming the integer - constant with a SET instruction. See integer_ok_for_set. */ - { - register unsigned mask, uval = value; - register int top, bottom; - - if (xc != CONST_INT) - output_operand_lossage ("invalid %%s/S value"); - /* All the "one" bits must be contiguous. If so, MASK will be - a power of two or zero. */ - mask = (uval | (uval - 1)) + 1; - if (!(uval && POWER_OF_2_or_0 (mask))) - output_operand_lossage ("invalid %%s/S value"); - top = mask ? exact_log2 (mask) : 32; - bottom = exact_log2 (uval & ~(uval - 1)); - fprintf (file,"%d<%d>", top - bottom, bottom); - return; - } - - case 'P': /* print nothing if pc_rtx; output label_ref */ - if (xc == LABEL_REF) - output_addr_const (file, x); - else if (xc != PC) - output_operand_lossage ("invalid %%P operand"); - return; - - case 'L': /* print 0 or 1 if operand is label_ref and then... */ - fputc (xc == LABEL_REF ? '1' : '0', file); - case '.': /* print .n if delay slot is used */ - fputs ((final_sequence - && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))) - ? ".n\t" : "\t", file); - return; - - case '!': /* Reverse the following condition. */ - sequencep++; - reversep = 1; - return; - case 'R': /* reverse the condition of the next print_operand - if operand is a label_ref. */ - sequencep++; - reversep = (xc == LABEL_REF); - return; - - case 'B': /* bcnd branch values */ - fputs (m88k_pound_sign, file); - switch (xc) - { - case EQ: fputs ("eq0", file); return; - case NE: fputs ("ne0", file); return; - case GT: fputs ("gt0", file); return; - case LE: fputs ("le0", file); return; - case LT: fputs ("lt0", file); return; - case GE: fputs ("ge0", file); return; - default: output_operand_lossage ("invalid %%B value"); - } - - case 'C': /* bb0/bb1 branch values for comparisons */ - fputs (m88k_pound_sign, file); - switch (xc) - { - case EQ: fputs ("eq", file); return; - case NE: fputs ("ne", file); return; - case GT: fputs ("gt", file); return; - case LE: fputs ("le", file); return; - case LT: fputs ("lt", file); return; - case GE: fputs ("ge", file); return; - case GTU: fputs ("hi", file); return; - case LEU: fputs ("ls", file); return; - case LTU: fputs ("lo", file); return; - case GEU: fputs ("hs", file); return; - default: output_operand_lossage ("invalid %%C value"); - } - - case 'D': /* bcnd branch values for float comparisons */ - switch (xc) - { - case EQ: fputs ("0xa", file); return; - case NE: fputs ("0x5", file); return; - case GT: fputs (m88k_pound_sign, file); - fputs ("gt0", file); return; - case LE: fputs ("0xe", file); return; - case LT: fputs ("0x4", file); return; - case GE: fputs ("0xb", file); return; - default: output_operand_lossage ("invalid %%D value"); - } - - case 'E': /* bcnd branch values for special integers */ - switch (xc) - { - case EQ: fputs ("0x8", file); return; - case NE: fputs ("0x7", file); return; - default: output_operand_lossage ("invalid %%E value"); - } - - case 'd': /* second register of a two register pair */ - if (xc != REG) - output_operand_lossage ("`%%d' operand isn't a register"); - fputs (reg_names[REGNO (x) + 1], file); - return; - - case 'r': /* an immediate 0 should be represented as `r0' */ - if (x == const0_rtx) - { - fputs (reg_names[0], file); - return; - } - else if (xc != REG) - output_operand_lossage ("invalid %%r value"); - case 0: - name: - if (xc == REG) - { - reg: - if (REGNO (x) == ARG_POINTER_REGNUM) - output_operand_lossage ("operand is r0"); - else - fputs (reg_names[REGNO (x)], file); - } - else if (xc == PLUS) - output_address (x); - else if (xc == MEM) - output_address (XEXP (x, 0)); - else if (flag_pic && xc == UNSPEC) - { - output_addr_const (file, XVECEXP (x, 0, 0)); - fputs ("#got_rel", file); - } - else if (xc == CONST_DOUBLE) - output_operand_lossage ("operand is const_double"); - else - output_addr_const (file, x); - return; - - case 'g': /* append #got_rel as needed */ - if (flag_pic && (xc == SYMBOL_REF || xc == LABEL_REF)) - { - output_addr_const (file, x); - fputs ("#got_rel", file); - return; - } - goto name; - - case 'a': /* (standard), assume operand is an address */ - case 'c': /* (standard), assume operand is an immediate value */ - case 'l': /* (standard), assume operand is a label_ref */ - case 'n': /* (standard), like %c, except negate first */ - default: - output_operand_lossage ("invalid code"); - } -} - -void -print_operand_address (file, addr) - FILE *file; - rtx addr; -{ - register rtx reg0, reg1, temp; - - switch (GET_CODE (addr)) - { - case REG: - if (REGNO (addr) == ARG_POINTER_REGNUM) - abort (); - else - fprintf (file, "%s,%s", reg_names[0], reg_names [REGNO (addr)]); - break; - - case LO_SUM: - fprintf (file, "%s,%slo16(", - reg_names[REGNO (XEXP (addr, 0))], m88k_pound_sign); - output_addr_const (file, XEXP (addr, 1)); - fputc (')', file); - break; - - case PLUS: - reg0 = XEXP (addr, 0); - reg1 = XEXP (addr, 1); - if (GET_CODE (reg0) == MULT || GET_CODE (reg0) == CONST_INT) - { - rtx tmp = reg0; - reg0 = reg1; - reg1 = tmp; - } - - if ((REG_P (reg0) && REGNO (reg0) == ARG_POINTER_REGNUM) - || (REG_P (reg1) && REGNO (reg1) == ARG_POINTER_REGNUM)) - abort (); - - else if (REG_P (reg0)) - { - if (REG_P (reg1)) - fprintf (file, "%s,%s", - reg_names [REGNO (reg0)], reg_names [REGNO (reg1)]); - - else if (GET_CODE (reg1) == CONST_INT) - fprintf (file, "%s,%d", - reg_names [REGNO (reg0)], INTVAL (reg1)); - - else if (GET_CODE (reg1) == MULT) - { - rtx mreg = XEXP (reg1, 0); - if (REGNO (mreg) == ARG_POINTER_REGNUM) - abort (); - - fprintf (file, "%s[%s]", reg_names[REGNO (reg0)], - reg_names[REGNO (mreg)]); - } - - else if (GET_CODE (reg1) == ZERO_EXTRACT) - { - fprintf (file, "%s,%slo16(", - reg_names[REGNO (reg0)], m88k_pound_sign); - output_addr_const (file, XEXP (reg1, 0)); - fputc (')', file); - } - - else if (flag_pic) - { - fprintf (file, "%s,", reg_names[REGNO (reg0)]); - output_addr_const (file, reg1); - fputs ("#got_rel", file); - } - else abort (); - } - - else - abort (); - break; - - case MULT: - if (REGNO (XEXP (addr, 0)) == ARG_POINTER_REGNUM) - abort (); - - fprintf (file, "%s[%s]", - reg_names[0], reg_names[REGNO (XEXP (addr, 0))]); - break; - - case CONST_INT: - fprintf (file, "%s,%d", reg_names[0], INTVAL (addr)); - break; - - default: - fprintf (file, "%s,", reg_names[0]); - if (SHORT_ADDRESS_P (addr, temp)) - { - fprintf (file, "%siw16(", m88k_pound_sign); - output_addr_const (file, addr); - fputc (')', file); - } - else - output_addr_const (file, addr); - } -} - -/* Return true if X is an address which needs a temporary register when - reloaded while generating PIC code. */ - -int -pic_address_needs_scratch (x) - rtx x; -{ - /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ - if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS - && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF - && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT - && ! ADD_INT (XEXP (XEXP (x, 0), 1))) - return 1; - - return 0; -} - -/* Returns 1 if OP is either a symbol reference or a sum of a symbol - reference and a constant. */ - -int -symbolic_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - switch (GET_CODE (op)) - { - case SYMBOL_REF: - case LABEL_REF: - return 1; - - case CONST: - op = XEXP (op, 0); - return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF - || GET_CODE (XEXP (op, 0)) == LABEL_REF) - && GET_CODE (XEXP (op, 1)) == CONST_INT); - - /* ??? This clause seems to be irrelevant. */ - case CONST_DOUBLE: - return GET_MODE (op) == mode; - - default: - return 0; - } -} - -#if defined (CTOR_LIST_BEGIN) && !defined (OBJECT_FORMAT_ELF) -static void -m88k_svr3_asm_out_constructor (symbol, priority) - rtx symbol; - int priority ATTRIBUTE_UNUSED; -{ - const char *name = XSTR (symbol, 0); - - init_section (); - fprintf (asm_out_file, "\tor.u\t r13,r0,hi16("); - assemble_name (asm_out_file, name); - fprintf (asm_out_file, ")\n\tor\t r13,r13,lo16("); - assemble_name (asm_out_file, name); - fprintf (asm_out_file, ")\n\tsubu\t r31,r31,%d\n\tst\t r13,r31,%d\n", - STACK_BOUNDARY / BITS_PER_UNIT, REG_PARM_STACK_SPACE (0)); -} - -static void -m88k_svr3_asm_out_destructor (symbol, priority) - rtx symbol; - int priority ATTRIBUTE_UNUSED; -{ - int i; - - fini_section (); - assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1); - for (i = 1; i < 4; i++) - assemble_integer (constm1_rtx, UNITS_PER_WORD, BITS_PER_WORD, 1); -} -#endif /* INIT_SECTION_ASM_OP && ! OBJECT_FORMAT_ELF */ - -static void -m88k_select_section (decl, reloc, align) - tree decl; - int reloc; - unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED; -{ - if (TREE_CODE (decl) == STRING_CST) - { - if (! flag_writable_strings) - readonly_data_section (); - else if (TREE_STRING_LENGTH (decl) <= m88k_gp_threshold) - sdata_section (); - else - data_section (); - } - else if (TREE_CODE (decl) == VAR_DECL) - { - if (SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0))) - sdata_section (); - else if ((flag_pic && reloc) - || !TREE_READONLY (decl) || TREE_SIDE_EFFECTS (decl) - || !DECL_INITIAL (decl) - || (DECL_INITIAL (decl) != error_mark_node - && !TREE_CONSTANT (DECL_INITIAL (decl)))) - data_section (); - else - readonly_data_section (); - } - else - readonly_data_section (); -} - -/* Adjust the cost of INSN based on the relationship between INSN that - is dependent on DEP_INSN through the dependence LINK. The default - is to make no adjustment to COST. - - On the m88k, ignore the cost of anti- and output-dependencies. On - the m88100, a store can issue two cycles before the value (not the - address) has finished computing. */ - -static int -m88k_adjust_cost (insn, link, dep, cost) - rtx insn; - rtx link; - rtx dep; - int cost; -{ - if (REG_NOTE_KIND (link) != 0) - return 0; /* Anti or output dependence. */ - - if (! TARGET_88100 - && recog_memoized (insn) >= 0 - && get_attr_type (insn) == TYPE_STORE - && SET_SRC (PATTERN (insn)) == SET_DEST (PATTERN (dep))) - return cost - 4; /* 88110 store reservation station. */ - - return cost; -} - -/* For the m88k, determine if the item should go in the global pool. */ - -static void -m88k_encode_section_info (decl, rtl, first) - tree decl; - rtx rtl; - int first ATTRIBUTE_UNUSED; -{ - if (m88k_gp_threshold > 0) - { - if (TREE_CODE (decl) == VAR_DECL) - { - if (!TREE_READONLY (decl) || TREE_SIDE_EFFECTS (decl)) - { - int size = int_size_in_bytes (TREE_TYPE (decl)); - - if (size > 0 && size <= m88k_gp_threshold) - SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; - } - } - else if (TREE_CODE (decl) == STRING_CST - && flag_writable_strings - && TREE_STRING_LENGTH (decl) <= m88k_gp_threshold) - SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; - } -} - -#ifdef AS_BUG_DOT_LABELS /* The assembler requires a declaration of local. */ -static void -m88k_internal_label (stream, prefix, labelno) - FILE *stream; - const char *prefix; - unsigned long labelno; -{ - fprintf (stream, TARGET_SVR4 ? ".%s%lu:\n%s.%s%lu\n" : "@%s%ld:\n", - prefix, labelno, INTERNAL_ASM_OP, prefix, labelno); -} -#endif - -static bool -m88k_rtx_costs (x, code, outer_code, total) - rtx x; - int code, outer_code; - int *total; -{ - switch (code) - { - /* We assume that any 16 bit integer can easily be recreated, so we - indicate 0 cost, in an attempt to get GCC not to optimize things - like comparison against a constant. */ - case CONST_INT: - if (SMALL_INT (x)) - *total = 0; - else if (SMALL_INTVAL (- INTVAL (x))) - *total = 2; - else if (classify_integer (SImode, INTVAL (x)) != m88k_oru_or) - *total = 4; - else - *total = 7; - return true; - - case HIGH: - *total = 2; - return true; - - case CONST: - case LABEL_REF: - case SYMBOL_REF: - if (flag_pic) - *total = (flag_pic == 2) ? 11 : 8; - else - *total = 5; - return true; - - /* The cost of CONST_DOUBLE is zero (if it can be placed in an insn, it - is as good as a register; since it can't be placed in any insn, it - won't do anything in cse, but it will cause expand_binop to pass the - constant to the define_expands). */ - case CONST_DOUBLE: - *total = 0; - return true; - - case MEM: - *total = COSTS_N_INSNS (2); - return true; - - case MULT: - *total = COSTS_N_INSNS (3); - return true; - - case DIV: - case UDIV: - case MOD: - case UMOD: - *total = COSTS_N_INSNS (38); - return true; - - default: - return false; - } -} - -/* Provide the costs of an addressing mode that contains ADDR. - If ADDR is not a valid address, its cost is irrelevant. - REG+REG is made slightly more expensive because it might keep - a register live for longer than we might like. */ -static int -m88k_address_cost (x) - rtx x; -{ - switch (GET_CODE (x)) - { - case REG: - case LO_SUM: - case MULT: - return 1; - case HIGH: - return 2; - case PLUS: - return (REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) ? 2 : 1; - default: - return 4; - } -} diff --git a/gcc/config/m88k/m88k.h b/gcc/config/m88k/m88k.h deleted file mode 100644 index 442c62aa9e6..00000000000 --- a/gcc/config/m88k/m88k.h +++ /dev/null @@ -1,2221 +0,0 @@ -/* Definitions of target machine for GNU compiler for - Motorola m88100 in an 88open OCS/BCS environment. - Copyright (C) 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, - 2001, 2002 Free Software Foundation, Inc. - Contributed by Michael Tiemann (tiemann@cygnus.com). - Currently maintained by (gcc@dg-rtp.dg.com) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* The m88100 port of GNU CC adheres to the various standards from 88open. - These documents are available by writing: - - 88open Consortium Ltd. - 100 Homeland Court, Suite 800 - San Jose, CA 95112 - (408) 436-6600 - - In brief, the current standards are: - - Binary Compatibility Standard, Release 1.1A, May 1991 - This provides for portability of application-level software at the - executable level for AT&T System V Release 3.2. - - Object Compatibility Standard, Release 1.1A, May 1991 - This provides for portability of application-level software at the - object file and library level for C, Fortran, and Cobol, and again, - largely for SVR3. - - Under development are standards for AT&T System V Release 4, based on the - [generic] System V Application Binary Interface from AT&T. These include: - - System V Application Binary Interface, Motorola 88000 Processor Supplement - Another document from AT&T for SVR4 specific to the m88100. - Available from Prentice Hall. - - System V Application Binary Interface, Motorola 88000 Processor Supplement, - Release 1.1, Draft H, May 6, 1991 - A proposed update to the AT&T document from 88open. - - System V ABI Implementation Guide for the M88000 Processor, - Release 1.0, January 1991 - A companion ABI document from 88open. */ - -/* Other *.h files in config/m88k include this one and override certain items. - Currently these are sysv3.h, sysv4.h, dgux.h, dolph.h, tekXD88.h, and luna.h. - Additionally, sysv4.h and dgux.h include svr4.h first. All other - m88k targets except luna.h are based on svr3.h. */ - -/* Choose SVR3 as the default. */ -#if !defined(DBX_DEBUGGING_INFO) && !defined(DWARF_DEBUGGING_INFO) -#include "svr3.h" -#endif - -/* External types used. */ - -/* What instructions are needed to manufacture an integer constant. */ -enum m88k_instruction { - m88k_zero, - m88k_or, - m88k_subu, - m88k_or_lo16, - m88k_or_lo8, - m88k_set, - m88k_oru_hi16, - m88k_oru_or -}; - -/* Which processor to schedule for. The elements of the enumeration - must match exactly the cpu attribute in the m88k.md machine description. */ - -enum processor_type { - PROCESSOR_M88100, - PROCESSOR_M88110, - PROCESSOR_M88000 -}; - -/* Recast the cpu class to be the cpu attribute. */ -#define m88k_cpu_attr ((enum attr_cpu)m88k_cpu) - -/* External variables/functions defined in m88k.c. */ - -extern const char *m88k_pound_sign; -extern const char *m88k_short_data; -extern const char *m88k_version; -extern char m88k_volatile_code; - -extern unsigned m88k_gp_threshold; -extern int m88k_prologue_done; -extern int m88k_function_number; -extern int m88k_fp_offset; -extern int m88k_stack_size; -extern int m88k_case_index; - -extern struct rtx_def *m88k_compare_reg; -extern struct rtx_def *m88k_compare_op0; -extern struct rtx_def *m88k_compare_op1; - -extern enum processor_type m88k_cpu; - -/* external variables defined elsewhere in the compiler */ - -extern int target_flags; /* -m compiler switches */ -extern int frame_pointer_needed; /* current function has a FP */ -extern int flag_delayed_branch; /* -fdelayed-branch */ -extern int flag_pic; /* -fpic */ - -/* Specify the default monitors. The meaning of these values can - be obtained by doing "grep MONITOR_GCC *m88k*". Generally, the - values downward from 0x8000 are tests that will soon go away. - values upward from 0x1 are generally useful tests that will remain. */ - -#ifndef MONITOR_GCC -#define MONITOR_GCC 0 -#endif - -/*** Controlling the Compilation Driver, `gcc' ***/ -/* Show we can debug even without a frame pointer. */ -#define CAN_DEBUG_WITHOUT_FP - -/* If -m88100 is in effect, add -D__m88100__; similarly for -m88110. - Here, the CPU_DEFAULT is assumed to be -m88100. */ -#undef CPP_SPEC -#define CPP_SPEC "%{!m88000:%{!m88100:%{m88110:-D__m88110__}}} \ - %{!m88000:%{!m88110:-D__m88100__}}" - -/* LIB_SPEC, LINK_SPEC, and STARTFILE_SPEC defined in svr3.h. - ASM_SPEC, ASM_FINAL_SPEC, LIB_SPEC, LINK_SPEC, and STARTFILE_SPEC redefined - in svr4.h. - CPP_SPEC, ASM_SPEC, ASM_FINAL_SPEC, LIB_SPEC, LINK_SPEC, and - STARTFILE_SPEC redefined in dgux.h. */ - -/*** Run-time Target Specification ***/ - -/* Names to predefine in the preprocessor for this target machine. - Redefined in sysv3.h, sysv4.h, dgux.h, and luna.h. */ -#define CPP_PREDEFINES "-Dm88000 -Dm88k -Dunix -D__CLASSIFY_TYPE__=2" - -#define TARGET_VERSION fprintf (stderr, " (%s)", VERSION_INFO1) - -#ifndef VERSION_INFO1 -#define VERSION_INFO1 "m88k" -#endif - -/* Run-time compilation parameters selecting different hardware subsets. */ - -/* Macro to define tables used to set the flags. - This is a list in braces of pairs in braces, - each pair being { "NAME", VALUE } - where VALUE is the bits to set or minus the bits to clear. - An empty string NAME is used to identify the default VALUE. */ - -#define MASK_88100 0x00000001 /* Target m88100 */ -#define MASK_88110 0x00000002 /* Target m88110 */ -#define MASK_88000 (MASK_88100 | MASK_88110) - -#define MASK_OCS_DEBUG_INFO 0x00000004 /* Emit .tdesc info */ -#define MASK_OCS_FRAME_POSITION 0x00000008 /* Debug frame = CFA, not r30 */ -#define MASK_SVR4 0x00000010 /* Target is AT&T System V.4 */ -#define MASK_SVR3 0x00000020 /* Target is AT&T System V.3 */ -#define MASK_NO_UNDERSCORES 0x00000040 /* Don't emit a leading `_' */ -#define MASK_BIG_PIC 0x00000080 /* PIC with large got-rel's -fPIC */ -#define MASK_TRAP_LARGE_SHIFT 0x00000100 /* Trap if shift not <= 31 */ -#define MASK_HANDLE_LARGE_SHIFT 0x00000200 /* Handle shift count >= 32 */ -#define MASK_CHECK_ZERO_DIV 0x00000400 /* Check for int div. by 0 */ -#define MASK_USE_DIV 0x00000800 /* No signed div. checks */ -#define MASK_IDENTIFY_REVISION 0x00001000 /* Emit ident, with GCC rev */ -#define MASK_WARN_PASS_STRUCT 0x00002000 /* Warn about passed structs */ -#define MASK_OPTIMIZE_ARG_AREA 0x00004000 /* Save stack space */ -#define MASK_NO_SERIALIZE_VOLATILE 0x00008000 /* Serialize volatile refs */ -#define MASK_EITHER_LARGE_SHIFT (MASK_TRAP_LARGE_SHIFT | \ - MASK_HANDLE_LARGE_SHIFT) -#define MASK_OMIT_LEAF_FRAME_POINTER 0x00020000 /* omit leaf frame pointers */ - - -#define TARGET_88100 ((target_flags & MASK_88000) == MASK_88100) -#define TARGET_88110 ((target_flags & MASK_88000) == MASK_88110) -#define TARGET_88000 ((target_flags & MASK_88000) == MASK_88000) - -#define TARGET_OCS_DEBUG_INFO (target_flags & MASK_OCS_DEBUG_INFO) -#define TARGET_OCS_FRAME_POSITION (target_flags & MASK_OCS_FRAME_POSITION) -#define TARGET_SVR4 (target_flags & MASK_SVR4) -#define TARGET_SVR3 (target_flags & MASK_SVR3) -#define TARGET_NO_UNDERSCORES (target_flags & MASK_NO_UNDERSCORES) -#define TARGET_BIG_PIC (target_flags & MASK_BIG_PIC) -#define TARGET_TRAP_LARGE_SHIFT (target_flags & MASK_TRAP_LARGE_SHIFT) -#define TARGET_HANDLE_LARGE_SHIFT (target_flags & MASK_HANDLE_LARGE_SHIFT) -#define TARGET_CHECK_ZERO_DIV (target_flags & MASK_CHECK_ZERO_DIV) -#define TARGET_USE_DIV (target_flags & MASK_USE_DIV) -#define TARGET_IDENTIFY_REVISION (target_flags & MASK_IDENTIFY_REVISION) -#define TARGET_WARN_PASS_STRUCT (target_flags & MASK_WARN_PASS_STRUCT) -#define TARGET_OPTIMIZE_ARG_AREA (target_flags & MASK_OPTIMIZE_ARG_AREA) -#define TARGET_SERIALIZE_VOLATILE (!(target_flags & MASK_NO_SERIALIZE_VOLATILE)) - -#define TARGET_EITHER_LARGE_SHIFT (target_flags & MASK_EITHER_LARGE_SHIFT) -#define TARGET_OMIT_LEAF_FRAME_POINTER (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) - -/* Redefined in sysv3.h, sysv4.h, and dgux.h. */ -#define TARGET_DEFAULT (MASK_CHECK_ZERO_DIV) -#define CPU_DEFAULT MASK_88100 - -#define TARGET_SWITCHES \ - { \ - { "88110", MASK_88110 }, \ - { "88100", MASK_88100 }, \ - { "88000", MASK_88000 }, \ - { "ocs-debug-info", MASK_OCS_DEBUG_INFO }, \ - { "no-ocs-debug-info", -MASK_OCS_DEBUG_INFO }, \ - { "ocs-frame-position", MASK_OCS_FRAME_POSITION }, \ - { "no-ocs-frame-position", -MASK_OCS_FRAME_POSITION }, \ - { "svr4", MASK_SVR4 }, \ - { "svr3", -MASK_SVR4 }, \ - { "no-underscores", MASK_NO_UNDERSCORES }, \ - { "big-pic", MASK_BIG_PIC }, \ - { "trap-large-shift", MASK_TRAP_LARGE_SHIFT }, \ - { "handle-large-shift", MASK_HANDLE_LARGE_SHIFT }, \ - { "check-zero-division", MASK_CHECK_ZERO_DIV }, \ - { "no-check-zero-division", -MASK_CHECK_ZERO_DIV }, \ - { "use-div-instruction", MASK_USE_DIV }, \ - { "identify-revision", MASK_IDENTIFY_REVISION }, \ - { "warn-passed-structs", MASK_WARN_PASS_STRUCT }, \ - { "optimize-arg-area", MASK_OPTIMIZE_ARG_AREA }, \ - { "no-optimize-arg-area", -MASK_OPTIMIZE_ARG_AREA }, \ - { "no-serialize-volatile", MASK_NO_SERIALIZE_VOLATILE }, \ - { "serialize-volatile", -MASK_NO_SERIALIZE_VOLATILE }, \ - { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER }, \ - { "no-omit-leaf-frame-pointer", -MASK_OMIT_LEAF_FRAME_POINTER }, \ - SUBTARGET_SWITCHES \ - /* Default switches */ \ - { "", TARGET_DEFAULT }, \ - } - -/* Redefined in dgux.h. */ -#define SUBTARGET_SWITCHES - -/* Macro to define table for command options with values. */ - -#define TARGET_OPTIONS { { "short-data-", &m88k_short_data, 0}, \ - { "version-", &m88k_version, 0} } - -/* Do any checking or such that is needed after processing the -m switches. */ - -#define OVERRIDE_OPTIONS \ - do { \ - register int i; \ - \ - if ((target_flags & MASK_88000) == 0) \ - target_flags |= CPU_DEFAULT; \ - \ - if (TARGET_88110) \ - { \ - target_flags |= MASK_USE_DIV; \ - target_flags &= ~MASK_CHECK_ZERO_DIV; \ - } \ - \ - m88k_cpu = (TARGET_88000 ? PROCESSOR_M88000 \ - : (TARGET_88100 ? PROCESSOR_M88100 : PROCESSOR_M88110)); \ - \ - if (TARGET_BIG_PIC) \ - flag_pic = 2; \ - \ - if ((target_flags & MASK_EITHER_LARGE_SHIFT) == MASK_EITHER_LARGE_SHIFT) \ - error ("-mtrap-large-shift and -mhandle-large-shift are incompatible");\ - \ - if (TARGET_SVR4) \ - { \ - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ - reg_names[i]--; \ - m88k_pound_sign = "#"; \ - } \ - else \ - { \ - target_flags |= MASK_SVR3; \ - target_flags &= ~MASK_SVR4; \ - } \ - \ - if (m88k_short_data) \ - { \ - const char *p = m88k_short_data; \ - while (*p) \ - if (ISDIGIT (*p)) \ - p++; \ - else \ - { \ - error ("invalid option `-mshort-data-%s'", m88k_short_data); \ - break; \ - } \ - m88k_gp_threshold = atoi (m88k_short_data); \ - if (m88k_gp_threshold > 0x7fffffff) \ - error ("-mshort-data-%s is too large ", m88k_short_data); \ - if (flag_pic) \ - error ("-mshort-data-%s and PIC are incompatible", m88k_short_data); \ - } \ - if (TARGET_OMIT_LEAF_FRAME_POINTER) /* keep nonleaf frame pointers */ \ - flag_omit_frame_pointer = 1; \ - } while (0) - -/*** Storage Layout ***/ - -/* Sizes in bits of the various types. */ -#define SHORT_TYPE_SIZE 16 -#define INT_TYPE_SIZE 32 -#define LONG_TYPE_SIZE 32 -#define LONG_LONG_TYPE_SIZE 64 -#define FLOAT_TYPE_SIZE 32 -#define DOUBLE_TYPE_SIZE 64 -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* Define this if most significant bit is lowest numbered - in instructions that operate on numbered bit-fields. - Somewhat arbitrary. It matches the bit field patterns. */ -#define BITS_BIG_ENDIAN 1 - -/* Define this if most significant byte of a word is the lowest numbered. - That is true on the m88000. */ -#define BYTES_BIG_ENDIAN 1 - -/* Define this if most significant word of a multiword number is the lowest - numbered. - For the m88000 we can decide arbitrarily since there are no machine - instructions for them. */ -#define WORDS_BIG_ENDIAN 1 - -/* Width of a word, in units (bytes). */ -#define UNITS_PER_WORD 4 - -/* Allocation boundary (in *bits*) for storing arguments in argument list. */ -#define PARM_BOUNDARY 32 - -/* Largest alignment for stack parameters (if greater than PARM_BOUNDARY). */ -#define MAX_PARM_BOUNDARY 64 - -/* Boundary (in *bits*) on which stack pointer should be aligned. */ -#define STACK_BOUNDARY 128 - -/* Allocation boundary (in *bits*) for the code of a function. On the - m88100, it is desirable to align to a cache line. However, SVR3 targets - only provided 8 byte alignment. The m88110 cache is small, so align - to an 8 byte boundary. Pack code tightly when compiling crtstuff.c. */ -#define FUNCTION_BOUNDARY (flag_inhibit_size_directive ? 32 : \ - (TARGET_88100 && TARGET_SVR4 ? 128 : 64)) - -/* No data type wants to be aligned rounder than this. */ -#define BIGGEST_ALIGNMENT 64 - -/* The best alignment to use in cases where we have a choice. */ -#define FASTEST_ALIGNMENT (TARGET_88100 ? 32 : 64) - -/* Make strings 4/8 byte aligned so strcpy from constants will be faster. */ -#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ - ((TREE_CODE (EXP) == STRING_CST \ - && (ALIGN) < FASTEST_ALIGNMENT) \ - ? FASTEST_ALIGNMENT : (ALIGN)) - -/* Make arrays of chars 4/8 byte aligned for the same reasons. */ -#define DATA_ALIGNMENT(TYPE, ALIGN) \ - (TREE_CODE (TYPE) == ARRAY_TYPE \ - && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ - && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) - -/* Alignment of field after `int : 0' in a structure. - Ignored with PCC_BITFIELD_TYPE_MATTERS. */ -/* #define EMPTY_FIELD_BOUNDARY 8 */ - -/* Every structure's size must be a multiple of this. */ -#define STRUCTURE_SIZE_BOUNDARY 8 - -/* Set this nonzero if move instructions will actually fail to work - when given unaligned data. */ -#define STRICT_ALIGNMENT 1 - -/* A bit-field declared as `int' forces `int' alignment for the struct. */ -#define PCC_BITFIELD_TYPE_MATTERS 1 - -/* Maximum size (in bits) to use for the largest integral type that - replaces a BLKmode type. */ -/* #define MAX_FIXED_MODE_SIZE 0 */ - -/*** Register Usage ***/ - -/* Number of actual hardware registers. - The hardware registers are assigned numbers for the compiler - from 0 to just below FIRST_PSEUDO_REGISTER. - All registers that the compiler knows about must be given numbers, - even those that are not normally considered general registers. - - The m88100 has a General Register File (GRF) of 32 32-bit registers. - The m88110 adds an Extended Register File (XRF) of 32 80-bit registers. */ -#define FIRST_PSEUDO_REGISTER 64 -#define FIRST_EXTENDED_REGISTER 32 - -/* General notes on extended registers, their use and misuse. - - Possible good uses: - - spill area instead of memory. - -waste if only used once - - floating point calculations - -probably a waste unless we have run out of general purpose registers - - freeing up general purpose registers - -e.g. may be able to have more loop invariants if floating - point is moved into extended registers. - - - I've noticed wasteful moves into and out of extended registers; e.g. a load - into x21, then inside a loop a move into r24, then r24 used as input to - an fadd. Why not just load into r24 to begin with? Maybe the new cse.c - will address this. This wastes a move, but the load,store and move could - have been saved had extended registers been used throughout. - E.g. in the code following code, if z and xz are placed in extended - registers, there is no need to save preserve registers. - - long c=1,d=1,e=1,f=1,g=1,h=1,i=1,j=1,k; - - double z=0,xz=4.5; - - foo(a,b) - long a,b; - { - while (a < b) - { - k = b + c + d + e + f + g + h + a + i + j++; - z += xz; - a++; - } - printf("k= %d; z=%f;\n", k, z); - } - - I've found that it is possible to change the constraints (putting * before - the 'r' constraints int the fadd.ddd instruction) and get the entire - addition and store to go into extended registers. However, this also - forces simple addition and return of floating point arguments to a - function into extended registers. Not the correct solution. - - Found the following note in local-alloc.c which may explain why I can't - get both registers to be in extended registers since two are allocated in - local-alloc and one in global-alloc. Doesn't explain (I don't believe) - why an extended register is used instead of just using the preserve - register. - - from local-alloc.c: - We have provision to exempt registers, even when they are contained - within the block, that can be tied to others that are not contained in it. - This is so that global_alloc could process them both and tie them then. - But this is currently disabled since tying in global_alloc is not - yet implemented. - - The explanation of why the preserved register is not used is as follows, - I believe. The registers are being allocated in order. Tying is not - done so efficiently, so when it comes time to do the first allocation, - there are no registers left to use without spilling except extended - registers. Then when the next pseudo register needs a hard reg, there - are still no registers to be had for free, but this one must be a GRF - reg instead of an extended reg, so a preserve register is spilled. Thus - the move from extended to GRF is necessitated. I do not believe this can - be 'fixed' through the files in config/m88k. - - gcc seems to sometimes make worse use of register allocation -- not counting - moves -- whenever extended registers are present. For example in the - whetstone, the simple for loop (slightly modified) - for(i = 1; i <= n1; i++) - { - x1 = (x1 + x2 + x3 - x4) * t; - x2 = (x1 + x2 - x3 + x4) * t; - x3 = (x1 - x2 + x3 + x4) * t; - x4 = (x1 + x2 + x3 + x4) * t; - } - in general loads the high bits of the addresses of x2-x4 and i into registers - outside the loop. Whenever extended registers are used, it loads all of - these inside the loop. My conjecture is that since the 88110 has so many - registers, and gcc makes no distinction at this point -- just that they are - not fixed, that in loop.c it believes it can expect a number of registers - to be available. Then it allocates 'too many' in local-alloc which causes - problems later. 'Too many' are allocated because a large portion of the - registers are extended registers and cannot be used for certain purposes - ( e.g. hold the address of a variable). When this loop is compiled on its - own, the problem does not occur. I don't know the solution yet, though it - is probably in the base sources. Possibly a different way to calculate - "threshold". */ - -/* 1 for registers that have pervasive standard uses and are not available - for the register allocator. Registers r14-r25 and x22-x29 are expected - to be preserved across function calls. - - On the 88000, the standard uses of the General Register File (GRF) are: - Reg 0 = Pseudo argument pointer (hardware fixed to 0). - Reg 1 = Subroutine return pointer (hardware). - Reg 2-9 = Parameter registers (OCS). - Reg 10 = OCS reserved temporary. - Reg 11 = Static link if needed [OCS reserved temporary]. - Reg 12 = Address of structure return (OCS). - Reg 13 = OCS reserved temporary. - Reg 14-25 = Preserved register set. - Reg 26-29 = Reserved by OCS and ABI. - Reg 30 = Frame pointer (Common use). - Reg 31 = Stack pointer. - - The following follows the current 88open UCS specification for the - Extended Register File (XRF): - Reg 32 = x0 Always equal to zero - Reg 33-53 = x1-x21 Temporary registers (Caller Save) - Reg 54-61 = x22-x29 Preserver registers (Callee Save) - Reg 62-63 = x30-x31 Reserved for future ABI use. - - Note: The current 88110 extended register mapping is subject to change. - The bias towards caller-save registers is based on the - presumption that memory traffic can potentially be reduced by - allowing the "caller" to save only that part of the register - which is actually being used. (i.e. don't do a st.x if a st.d - is sufficient). Also, in scientific code (a.k.a. Fortran), the - large number of variables defined in common blocks may require - that almost all registers be saved across calls anyway. */ - -#define FIXED_REGISTERS \ - {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1} - -/* 1 for registers not available across function calls. - These must include the FIXED_REGISTERS and also any - registers that can be used without being saved. - The latter must include the registers where values are returned - and the register where structure-value addresses are passed. - Aside from that, you can include as many other registers as you like. */ - -#define CALL_USED_REGISTERS \ - {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ - 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1} - -/* Macro to conditionally modify fixed_regs/call_used_regs. */ -#define CONDITIONAL_REGISTER_USAGE \ - { \ - if (! TARGET_88110) \ - { \ - register int i; \ - for (i = FIRST_EXTENDED_REGISTER; i < FIRST_PSEUDO_REGISTER; i++) \ - { \ - fixed_regs[i] = 1; \ - call_used_regs[i] = 1; \ - } \ - } \ - if (flag_pic) \ - { \ - /* Current hack to deal with -fpic -O2 problems. */ \ - fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ - call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ - global_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ - } \ - } - -/* True if register is an extended register. */ -#define XRF_REGNO_P(N) ((N) < FIRST_PSEUDO_REGISTER && (N) >= FIRST_EXTENDED_REGISTER) - -/* Return number of consecutive hard regs needed starting at reg REGNO - to hold something of mode MODE. - This is ordinarily the length in words of a value of mode MODE - but can be less for certain modes in special long registers. - - On the m88000, GRF registers hold 32-bits and XRF registers hold 80-bits. - An XRF register can hold any mode, but two GRF registers are required - for larger modes. */ -#define HARD_REGNO_NREGS(REGNO, MODE) \ - (XRF_REGNO_P (REGNO) \ - ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) - -/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. - - For double integers, we never put the value into an odd register so that - the operators don't run into the situation where the high part of one of - the inputs is the low part of the result register. (It's ok if the output - registers are the same as the input registers.) The XRF registers can - hold all modes, but only DF and SF modes can be manipulated in these - registers. The compiler should be allowed to use these as a fast spill - area. */ -#define HARD_REGNO_MODE_OK(REGNO, MODE) \ - (XRF_REGNO_P(REGNO) \ - ? (TARGET_88110 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ - : (((MODE) != DImode && (MODE) != DFmode && (MODE) != DCmode) \ - || ((REGNO) & 1) == 0)) - -/* Value is 1 if it is a good idea to tie two pseudo registers - when one has mode MODE1 and one has mode MODE2. - If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, - for any hard reg, then this must be 0 for correct output. */ -#define MODES_TIEABLE_P(MODE1, MODE2) \ - (((MODE1) == DFmode || (MODE1) == DCmode || (MODE1) == DImode \ - || (TARGET_88110 && GET_MODE_CLASS (MODE1) == MODE_FLOAT)) \ - == ((MODE2) == DFmode || (MODE2) == DCmode || (MODE2) == DImode \ - || (TARGET_88110 && GET_MODE_CLASS (MODE2) == MODE_FLOAT))) - -/* Specify the registers used for certain standard purposes. - The values of these macros are register numbers. */ - -/* the m88000 pc isn't overloaded on a register that the compiler knows about. */ -/* #define PC_REGNUM */ - -/* Register to use for pushing function arguments. */ -#define STACK_POINTER_REGNUM 31 - -/* Base register for access to local variables of the function. */ -#define FRAME_POINTER_REGNUM 30 - -/* Base register for access to arguments of the function. */ -#define ARG_POINTER_REGNUM 0 - -/* Register used in cases where a temporary is known to be safe to use. */ -#define TEMP_REGNUM 10 - -/* Register in which static-chain is passed to a function. */ -#define STATIC_CHAIN_REGNUM 11 - -/* Register in which address to store a structure value - is passed to a function. */ -#define STRUCT_VALUE_REGNUM 12 - -/* Register to hold the addressing base for position independent - code access to data items. */ -#define PIC_OFFSET_TABLE_REGNUM 25 - -/* Order in which registers are preferred (most to least). Use temp - registers, then param registers top down. Preserve registers are - top down to maximize use of double memory ops for register save. - The 88open reserved registers (r26-r29 and x30-x31) may commonly be used - in most environments with the -fcall-used- or -fcall-saved- options. */ -#define REG_ALLOC_ORDER \ - { \ - 13, 12, 11, 10, 29, 28, 27, 26, \ - 62, 63, 9, 8, 7, 6, 5, 4, \ - 3, 2, 1, 53, 52, 51, 50, 49, \ - 48, 47, 46, 45, 44, 43, 42, 41, \ - 40, 39, 38, 37, 36, 35, 34, 33, \ - 25, 24, 23, 22, 21, 20, 19, 18, \ - 17, 16, 15, 14, 61, 60, 59, 58, \ - 57, 56, 55, 54, 30, 31, 0, 32} - -/* Order for leaf functions. */ -#define REG_LEAF_ALLOC_ORDER \ - { \ - 9, 8, 7, 6, 13, 12, 11, 10, \ - 29, 28, 27, 26, 62, 63, 5, 4, \ - 3, 2, 0, 53, 52, 51, 50, 49, \ - 48, 47, 46, 45, 44, 43, 42, 41, \ - 40, 39, 38, 37, 36, 35, 34, 33, \ - 25, 24, 23, 22, 21, 20, 19, 18, \ - 17, 16, 15, 14, 61, 60, 59, 58, \ - 57, 56, 55, 54, 30, 31, 1, 32} - -/* Switch between the leaf and non-leaf orderings. The purpose is to avoid - write-over scoreboard delays between caller and callee. */ -#define ORDER_REGS_FOR_LOCAL_ALLOC \ -{ \ - static const int leaf[] = REG_LEAF_ALLOC_ORDER; \ - static const int nonleaf[] = REG_ALLOC_ORDER; \ - \ - memcpy (reg_alloc_order, regs_ever_live[1] ? nonleaf : leaf, \ - FIRST_PSEUDO_REGISTER * sizeof (int)); \ -} - -/*** Register Classes ***/ - -/* Define the classes of registers for register constraints in the - machine description. Also define ranges of constants. - - One of the classes must always be named ALL_REGS and include all hard regs. - If there is more than one class, another class must be named NO_REGS - and contain no registers. - - The name GENERAL_REGS must be the name of a class (or an alias for - another name such as ALL_REGS). This is the class of registers - that is allowed by "g" or "r" in a register constraint. - Also, registers outside this class are allocated only when - instructions express preferences for them. - - The classes must be numbered in nondecreasing order; that is, - a larger-numbered class must never be contained completely - in a smaller-numbered class. - - For any two classes, it is very desirable that there be another - class that represents their union. */ - -/* The m88000 hardware has two kinds of registers. In addition, we denote - the arg pointer as a separate class. */ - -enum reg_class { NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS, AGRF_REGS, - XGRF_REGS, ALL_REGS, LIM_REG_CLASSES }; - -#define N_REG_CLASSES (int) LIM_REG_CLASSES - -/* Give names of register classes as strings for dump file. */ -#define REG_CLASS_NAMES {"NO_REGS", "AP_REG", "XRF_REGS", "GENERAL_REGS", \ - "AGRF_REGS", "XGRF_REGS", "ALL_REGS" } - -/* Define which registers fit in which classes. - This is an initializer for a vector of HARD_REG_SET - of length N_REG_CLASSES. */ -#define REG_CLASS_CONTENTS {{0x00000000, 0x00000000}, \ - {0x00000001, 0x00000000}, \ - {0x00000000, 0xffffffff}, \ - {0xfffffffe, 0x00000000}, \ - {0xffffffff, 0x00000000}, \ - {0xfffffffe, 0xffffffff}, \ - {0xffffffff, 0xffffffff}} - -/* The same information, inverted: - Return the class number of the smallest class containing - reg number REGNO. This could be a conditional expression - or could index an array. */ -#define REGNO_REG_CLASS(REGNO) \ - ((REGNO) ? ((REGNO < 32) ? GENERAL_REGS : XRF_REGS) : AP_REG) - -/* The class value for index registers, and the one for base regs. */ -#define BASE_REG_CLASS AGRF_REGS -#define INDEX_REG_CLASS GENERAL_REGS - -/* Get reg_class from a letter such as appears in the machine description. - For the 88000, the following class/letter is defined for the XRF: - x - Extended register file */ -#define REG_CLASS_FROM_LETTER(C) \ - (((C) == 'x') ? XRF_REGS : NO_REGS) - -/* Macros to check register numbers against specific register classes. - These assume that REGNO is a hard or pseudo reg number. - They give nonzero only if REGNO is a hard reg of the suitable class - or a pseudo reg currently allocated to a suitable hard reg. - Since they use reg_renumber, they are safe only once reg_renumber - has been allocated, which happens in local-alloc.c. */ -#define REGNO_OK_FOR_BASE_P(REGNO) \ - ((REGNO) < FIRST_EXTENDED_REGISTER \ - || (unsigned) reg_renumber[REGNO] < FIRST_EXTENDED_REGISTER) -#define REGNO_OK_FOR_INDEX_P(REGNO) \ - (((REGNO) && (REGNO) < FIRST_EXTENDED_REGISTER) \ - || (unsigned) reg_renumber[REGNO] < FIRST_EXTENDED_REGISTER) - -/* Given an rtx X being reloaded into a reg required to be - in class CLASS, return the class of reg to actually use. - In general this is just CLASS; but on some machines - in some cases it is preferable to use a more restrictive class. - Double constants should be in a register iff they can be made cheaply. */ -#define PREFERRED_RELOAD_CLASS(X,CLASS) \ - (CONSTANT_P(X) && (CLASS == XRF_REGS) ? NO_REGS : (CLASS)) - -/* Return the register class of a scratch register needed to load IN - into a register of class CLASS in MODE. On the m88k, when PIC, we - need a temporary when loading some addresses into a register. */ -#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ - ((flag_pic \ - && GET_CODE (IN) == CONST \ - && GET_CODE (XEXP (IN, 0)) == PLUS \ - && GET_CODE (XEXP (XEXP (IN, 0), 0)) == CONST_INT \ - && ! SMALL_INT (XEXP (XEXP (IN, 0), 1))) ? GENERAL_REGS : NO_REGS) - -/* Return the maximum number of consecutive registers - needed to represent mode MODE in a register of class CLASS. */ -#define CLASS_MAX_NREGS(CLASS, MODE) \ - ((((CLASS) == XRF_REGS) ? 1 \ - : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) - -/* Letters in the range `I' through `P' in a register constraint string can - be used to stand for particular ranges of immediate operands. The C - expression is true iff C is a known letter and VALUE is appropriate for - that letter. - - For the m88000, the following constants are used: - `I' requires a non-negative 16-bit value. - `J' requires a non-positive 16-bit value. - `K' requires a non-negative value < 32. - `L' requires a constant with only the upper 16-bits set. - `M' requires constant values that can be formed with `set'. - `N' requires a negative value. - `O' requires zero. - `P' requires a non-negative value. */ - -/* Quick tests for certain values. */ -#define SMALL_INT(X) (SMALL_INTVAL (INTVAL (X))) -#define SMALL_INTVAL(I) ((unsigned) (I) < 0x10000) -#define ADD_INT(X) (ADD_INTVAL (INTVAL (X))) -#define ADD_INTVAL(I) ((unsigned) (I) + 0xffff < 0x1ffff) -#define POWER_OF_2(I) ((I) && POWER_OF_2_or_0(I)) -#define POWER_OF_2_or_0(I) (((I) & ((unsigned)(I) - 1)) == 0) - -#define CONST_OK_FOR_LETTER_P(VALUE, C) \ - ((C) == 'I' ? SMALL_INTVAL (VALUE) \ - : (C) == 'J' ? SMALL_INTVAL (-(VALUE)) \ - : (C) == 'K' ? (unsigned)(VALUE) < 32 \ - : (C) == 'L' ? ((VALUE) & 0xffff) == 0 \ - : (C) == 'M' ? integer_ok_for_set (VALUE) \ - : (C) == 'N' ? (VALUE) < 0 \ - : (C) == 'O' ? (VALUE) == 0 \ - : (C) == 'P' ? (VALUE) >= 0 \ - : 0) - -/* Similar, but for floating constants, and defining letters G and H. - Here VALUE is the CONST_DOUBLE rtx itself. For the m88000, the - constraints are: `G' requires zero, and `H' requires one or two. */ -#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ - ((C) == 'G' ? (CONST_DOUBLE_HIGH (VALUE) == 0 \ - && CONST_DOUBLE_LOW (VALUE) == 0) \ - : 0) - -/* Letters in the range `Q' through `U' in a register constraint string - may be defined in a machine-dependent fashion to stand for arbitrary - operand types. - - For the m88k, `Q' handles addresses in a call context. */ - -#define EXTRA_CONSTRAINT(OP, C) \ - ((C) == 'Q' ? symbolic_address_p (OP) : 0) - -/*** Describing Stack Layout ***/ - -/* Define this if pushing a word on the stack moves the stack pointer - to a smaller address. */ -#define STACK_GROWS_DOWNWARD - -/* Define this if the addresses of local variable slots are at negative - offsets from the frame pointer. */ -/* #define FRAME_GROWS_DOWNWARD */ - -/* Offset from the frame pointer to the first local variable slot to be - allocated. For the m88k, the debugger wants the return address (r1) - stored at location r30+4, and the previous frame pointer stored at - location r30. */ -#define STARTING_FRAME_OFFSET 8 - -/* If we generate an insn to push BYTES bytes, this says how many the - stack pointer really advances by. The m88k has no push instruction. */ -/* #define PUSH_ROUNDING(BYTES) */ - -/* If defined, the maximum amount of space required for outgoing arguments - will be computed and placed into the variable - `current_function_outgoing_args_size'. No space will be pushed - onto the stack for each call; instead, the function prologue should - increase the stack frame size by this amount. */ -#define ACCUMULATE_OUTGOING_ARGS 1 - -/* Offset from the stack pointer register to the first location at which - outgoing arguments are placed. Use the default value zero. */ -/* #define STACK_POINTER_OFFSET 0 */ - -/* Offset of first parameter from the argument pointer register value. - Using an argument pointer, this is 0 for the m88k. GCC knows - how to eliminate the argument pointer references if necessary. */ -#define FIRST_PARM_OFFSET(FNDECL) 0 - -/* Define this if functions should assume that stack space has been - allocated for arguments even when their values are passed in - registers. - - The value of this macro is the size, in bytes, of the area reserved for - arguments passed in registers. - - This space can either be allocated by the caller or be a part of the - machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' - says which. */ -#define REG_PARM_STACK_SPACE(FNDECL) 32 - -/* Define this macro if REG_PARM_STACK_SPACE is defined but stack - parameters don't skip the area specified by REG_PARM_STACK_SPACE. - Normally, when a parameter is not passed in registers, it is placed on - the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro - suppresses this behavior and causes the parameter to be passed on the - stack in its natural location. */ -#define STACK_PARMS_IN_REG_PARM_AREA - -/* Define this if it is the responsibility of the caller to allocate the - area reserved for arguments passed in registers. If - `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect of this - macro is to determine whether the space is included in - `current_function_outgoing_args_size'. */ -/* #define OUTGOING_REG_PARM_STACK_SPACE */ - -/* Offset from the stack pointer register to an item dynamically allocated - on the stack, e.g., by `alloca'. - - The default value for this macro is `STACK_POINTER_OFFSET' plus the - length of the outgoing arguments. The default is correct for most - machines. See `function.c' for details. */ -/* #define STACK_DYNAMIC_OFFSET(FUNDECL) ... */ - -/* Value is the number of bytes of arguments automatically - popped when returning from a subroutine call. - FUNDECL is the declaration node of the function (as a tree), - FUNTYPE is the data type of the function (as a tree), - or for a library call it is an identifier node for the subroutine name. - SIZE is the number of bytes of arguments passed on the stack. */ -#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 - -/* Define how to find the value returned by a function. - VALTYPE is the data type of the value (as a tree). - If the precise function being called is known, FUNC is its FUNCTION_DECL; - otherwise, FUNC is 0. */ -#define FUNCTION_VALUE(VALTYPE, FUNC) \ - gen_rtx_REG (TYPE_MODE (VALTYPE) == BLKmode ? SImode : TYPE_MODE (VALTYPE), \ - 2) - -/* Define this if it differs from FUNCTION_VALUE. */ -/* #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) ... */ - -/* Disable the promotion of some structures and unions to registers. */ -#define RETURN_IN_MEMORY(TYPE) \ - (TYPE_MODE (TYPE) == BLKmode \ - || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \ - && !(TYPE_MODE (TYPE) == SImode \ - || (TYPE_MODE (TYPE) == BLKmode \ - && TYPE_ALIGN (TYPE) == BITS_PER_WORD \ - && int_size_in_bytes (TYPE) == UNITS_PER_WORD)))) - -/* Don't default to pcc-struct-return, because we have already specified - exactly how to return structures in the RETURN_IN_MEMORY macro. */ -#define DEFAULT_PCC_STRUCT_RETURN 0 - -/* Define how to find the value returned by a library function - assuming the value has mode MODE. */ -#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 2) - -/* True if N is a possible register number for a function value - as seen by the caller. */ -#define FUNCTION_VALUE_REGNO_P(N) ((N) == 2) - -/* Determine whether a function argument is passed in a register, and - which register. See m88k.c. */ -#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ - m88k_function_arg (CUM, MODE, TYPE, NAMED) - -/* Define this if it differs from FUNCTION_ARG. */ -/* #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) ... */ - -/* A C expression for the number of words, at the beginning of an - argument, must be put in registers. The value must be zero for - arguments that are passed entirely in registers or that are entirely - pushed on the stack. */ -#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0) - -/* A C expression that indicates when an argument must be passed by - reference. If nonzero for an argument, a copy of that argument is - made in memory and a pointer to the argument is passed instead of the - argument itself. The pointer is passed in whatever way is appropriate - for passing a pointer to that type. */ -#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) (0) - -/* A C type for declaring a variable that is used as the first argument - of `FUNCTION_ARG' and other related values. It suffices to count - the number of words of argument so far. */ -#define CUMULATIVE_ARGS int - -/* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a - function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ -#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) ((CUM) = 0) - -/* A C statement (sans semicolon) to update the summarizer variable - CUM to advance past an argument in the argument list. The values - MODE, TYPE and NAMED describe that argument. Once this is done, - the variable CUM is suitable for analyzing the *following* argument - with `FUNCTION_ARG', etc. (TYPE is null for libcalls where that - information may not be available.) */ -#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ - do { \ - enum machine_mode __mode = (TYPE) ? TYPE_MODE (TYPE) : (MODE); \ - if ((CUM & 1) \ - && (__mode == DImode || __mode == DFmode \ - || ((TYPE) && TYPE_ALIGN (TYPE) > BITS_PER_WORD))) \ - CUM++; \ - CUM += (((__mode != BLKmode) \ - ? GET_MODE_SIZE (MODE) : int_size_in_bytes (TYPE)) \ - + 3) / 4; \ - } while (0) - -/* True if N is a possible register number for function argument passing. - On the m88000, these are registers 2 through 9. */ -#define FUNCTION_ARG_REGNO_P(N) ((N) <= 9 && (N) >= 2) - -/* A C expression which determines whether, and in which direction, - to pad out an argument with extra space. The value should be of - type `enum direction': either `upward' to pad above the argument, - `downward' to pad below, or `none' to inhibit padding. - - This macro does not control the *amount* of padding; that is always - just enough to reach the next multiple of `FUNCTION_ARG_BOUNDARY'. */ -#define FUNCTION_ARG_PADDING(MODE, TYPE) \ - ((MODE) == BLKmode \ - || ((TYPE) && (TREE_CODE (TYPE) == RECORD_TYPE \ - || TREE_CODE (TYPE) == UNION_TYPE)) \ - ? upward : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY ? downward : none) - -/* If defined, a C expression that gives the alignment boundary, in bits, - of an argument with the specified mode and type. If it is not defined, - `PARM_BOUNDARY' is used for all arguments. */ -#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ - (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \ - ? PARM_BOUNDARY : 2 * PARM_BOUNDARY) - -/* Generate necessary RTL for __builtin_saveregs(). - ARGLIST is the argument list; see expr.c. */ -#define EXPAND_BUILTIN_SAVEREGS() m88k_builtin_saveregs () - -/* Define the `__builtin_va_list' type for the ABI. */ -#define BUILD_VA_LIST_TYPE(VALIST) \ - (VALIST) = m88k_build_va_list () - -/* Implement `va_start' for varargs and stdarg. */ -#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ - m88k_va_start (valist, nextarg) - -/* Implement `va_arg'. */ -#define EXPAND_BUILTIN_VA_ARG(valist, type) \ - m88k_va_arg (valist, type) - -/* Output assembler code to FILE to increment profiler label # LABELNO - for profiling a function entry. Redefined in sysv3.h, sysv4.h and - dgux.h. */ -#define FUNCTION_PROFILER(FILE, LABELNO) \ - output_function_profiler (FILE, LABELNO, "mcount", 1) - -/* Maximum length in instructions of the code output by FUNCTION_PROFILER. */ -#define FUNCTION_PROFILER_LENGTH (5+3+1+5) - -/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, - the stack pointer does not matter. The value is tested only in - functions that have frame pointers. - No definition is equivalent to always zero. */ -#define EXIT_IGNORE_STACK (1) - -/* Value should be nonzero if functions must have frame pointers. - Zero means the frame pointer need not be set up (and parms - may be accessed via the stack pointer) in functions that seem suitable. - This is computed in `reload', in reload1.c. */ -#define FRAME_POINTER_REQUIRED \ -((TARGET_OMIT_LEAF_FRAME_POINTER && !leaf_function_p ()) \ - || (write_symbols != NO_DEBUG && !TARGET_OCS_FRAME_POSITION)) - -/* Definitions for register eliminations. - - We have two registers that can be eliminated on the m88k. First, the - frame pointer register can often be eliminated in favor of the stack - pointer register. Secondly, the argument pointer register can always be - eliminated; it is replaced with either the stack or frame pointer. */ - -/* This is an array of structures. Each structure initializes one pair - of eliminable registers. The "from" register number is given first, - followed by "to". Eliminations of the same "from" register are listed - in order of preference. */ -#define ELIMINABLE_REGS \ -{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ - { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ - { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} - -/* Given FROM and TO register numbers, say whether this elimination - is allowed. */ -#define CAN_ELIMINATE(FROM, TO) \ - (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) - -/* Define the offset between two registers, one to be eliminated, and the other - its replacement, at the start of a routine. */ -#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -{ m88k_layout_frame (); \ - if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ - (OFFSET) = m88k_fp_offset; \ - else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ - (OFFSET) = m88k_stack_size - m88k_fp_offset; \ - else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ - (OFFSET) = m88k_stack_size; \ - else \ - abort (); \ -} - -/*** Trampolines for Nested Functions ***/ - -/* Output assembler code for a block containing the constant parts - of a trampoline, leaving space for the variable parts. - - This block is placed on the stack and filled in. It is aligned - 0 mod 128 and those portions that are executed are constant. - This should work for instruction caches that have cache lines up - to the aligned amount (128 is arbitrary), provided no other code - producer is attempting to play the same game. This of course is - in violation of any number of 88open standards. */ - -#define TRAMPOLINE_TEMPLATE(FILE) \ -{ \ - char buf[256]; \ - static int labelno = 0; \ - labelno++; \ - ASM_GENERATE_INTERNAL_LABEL (buf, "LTRMP", labelno); \ - /* Save the return address (r1) in the static chain reg (r11). */ \ - fprintf (FILE, "\tor\t %s,%s,0\n", reg_names[11], reg_names[1]); \ - /* Locate this block; transfer to the next instruction. */ \ - fprintf (FILE, "\tbsr\t %s\n", &buf[1]); \ - (*targetm.asm_out.internal_label) (FILE, "LTRMP", labelno); \ - /* Save r10; use it as the relative pointer; restore r1. */ \ - fprintf (FILE, "\tst\t %s,%s,24\n", reg_names[10], reg_names[1]); \ - fprintf (FILE, "\tor\t %s,%s,0\n", reg_names[10], reg_names[1]); \ - fprintf (FILE, "\tor\t %s,%s,0\n", reg_names[1], reg_names[11]); \ - /* Load the function's address and go there. */ \ - fprintf (FILE, "\tld\t %s,%s,32\n", reg_names[11], reg_names[10]); \ - fprintf (FILE, "\tjmp.n\t %s\n", reg_names[11]); \ - /* Restore r10 and load the static chain register. */ \ - fprintf (FILE, "\tld.d\t %s,%s,24\n", reg_names[10], reg_names[10]); \ - /* Storage: r10 save area, static chain, function address. */ \ - assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ - assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ - assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ -} - -/* Length in units of the trampoline for entering a nested function. - This is really two components. The first 32 bytes are fixed and - must be copied; the last 12 bytes are just storage that's filled - in later. So for allocation purposes, it's 32+12 bytes, but for - initialization purposes, it's 32 bytes. */ - -#define TRAMPOLINE_SIZE (32+12) - -/* Alignment required for a trampoline. 128 is used to find the - beginning of a line in the instruction cache and to allow for - instruction cache lines of up to 128 bytes. */ - -#define TRAMPOLINE_ALIGNMENT 128 - -/* Emit RTL insns to initialize the variable parts of a trampoline. - FNADDR is an RTX for the address of the function's pure code. - CXT is an RTX for the static chain value for the function. */ - -#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -{ \ - emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 40)), FNADDR); \ - emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 36)), CXT); \ -} - -/*** Library Subroutine Names ***/ - -/* Define this macro if GNU CC should generate calls to the System V - (and ANSI C) library functions `memcpy' and `memset' rather than - the BSD functions `bcopy' and `bzero'. */ -#define TARGET_MEM_FUNCTIONS - -/*** Addressing Modes ***/ - -#define SELECT_CC_MODE(OP,X,Y) CCmode - -/* Recognize any constant value that is a valid address. - When PIC, we do not accept an address that would require a scratch reg - to load into a register. */ - -#define CONSTANT_ADDRESS_P(X) \ - (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ - || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ - || (GET_CODE (X) == CONST \ - && ! (flag_pic && pic_address_needs_scratch (X)))) - - -/* Maximum number of registers that can appear in a valid memory address. */ -#define MAX_REGS_PER_ADDRESS 2 - -/* The condition for memory shift insns. */ -#define SCALED_ADDRESS_P(ADDR) \ - (GET_CODE (ADDR) == PLUS \ - && (GET_CODE (XEXP (ADDR, 0)) == MULT \ - || GET_CODE (XEXP (ADDR, 1)) == MULT)) - -/* Can the reference to X be made short? */ -#define SHORT_ADDRESS_P(X,TEMP) \ - ((TEMP) = (GET_CODE (X) == CONST ? get_related_value (X) : X), \ - ((TEMP) && GET_CODE (TEMP) == SYMBOL_REF && SYMBOL_REF_FLAG (TEMP))) - -/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression - that is a valid memory address for an instruction. - The MODE argument is the machine mode for the MEM expression - that wants to use this address. - - On the m88000, a legitimate address has the form REG, REG+REG, - REG+SMALLINT, REG+(REG*modesize) (REG[REG]), or SMALLINT. - - The register elimination process should deal with the argument - pointer and frame pointer changing to REG+SMALLINT. */ - -#define LEGITIMATE_INDEX_P(X, MODE) \ - ((GET_CODE (X) == CONST_INT \ - && SMALL_INT (X)) \ - || (REG_P (X) \ - && REG_OK_FOR_INDEX_P (X)) \ - || (GET_CODE (X) == MULT \ - && REG_P (XEXP (X, 0)) \ - && REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ - && GET_CODE (XEXP (X, 1)) == CONST_INT \ - && INTVAL (XEXP (X, 1)) == GET_MODE_SIZE (MODE))) - -#define RTX_OK_FOR_BASE_P(X) \ - ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ - || (GET_CODE (X) == SUBREG \ - && GET_CODE (SUBREG_REG (X)) == REG \ - && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) - -#define RTX_OK_FOR_INDEX_P(X) \ - ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ - || (GET_CODE (X) == SUBREG \ - && GET_CODE (SUBREG_REG (X)) == REG \ - && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) - -#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -{ \ - register rtx _x; \ - if (REG_P (X)) \ - { \ - if (REG_OK_FOR_BASE_P (X)) \ - goto ADDR; \ - } \ - else if (GET_CODE (X) == PLUS) \ - { \ - register rtx _x0 = XEXP (X, 0); \ - register rtx _x1 = XEXP (X, 1); \ - if ((flag_pic \ - && _x0 == pic_offset_table_rtx \ - && (flag_pic == 2 \ - ? RTX_OK_FOR_BASE_P (_x1) \ - : (GET_CODE (_x1) == SYMBOL_REF \ - || GET_CODE (_x1) == LABEL_REF))) \ - || (REG_P (_x0) \ - && (REG_OK_FOR_BASE_P (_x0) \ - && LEGITIMATE_INDEX_P (_x1, MODE))) \ - || (REG_P (_x1) \ - && (REG_OK_FOR_BASE_P (_x1) \ - && LEGITIMATE_INDEX_P (_x0, MODE)))) \ - goto ADDR; \ - } \ - else if (GET_CODE (X) == LO_SUM) \ - { \ - register rtx _x0 = XEXP (X, 0); \ - register rtx _x1 = XEXP (X, 1); \ - if (((REG_P (_x0) \ - && REG_OK_FOR_BASE_P (_x0)) \ - || (GET_CODE (_x0) == SUBREG \ - && REG_P (SUBREG_REG (_x0)) \ - && REG_OK_FOR_BASE_P (SUBREG_REG (_x0)))) \ - && CONSTANT_P (_x1)) \ - goto ADDR; \ - } \ - else if (GET_CODE (X) == CONST_INT \ - && SMALL_INT (X)) \ - goto ADDR; \ - else if (SHORT_ADDRESS_P (X, _x)) \ - goto ADDR; \ -} - -/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx - and check its validity for a certain class. - We have two alternate definitions for each of them. - The usual definition accepts all pseudo regs; the other rejects - them unless they have been allocated suitable hard regs. - The symbol REG_OK_STRICT causes the latter definition to be used. - - Most source files want to accept pseudo regs in the hope that - they will get allocated to the class that the insn wants them to be in. - Source files for reload pass need to be strict. - After reload, it makes no difference, since pseudo regs have - been eliminated by then. */ - -#ifndef REG_OK_STRICT - -/* Nonzero if X is a hard reg that can be used as an index - or if it is a pseudo reg. Not the argument pointer. */ -#define REG_OK_FOR_INDEX_P(X) \ - (!XRF_REGNO_P(REGNO (X))) -/* Nonzero if X is a hard reg that can be used as a base reg - or if it is a pseudo reg. */ -#define REG_OK_FOR_BASE_P(X) (REG_OK_FOR_INDEX_P (X)) - -#else - -/* Nonzero if X is a hard reg that can be used as an index. */ -#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) -/* Nonzero if X is a hard reg that can be used as a base reg. */ -#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) - -#endif - -/* Try machine-dependent ways of modifying an illegitimate address - to be legitimate. If we find one, return the new, valid address. - This macro is used in only one place: `memory_address' in explow.c. - - OLDX is the address as it was before break_out_memory_refs was called. - In some cases it is useful to look at this to decide what needs to be done. - - MODE and WIN are passed so that this macro can use - GO_IF_LEGITIMATE_ADDRESS. - - It is always safe for this macro to do nothing. It exists to recognize - opportunities to optimize the output. */ - -/* On the m88000, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ - -#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ -{ \ - if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ - (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \ - copy_to_mode_reg (SImode, XEXP (X, 1))); \ - if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ - (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \ - copy_to_mode_reg (SImode, XEXP (X, 0))); \ - if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ - (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \ - force_operand (XEXP (X, 0), 0)); \ - if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ - (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \ - force_operand (XEXP (X, 1), 0)); \ - if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ - (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\ - XEXP (X, 1)); \ - if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ - (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ - force_operand (XEXP (X, 1), NULL_RTX)); \ - if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ - || GET_CODE (X) == LABEL_REF) \ - (X) = legitimize_address (flag_pic, X, 0, 0); \ - if (memory_address_p (MODE, X)) \ - goto WIN; } - -/* Go to LABEL if ADDR (a legitimate address expression) - has an effect that depends on the machine mode it is used for. - On the m88000 this is never true. */ - -#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) - -/* Nonzero if the constant value X is a legitimate general operand. - It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ -#define LEGITIMATE_CONSTANT_P(X) (1) - -/* Define this, so that when PIC, reload won't try to reload invalid - addresses which require two reload registers. */ - -#define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) - - -/*** Condition Code Information ***/ - -/* C code for a data type which is used for declaring the `mdep' - component of `cc_status'. It defaults to `int'. */ -/* #define CC_STATUS_MDEP int */ - -/* A C expression to initialize the `mdep' field to "empty". */ -/* #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) */ - -/* Macro to zap the normal portions of CC_STATUS, but leave the - machine dependent parts (ie, literal synthesis) alone. */ -/* #define CC_STATUS_INIT_NO_MDEP \ - (cc_status.flags = 0, cc_status.value1 = 0, cc_status.value2 = 0) */ - -/* When using a register to hold the condition codes, the cc_status - mechanism cannot be used. */ -#define NOTICE_UPDATE_CC(EXP, INSN) (0) - -/*** Miscellaneous Parameters ***/ - -/* Define the codes that are matched by predicates in m88k.c. */ -#define PREDICATE_CODES \ - {"move_operand", {SUBREG, REG, CONST_INT, LO_SUM, MEM}}, \ - {"call_address_operand", {SUBREG, REG, SYMBOL_REF, LABEL_REF, CONST}}, \ - {"arith_operand", {SUBREG, REG, CONST_INT}}, \ - {"arith5_operand", {SUBREG, REG, CONST_INT}}, \ - {"arith32_operand", {SUBREG, REG, CONST_INT}}, \ - {"arith64_operand", {SUBREG, REG, CONST_INT}}, \ - {"int5_operand", {CONST_INT}}, \ - {"int32_operand", {CONST_INT}}, \ - {"add_operand", {SUBREG, REG, CONST_INT}}, \ - {"reg_or_bbx_mask_operand", {SUBREG, REG, CONST_INT}}, \ - {"real_or_0_operand", {SUBREG, REG, CONST_DOUBLE}}, \ - {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ - {"relop", {EQ, NE, LT, LE, GE, GT, LTU, LEU, GEU, GTU}}, \ - {"even_relop", {EQ, LT, GT, LTU, GTU}}, \ - {"odd_relop", { NE, LE, GE, LEU, GEU}}, \ - {"partial_ccmode_register_operand", { SUBREG, REG}}, \ - {"relop_no_unsigned", {EQ, NE, LT, LE, GE, GT}}, \ - {"equality_op", {EQ, NE}}, \ - {"pc_or_label_ref", {PC, LABEL_REF}}, - -/* A list of predicates that do special things with modes, and so - should not elicit warnings for VOIDmode match_operand. */ - -#define SPECIAL_MODE_PREDICATES \ - "partial_ccmode_register_operand", \ - "pc_or_label_ref", - -/* The case table contains either words or branch instructions. This says - which. We always claim that the vector is PC-relative. It is position - independent when -fpic is used. */ -#define CASE_VECTOR_INSNS (TARGET_88100 || flag_pic) - -/* An alias for a machine mode name. This is the machine mode that - elements of a jump-table should have. */ -#define CASE_VECTOR_MODE SImode - -/* Define as C expression which evaluates to nonzero if the tablejump - instruction expects the table to contain offsets from the address of the - table. - Do not define this if the table should contain absolute addresses. */ -#define CASE_VECTOR_PC_RELATIVE 1 - -/* Define this if control falls through a `case' insn when the index - value is out of range. This means the specified default-label is - actually ignored by the `case' insn proper. */ -/* #define CASE_DROPS_THROUGH */ - -/* Define this to be the smallest number of different values for which it - is best to use a jump-table instead of a tree of conditional branches. - The default is 4 for machines with a casesi instruction and 5 otherwise. - The best 88110 number is around 7, though the exact number isn't yet - known. A third alternative for the 88110 is to use a binary tree of - bb1 instructions on bits 2/1/0 if the range is dense. This may not - win very much though. */ -#define CASE_VALUES_THRESHOLD (TARGET_88100 ? 4 : 7) - -/* Define this as 1 if `char' should by default be signed; else as 0. */ -#define DEFAULT_SIGNED_CHAR 1 - -/* The 88open ABI says size_t is unsigned int. */ -#define SIZE_TYPE "unsigned int" - -/* Handle #pragma pack and sometimes #pragma weak. */ -#define HANDLE_SYSV_PRAGMA 1 - -/* Tell when to handle #pragma weak. This is only done for V.4. */ -#define SUPPORTS_WEAK TARGET_SVR4 -#define SUPPORTS_ONE_ONLY TARGET_SVR4 - -/* Max number of bytes we can move from memory to memory - in one reasonably fast instruction. */ -#define MOVE_MAX 8 - -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bigs in the register. */ -#define BYTE_LOADS_ZERO_EXTEND - -/* Zero if access to memory by bytes is faster. */ -#define SLOW_BYTE_ACCESS 1 - -/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits - is done just by pretending it is already truncated. */ -#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 - -/* Define this if addresses of constant functions - shouldn't be put through pseudo regs where they can be cse'd. - Desirable on machines where ordinary constants are expensive - but a CALL with constant address is cheap. */ -#define NO_FUNCTION_CSE - -/* Define this macro if an argument declared as `char' or - `short' in a prototype should actually be passed as an - `int'. In addition to avoiding errors in certain cases of - mismatch, it also makes for better code on certain machines. */ -#define PROMOTE_PROTOTYPES 1 - -/* We assume that the store-condition-codes instructions store 0 for false - and some other value for true. This is the value stored for true. */ -#define STORE_FLAG_VALUE (-1) - -/* Specify the machine mode that pointers have. - After generation of rtl, the compiler makes no further distinction - between pointers and any other objects of this machine mode. */ -#define Pmode SImode - -/* A function address in a call instruction - is a word address (for indexing purposes) - so give the MEM rtx word mode. */ -#define FUNCTION_MODE SImode - -/* A barrier will be aligned so account for the possible expansion. - A volatile load may be preceded by a serializing instruction. - Account for profiling code output at NOTE_INSN_PROLOGUE_END. - Account for block profiling code at basic block boundaries. */ -#define ADJUST_INSN_LENGTH(RTX, LENGTH) \ - if (GET_CODE (RTX) == BARRIER \ - || (TARGET_SERIALIZE_VOLATILE \ - && GET_CODE (RTX) == INSN \ - && GET_CODE (PATTERN (RTX)) == SET \ - && ((GET_CODE (SET_SRC (PATTERN (RTX))) == MEM \ - && MEM_VOLATILE_P (SET_SRC (PATTERN (RTX))))))) \ - LENGTH += 1; \ - else if (GET_CODE (RTX) == NOTE \ - && NOTE_LINE_NUMBER (RTX) == NOTE_INSN_PROLOGUE_END) \ - { \ - if (current_function_profile) \ - LENGTH += (FUNCTION_PROFILER_LENGTH + REG_PUSH_LENGTH \ - + REG_POP_LENGTH); \ - } \ - -/* Track the state of the last volatile memory reference. Clear the - state with CC_STATUS_INIT for now. */ -#define CC_STATUS_INIT m88k_volatile_code = '\0' - -/* A C expressions returning the cost of moving data of MODE from a register - to or from memory. This is more costly than between registers. */ -#define MEMORY_MOVE_COST(MODE,CLASS,IN) 4 - -/* Provide the cost of a branch. Exact meaning under development. */ -#define BRANCH_COST (TARGET_88100 ? 1 : 2) - -/* Do not break .stabs pseudos into continuations. */ -#define DBX_CONTIN_LENGTH 0 - -/*** Output of Assembler Code ***/ - -/* Control the assembler format that we output. */ - -/* A C string constant describing how to begin a comment in the target - assembler language. The compiler assumes that the comment will end at - the end of the line. */ -#define ASM_COMMENT_START ";" - -/* Allow pseudo-ops to be overridden. Override these in svr[34].h. */ -#undef ASCII_DATA_ASM_OP -#undef READONLY_DATA_SECTION_ASM_OP -#undef CTORS_SECTION_ASM_OP -#undef DTORS_SECTION_ASM_OP -#undef TARGET_ASM_NAMED_SECTION -#undef INIT_SECTION_ASM_OP -#undef FINI_SECTION_ASM_OP -#undef TYPE_ASM_OP -#undef SIZE_ASM_OP -#undef SET_ASM_OP -#undef SKIP_ASM_OP -#undef COMMON_ASM_OP -#undef ALIGN_ASM_OP -#undef IDENT_ASM_OP - -/* These are used in varasm.c as well. */ -#define TEXT_SECTION_ASM_OP "\ttext" -#define DATA_SECTION_ASM_OP "\tdata" - -/* Other sections. */ -#define READONLY_DATA_SECTION_ASM_OP (TARGET_SVR4 \ - ? "\tsection\t .rodata,\"a\"" \ - : "\tsection\t .rodata,\"x\"") -#define TDESC_SECTION_ASM_OP (TARGET_SVR4 \ - ? "\tsection\t .tdesc,\"a\"" \ - : "\tsection\t .tdesc,\"x\"") - -/* These must be constant strings for crtstuff.c. */ -#define CTORS_SECTION_ASM_OP "\tsection\t .ctors,\"d\"" -#define DTORS_SECTION_ASM_OP "\tsection\t .dtors,\"d\"" -#define INIT_SECTION_ASM_OP "\tsection\t .init,\"x\"" -#define FINI_SECTION_ASM_OP "\tsection\t .fini,\"x\"" - -/* These are pretty much common to all assemblers. */ -#define IDENT_ASM_OP "\tident\t" -#define FILE_ASM_OP "\tfile\t" -#define SET_ASM_OP "\tdef\t" -#define GLOBAL_ASM_OP "\tglobal\t" -#define ALIGN_ASM_OP "\talign\t" -#define SKIP_ASM_OP "\tzero\t" -#define COMMON_ASM_OP "\tcomm\t" -#define BSS_ASM_OP "\tbss\t" -#define FLOAT_ASM_OP "\tfloat\t" -#define DOUBLE_ASM_OP "\tdouble\t" -#define ASCII_DATA_ASM_OP "\tstring\t" - -/* These are particular to the global pool optimization. */ -#define SBSS_ASM_OP "\tsbss\t" -#define SCOMM_ASM_OP "\tscomm\t" -#define SDATA_SECTION_ASM_OP "\tsdata" - -/* These are specific to PIC. */ -#define TYPE_ASM_OP "\ttype\t" -#define SIZE_ASM_OP "\tsize\t" -#ifndef AS_BUG_POUND_TYPE /* Faulty assemblers require @ rather than #. */ -#undef TYPE_OPERAND_FMT -#define TYPE_OPERAND_FMT "#%s" -#endif - -/* This is how we tell the assembler that a symbol is weak. */ - -#undef ASM_WEAKEN_LABEL -#define ASM_WEAKEN_LABEL(FILE,NAME) \ - do { fputs ("\tweak\t", FILE); assemble_name (FILE, NAME); \ - fputc ('\n', FILE); } while (0) - -/* These are specific to version 03.00 assembler syntax. */ -#define INTERNAL_ASM_OP "\tlocal\t" -#define VERSION_ASM_OP "\tversion\t" -#define PUSHSECTION_ASM_OP "\tsection\t" -#define POPSECTION_ASM_OP "\tprevious" - -/* These are specific to the version 04.00 assembler syntax. */ -#define REQUIRES_88110_ASM_OP "\trequires_88110" - -/* Output any initial stuff to the assembly file. Always put out - a file directive, even if not debugging. - - Immediately after putting out the file, put out a "sem.<value>" - declaration. This should be harmless on other systems, and - is used in DG/UX by the debuggers to supplement COFF. The - fields in the integer value are as follows: - - Bits Value Meaning - ---- ----- ------- - 0-1 0 No information about stack locations - 1 Auto/param locations are based on r30 - 2 Auto/param locations are based on CFA - - 3-2 0 No information on dimension order - 1 Array dims in sym table matches source language - 2 Array dims in sym table is in reverse order - - 5-4 0 No information about the case of global names - 1 Global names appear in the symbol table as in the source - 2 Global names have been converted to lower case - 3 Global names have been converted to upper case. */ - -#ifdef SDB_DEBUGGING_INFO -#define ASM_COFFSEM(FILE) \ - if (write_symbols == SDB_DEBUG) \ - { \ - fprintf (FILE, "\nsem.%x:\t\t; %s\n", \ - (((TARGET_OCS_FRAME_POSITION) ? 2 : 1) << 0) + (1 << 2) + (1 << 4),\ - (TARGET_OCS_FRAME_POSITION) \ - ? "frame is CFA, normal array dims, case unchanged" \ - : "frame is r30, normal array dims, case unchanged"); \ - } -#else -#define ASM_COFFSEM(FILE) -#endif - -/* Output the first line of the assembly file. Redefined in dgux.h. */ - -#define ASM_FIRST_LINE(FILE) \ - do { \ - if (TARGET_SVR4) \ - { \ - if (TARGET_88110) \ - fprintf (FILE, "%s\"%s\"\n", VERSION_ASM_OP, "04.00"); \ - else \ - fprintf (FILE, "%s\"%s\"\n", VERSION_ASM_OP, "03.00"); \ - } \ - } while (0) - -/* Override svr[34].h. */ -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) \ - output_file_start (FILE, \ - (struct m88k_lang_independent_options *) f_options, \ - ARRAY_SIZE (f_options), \ - (struct m88k_lang_independent_options *) W_options, \ - ARRAY_SIZE (W_options)) - -#undef ASM_FILE_END - -#define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) \ - do { \ - fputs (FILE_ASM_OP, FILE); \ - output_quoted_string (FILE, NAME); \ - putc ('\n', FILE); \ - } while (0) - -#ifdef SDB_DEBUGGING_INFO -#undef ASM_OUTPUT_SOURCE_LINE -#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ - if (m88k_prologue_done) \ - fprintf (FILE, "\n\tln\t %d\t\t\t\t; Real source line %d\n",\ - LINE - sdb_begin_function_line, LINE) -#endif - -/* Code to handle #ident directives. Override svr[34].h definition. */ -#undef ASM_OUTPUT_IDENT -#ifdef DBX_DEBUGGING_INFO -#define ASM_OUTPUT_IDENT(FILE, NAME) -#else -#define ASM_OUTPUT_IDENT(FILE, NAME) \ - output_ascii (FILE, IDENT_ASM_OP, 4000, NAME, strlen (NAME)); -#endif - -/* Output to assembler file text saying following lines - may contain character constants, extra white space, comments, etc. */ -#define ASM_APP_ON "" - -/* Output to assembler file text saying following lines - no longer contain unusual constructs. */ -#define ASM_APP_OFF "" - -/* Format the assembly opcode so that the arguments are all aligned. - The maximum instruction size is 8 characters (fxxx.xxx), so a tab and a - space will do to align the output. Abandon the output if a `%' is - encountered. */ -#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ - { \ - int ch; \ - const char *orig_ptr; \ - \ - for (orig_ptr = (PTR); \ - (ch = *(PTR)) && ch != ' ' && ch != '\t' && ch != '\n' && ch != '%'; \ - (PTR)++) \ - putc (ch, STREAM); \ - \ - if (ch == ' ' && orig_ptr != (PTR) && (PTR) - orig_ptr < 8) \ - putc ('\t', STREAM); \ - } - -/* How to refer to registers in assembler output. - This sequence is indexed by compiler's hard-register-number. - Updated by OVERRIDE_OPTIONS to include the # for version 03.00 syntax. */ - -#define REGISTER_NAMES \ - {"#r0"+1, "#r1"+1, "#r2"+1, "#r3"+1, "#r4"+1, "#r5"+1, "#r6"+1, "#r7"+1, \ - "#r8"+1, "#r9"+1, "#r10"+1,"#r11"+1,"#r12"+1,"#r13"+1,"#r14"+1,"#r15"+1,\ - "#r16"+1,"#r17"+1,"#r18"+1,"#r19"+1,"#r20"+1,"#r21"+1,"#r22"+1,"#r23"+1,\ - "#r24"+1,"#r25"+1,"#r26"+1,"#r27"+1,"#r28"+1,"#r29"+1,"#r30"+1,"#r31"+1,\ - "#x0"+1, "#x1"+1, "#x2"+1, "#x3"+1, "#x4"+1, "#x5"+1, "#x6"+1, "#x7"+1, \ - "#x8"+1, "#x9"+1, "#x10"+1,"#x11"+1,"#x12"+1,"#x13"+1,"#x14"+1,"#x15"+1,\ - "#x16"+1,"#x17"+1,"#x18"+1,"#x19"+1,"#x20"+1,"#x21"+1,"#x22"+1,"#x23"+1,\ - "#x24"+1,"#x25"+1,"#x26"+1,"#x27"+1,"#x28"+1,"#x29"+1,"#x30"+1,"#x31"+1} - -/* Define additional names for use in asm clobbers and asm declarations. - - We define the fake Condition Code register as an alias for reg 0 (which - is our `condition code' register), so that condition codes can easily - be clobbered by an asm. The carry bit in the PSR is now used. */ - -#define ADDITIONAL_REGISTER_NAMES {{"psr", 0}, {"cc", 0}} - -/* Tell when to declare ASM names. Override svr4.h to provide this hook. */ -#undef DECLARE_ASM_NAME -#define DECLARE_ASM_NAME TARGET_SVR4 - -/* Write the extra assembler code needed to declare a function properly. */ -#undef ASM_DECLARE_FUNCTION_NAME -#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ - do { \ - if (DECLARE_ASM_NAME) \ - ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ - ASM_OUTPUT_LABEL(FILE, NAME); \ - } while (0) - -/* Write the extra assembler code needed to declare an object properly. */ -#undef ASM_DECLARE_OBJECT_NAME -#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ - do { \ - if (DECLARE_ASM_NAME) \ - { \ - HOST_WIDE_INT size; \ - \ - ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ - \ - size_directive_output = 0; \ - if (!flag_inhibit_size_directive \ - && (DECL) && DECL_SIZE (DECL)) \ - { \ - size_directive_output = 1; \ - size = int_size_in_bytes (TREE_TYPE (DECL)); \ - ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, size); \ - } \ - } \ - ASM_OUTPUT_LABEL(FILE, NAME); \ - } while (0); - -/* Output the size directive for a decl in rest_of_decl_compilation - in the case where we did not do so before the initializer. - Once we find the error_mark_node, we know that the value of - size_directive_output was set - by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ - -#undef ASM_FINISH_DECLARE_OBJECT -#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ -do { \ - const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ - HOST_WIDE_INT size; \ - if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ - && DECLARE_ASM_NAME \ - && ! AT_END && TOP_LEVEL \ - && DECL_INITIAL (DECL) == error_mark_node \ - && !size_directive_output) \ - { \ - size_directive_output = 1; \ - size = int_size_in_bytes (TREE_TYPE (DECL)); \ - ASM_OUTPUT_SIZE_DIRECTIVE (FILE, name, size); \ - } \ - } while (0) - -/* This is how to declare the size of a function. */ -#undef ASM_DECLARE_FUNCTION_SIZE -#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ - do { \ - if (DECLARE_ASM_NAME && !flag_inhibit_size_directive) \ - ASM_OUTPUT_MEASURED_SIZE (FILE, FNAME); \ - } while (0) - -/* The prefix to add to user-visible assembler symbols. - Override svr[34].h. */ -#undef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "_" - -/* This is how to output a reference to a user-level label named NAME. - Override svr[34].h. */ -#undef ASM_OUTPUT_LABELREF -#define ASM_OUTPUT_LABELREF(FILE,NAME) \ - { \ - if (!TARGET_NO_UNDERSCORES && !TARGET_SVR4) \ - fputc ('_', FILE); \ - fputs (NAME, FILE); \ - } - -/* This is how to store into the string LABEL - the symbol_ref name of an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. - This is suitable for output with `assemble_name'. This must agree - with (*targetm.asm_out.internal_label) above, except for being prefixed - with an `*'. */ - -#undef ASM_GENERATE_INTERNAL_LABEL -#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ - sprintf (LABEL, TARGET_SVR4 ? "*.%s%ld" : "*@%s%ld", PREFIX, (long)(NUM)) - -/* The single-byte pseudo-op is the default. Override svr[34].h. */ -#undef ASM_OUTPUT_ASCII -#define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ - output_ascii (FILE, ASCII_DATA_ASM_OP, 48, P, SIZE) - -/* Override svr4.h. Change to the readonly data section for a table of - addresses. final_scan_insn changes back to the text section. */ -#undef ASM_OUTPUT_CASE_LABEL -#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \ - do { \ - if (! CASE_VECTOR_INSNS) \ - { \ - readonly_data_section (); \ - ASM_OUTPUT_ALIGN (FILE, 2); \ - } \ - (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ - } while (0) - -/* Epilogue for case labels. This jump instruction is called by casesi - to transfer to the appropriate branch instruction within the table. - The label `@L<n>e' is coined to mark the end of the table. */ -#define ASM_OUTPUT_CASE_END(FILE, NUM, TABLE) \ - do { \ - if (CASE_VECTOR_INSNS) \ - { \ - char label[256]; \ - ASM_GENERATE_INTERNAL_LABEL (label, "L", NUM); \ - fprintf (FILE, "%se:\n", &label[1]); \ - if (! flag_delayed_branch) \ - fprintf (FILE, "\tlda\t %s,%s[%s]\n", reg_names[1], \ - reg_names[1], reg_names[m88k_case_index]); \ - fprintf (FILE, "\tjmp\t %s\n", reg_names[1]); \ - } \ - } while (0) - -/* This is how to output an element of a case-vector that is absolute. */ -#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ - do { \ - char buffer[256]; \ - ASM_GENERATE_INTERNAL_LABEL (buffer, "L", VALUE); \ - fprintf (FILE, CASE_VECTOR_INSNS ? "\tbr\t %s\n" : "\tword\t %s\n", \ - &buffer[1]); \ - } while (0) - -/* This is how to output an element of a case-vector that is relative. */ -#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ - ASM_OUTPUT_ADDR_VEC_ELT (FILE, VALUE) - -/* This is how to output an assembler line - that says to advance the location counter - to a multiple of 2**LOG bytes. */ -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ - if ((LOG) != 0) \ - fprintf (FILE, "%s%d\n", ALIGN_ASM_OP, 1<<(LOG)) - -/* On the m88100, align the text address to half a cache boundary when it - can only be reached by jumping. Pack code tightly when compiling - crtstuff.c. */ -#define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ - (TARGET_88100 && !flag_inhibit_size_directive ? 3 : 2) - -/* Override svr[34].h. */ -#undef ASM_OUTPUT_SKIP -#define ASM_OUTPUT_SKIP(FILE,SIZE) \ - fprintf (FILE, "%s%u\n", SKIP_ASM_OP, (int)(SIZE)) - -/* Override svr4.h. */ -#undef ASM_OUTPUT_EXTERNAL_LIBCALL - -/* This says how to output an assembler line to define a global common - symbol. Size can be zero for the unusual case of a `struct { int : 0; }'. - Override svr[34].h. */ -#undef ASM_OUTPUT_COMMON -#undef ASM_OUTPUT_ALIGNED_COMMON -#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -( fprintf ((FILE), "%s", \ - ((SIZE) ? (int)(SIZE) : 1) <= m88k_gp_threshold ? SCOMM_ASM_OP : COMMON_ASM_OP), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%u\n", (SIZE) ? (int)(SIZE) : 1)) - -/* This says how to output an assembler line to define a local common - symbol. Override svr[34].h. */ -#undef ASM_OUTPUT_LOCAL -#undef ASM_OUTPUT_ALIGNED_LOCAL -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -( fprintf ((FILE), "%s", \ - ((SIZE) ? (int)(SIZE) : 1) <= m88k_gp_threshold ? SBSS_ASM_OP : BSS_ASM_OP), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%u,%d\n", (SIZE) ? (int)(SIZE) : 1, (SIZE) <= 4 ? 4 : 8)) - -/* This is how to output an insn to push a register on the stack. - It need not be very fast code. */ -#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ - fprintf (FILE, "\tsubu\t %s,%s,%d\n\tst\t %s,%s,0\n", \ - reg_names[STACK_POINTER_REGNUM], \ - reg_names[STACK_POINTER_REGNUM], \ - (STACK_BOUNDARY / BITS_PER_UNIT), \ - reg_names[REGNO], \ - reg_names[STACK_POINTER_REGNUM]) - -/* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */ -#define REG_PUSH_LENGTH 2 - -/* This is how to output an insn to pop a register from the stack. */ -#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ - fprintf (FILE, "\tld\t %s,%s,0\n\taddu\t %s,%s,%d\n", \ - reg_names[REGNO], \ - reg_names[STACK_POINTER_REGNUM], \ - reg_names[STACK_POINTER_REGNUM], \ - reg_names[STACK_POINTER_REGNUM], \ - (STACK_BOUNDARY / BITS_PER_UNIT)) - -/* Length in instructions of the code output by ASM_OUTPUT_REG_POP. */ -#define REG_POP_LENGTH 2 - -/* Macros to deal with OCS debug information */ - -#define OCS_START_PREFIX "Ltb" -#define OCS_END_PREFIX "Lte" - -#define PUT_OCS_FUNCTION_START(FILE) \ - { (*targetm.asm_out.internal_label) (FILE, OCS_START_PREFIX, m88k_function_number); } - -#define PUT_OCS_FUNCTION_END(FILE) \ - { (*targetm.asm_out.internal_label) (FILE, OCS_END_PREFIX, m88k_function_number); } - -/* Macros for debug information */ -#define DEBUGGER_AUTO_OFFSET(X) \ - (m88k_debugger_offset (X, 0) \ - + (TARGET_OCS_FRAME_POSITION ? 0 : m88k_stack_size - m88k_fp_offset)) - -#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ - (m88k_debugger_offset (X, OFFSET) \ - + (TARGET_OCS_FRAME_POSITION ? 0 : m88k_stack_size - m88k_fp_offset)) - -/* Macros to deal with SDB debug information */ -#ifdef SDB_DEBUGGING_INFO - -/* Output structure tag names even when it causes a forward reference. */ -#define SDB_ALLOW_FORWARD_REFERENCES - -/* Print out extra debug information in the assembler file */ -#define PUT_SDB_SCL(a) \ - do { \ - register int s = (a); \ - register const char *scl; \ - switch (s) \ - { \ - case C_EFCN: scl = "end of function"; break; \ - case C_NULL: scl = "NULL storage class"; break; \ - case C_AUTO: scl = "automatic"; break; \ - case C_EXT: scl = "external"; break; \ - case C_STAT: scl = "static"; break; \ - case C_REG: scl = "register"; break; \ - case C_EXTDEF: scl = "external definition"; break; \ - case C_LABEL: scl = "label"; break; \ - case C_ULABEL: scl = "undefined label"; break; \ - case C_MOS: scl = "structure member"; break; \ - case C_ARG: scl = "argument"; break; \ - case C_STRTAG: scl = "structure tag"; break; \ - case C_MOU: scl = "union member"; break; \ - case C_UNTAG: scl = "union tag"; break; \ - case C_TPDEF: scl = "typedef"; break; \ - case C_USTATIC: scl = "uninitialized static"; break; \ - case C_ENTAG: scl = "enumeration tag"; break; \ - case C_MOE: scl = "member of enumeration"; break; \ - case C_REGPARM: scl = "register parameter"; break; \ - case C_FIELD: scl = "bit field"; break; \ - case C_BLOCK: scl = "block start/end"; break; \ - case C_FCN: scl = "function start/end"; break; \ - case C_EOS: scl = "end of structure"; break; \ - case C_FILE: scl = "filename"; break; \ - case C_LINE: scl = "line"; break; \ - case C_ALIAS: scl = "duplicated tag"; break; \ - case C_HIDDEN: scl = "hidden"; break; \ - default: scl = "unknown"; break; \ - } \ - \ - fprintf(asm_out_file, "\tscl\t %d\t\t\t\t; %s\n", s, scl); \ - } while (0) - -#define PUT_SDB_TYPE(a) \ - do { \ - register int t = (a); \ - static char buffer[100]; \ - register char *p = buffer; \ - register const char *q; \ - register int typ = t; \ - register int i; \ - \ - for (i = 0; i <= 5; i++) \ - { \ - switch ((typ >> ((i*N_TSHIFT) + N_BTSHFT)) & 03) \ - { \ - case DT_PTR: \ - strcpy (p, "ptr to "); \ - p += sizeof("ptr to"); \ - break; \ - \ - case DT_ARY: \ - strcpy (p, "array of "); \ - p += sizeof("array of"); \ - break; \ - \ - case DT_FCN: \ - strcpy (p, "func ret "); \ - p += sizeof("func ret"); \ - break; \ - } \ - } \ - \ - switch (typ & N_BTMASK) \ - { \ - case T_NULL: q = "<no type>"; break; \ - case T_CHAR: q = "char"; break; \ - case T_SHORT: q = "short"; break; \ - case T_INT: q = "int"; break; \ - case T_LONG: q = "long"; break; \ - case T_FLOAT: q = "float"; break; \ - case T_DOUBLE: q = "double"; break; \ - case T_STRUCT: q = "struct"; break; \ - case T_UNION: q = "union"; break; \ - case T_ENUM: q = "enum"; break; \ - case T_MOE: q = "enum member"; break; \ - case T_UCHAR: q = "unsigned char"; break; \ - case T_USHORT: q = "unsigned short"; break; \ - case T_UINT: q = "unsigned int"; break; \ - case T_ULONG: q = "unsigned long"; break; \ - default: q = "void"; break; \ - } \ - \ - strcpy (p, q); \ - fprintf(asm_out_file, "\ttype\t %d\t\t\t\t; %s\n", \ - t, buffer); \ - } while (0) - -#define PUT_SDB_INT_VAL(a) \ - fprintf (asm_out_file, "\tval\t %d\n", (a)) - -#define PUT_SDB_VAL(a) \ -( fprintf (asm_out_file, "\tval\t "), \ - output_addr_const (asm_out_file, (a)), \ - fputc ('\n', asm_out_file)) - -#define PUT_SDB_DEF(a) \ - do { fprintf (asm_out_file, "\tsdef\t "); \ - ASM_OUTPUT_LABELREF (asm_out_file, a); \ - fputc ('\n', asm_out_file); \ - } while (0) - -#define PUT_SDB_PLAIN_DEF(a) \ - fprintf(asm_out_file,"\tsdef\t .%s\n", a) - -/* Simply and endef now. */ -#define PUT_SDB_ENDEF \ - fputs("\tendef\n\n", asm_out_file) - -#define PUT_SDB_SIZE(a) \ - fprintf (asm_out_file, "\tsize\t %d\n", (a)) - -/* Max dimensions to store for debug information (limited by COFF). */ -#define SDB_MAX_DIM 6 - -/* New method for dim operations. */ -#define PUT_SDB_START_DIM \ - fputs("\tdim\t ", asm_out_file) - -/* How to end the DIM sequence. */ -#define PUT_SDB_LAST_DIM(a) \ - fprintf(asm_out_file, "%d\n", a) - -#define PUT_SDB_TAG(a) \ - do { \ - fprintf (asm_out_file, "\ttag\t "); \ - ASM_OUTPUT_LABELREF (asm_out_file, a); \ - fputc ('\n', asm_out_file); \ - } while( 0 ) - -#define PUT_SDB_BLOCK_OR_FUNCTION(NAME, SCL, LINE) \ - do { \ - fprintf (asm_out_file, "\n\tsdef\t %s\n\tval\t .\n", \ - NAME); \ - PUT_SDB_SCL( SCL ); \ - fprintf (asm_out_file, "\tline\t %d\n\tendef\n\n", \ - (LINE)); \ - } while (0) - -#define PUT_SDB_BLOCK_START(LINE) \ - PUT_SDB_BLOCK_OR_FUNCTION (".bb", C_BLOCK, (LINE)) - -#define PUT_SDB_BLOCK_END(LINE) \ - PUT_SDB_BLOCK_OR_FUNCTION (".eb", C_BLOCK, (LINE)) - -#define PUT_SDB_FUNCTION_START(LINE) \ - do { \ - fprintf (asm_out_file, "\tln\t 1\n"); \ - PUT_SDB_BLOCK_OR_FUNCTION (".bf", C_FCN, (LINE)); \ - } while (0) - -#define PUT_SDB_FUNCTION_END(LINE) \ - do { \ - PUT_SDB_BLOCK_OR_FUNCTION (".ef", C_FCN, (LINE)); \ - } while (0) - -#define PUT_SDB_EPILOGUE_END(NAME) \ - do { \ - text_section (); \ - fprintf (asm_out_file, "\n\tsdef\t "); \ - ASM_OUTPUT_LABELREF(asm_out_file, (NAME)); \ - fputc('\n', asm_out_file); \ - PUT_SDB_SCL( C_EFCN ); \ - fprintf (asm_out_file, "\tendef\n\n"); \ - } while (0) - -#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ - sprintf ((BUFFER), ".%dfake", (NUMBER)); - -#endif /* SDB_DEBUGGING_INFO */ - -/* Support const and tdesc sections. Generally, a const section will - be distinct from the text section whenever we do V.4-like things - and so follows DECLARE_ASM_NAME. Note that strings go in text - rather than const. Override svr[34].h. */ - -#undef EXTRA_SECTIONS - -#if defined(USING_SVR4_H) - -#define EXTRA_SECTIONS in_tdesc, in_sdata -#define INIT_SECTION_FUNCTION -#define FINI_SECTION_FUNCTION - -#else -#if defined(USING_SVR3_H) - -#define EXTRA_SECTIONS in_tdesc, in_sdata, in_init, in_fini - -#else /* luna or other not based on svr[34].h. */ - -#undef READONLY_DATA_SECTION_ASM_OP -#undef INIT_SECTION_ASM_OP -#define EXTRA_SECTIONS in_tdesc, in_sdata -#define INIT_SECTION_FUNCTION -#define FINI_SECTION_FUNCTION - -#endif /* USING_SVR3_H */ -#endif /* USING_SVR4_H */ - -#undef EXTRA_SECTION_FUNCTIONS -#define EXTRA_SECTION_FUNCTIONS \ -void \ -tdesc_section () \ -{ \ - if (in_section != in_tdesc) \ - { \ - fprintf (asm_out_file, "%s\n", TDESC_SECTION_ASM_OP); \ - in_section = in_tdesc; \ - } \ -} \ - \ -void \ -sdata_section () \ -{ \ - if (in_section != in_sdata) \ - { \ - fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \ - in_section = in_sdata; \ - } \ -} \ - \ - INIT_SECTION_FUNCTION \ - FINI_SECTION_FUNCTION - -#define TARGET_ASM_SELECT_SECTION m88k_select_section - -/* Jump tables consist of branch instructions and should be output in - the text section. When we use a table of addresses, we explicitly - change to the readonly data section. */ -#define JUMP_TABLES_IN_TEXT_SECTION 1 - -/* Print operand X (an rtx) in assembler syntax to file FILE. - CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. - For `%' followed by punctuation, CODE is the punctuation and X is null. */ -#define PRINT_OPERAND_PUNCT_VALID_P(c) \ - ((c) == '#' || (c) == '.' || (c) == '!' || (c) == '*' || (c) == ';') - -#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) - -/* Print a memory address as an operand to reference that memory location. */ -#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) - -/* This says not to strength reduce the addr calculations within loops - (otherwise it does not take advantage of m88k scaled loads and stores */ - -#define DONT_REDUCE_ADDR diff --git a/gcc/config/m88k/m88k.md b/gcc/config/m88k/m88k.md deleted file mode 100644 index edefd23db08..00000000000 --- a/gcc/config/m88k/m88k.md +++ /dev/null @@ -1,4011 +0,0 @@ -;;- Machine description for the Motorola 88000 for GNU C compiler -;; Copyright (C) 1988, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000 -;; Free Software Foundation, Inc. -;; Contributed by Michael Tiemann (tiemann@mcc.com) -;; Currently maintained by (gcc@dg-rtp.dg.com) - -;; This file is part of GNU CC. - -;; GNU CC is free software; you can redistribute it and/or modify -;; it under the terms of the GNU General Public License as published by -;; the Free Software Foundation; either version 2, or (at your option) -;; any later version. - -;; GNU CC is distributed in the hope that it will be useful, -;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;; GNU General Public License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GNU CC; see the file COPYING. If not, write to -;; the Free Software Foundation, 59 Temple Place - Suite 330, -;; Boston, MA 02111-1307, USA. - - -;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. - -;; Attribute describing the processor. This attribute must match exactly -;; with the processor_type enumeration in m88k.h. - -; Target CPU. -(define_attr "cpu" "m88100,m88110,m88000" - (const (symbol_ref "m88k_cpu"))) - -; Type of each instruction. Default is arithmetic. -; I'd like to write the list as this, but genattrtab won't accept it. -; -; "branch,jump,call, ; flow-control instructions -; load,store,loadd,loada, ; data unit instructions -; spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv, ; FPU add instructions -; spmul,dpmul,imul, ; FPU multiply instructions -; arith,bit,mov ; integer unit instructions -; marith,weird" ; multi-word instructions - -; Classification of each insn. Some insns of TYPE_BRANCH are multi-word. -(define_attr "type" - "branch,jump,call,load,store,loadd,loada,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,bit,mov,marith,weird" - (const_string "arith")) - -(define_attr "fpu" "yes,no" - (if_then_else - (eq_attr "type" "spmul,dpmul,imul,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv") - (const_string "yes") (const_string "no"))) - -; Length in # of instructions of each insn. The values are not exact, but -; are safe. -(define_attr "length" "" - (cond [(eq_attr "type" "marith,weird,branch") - (const_int 2)] - (const_int 1))) - -; Describe a user's asm statement. -(define_asm_attributes - [(set_attr "type" "weird")]) - -; Define the delay slot requirements for branches and calls. -; The m88100 annuls instructions if a conditional branch is taken. -; For insns of TYPE_BRANCH that are multi-word instructions, the -; delay slot applies to the first instruction. - -; @@ For the moment, reorg.c requires that the delay slot of a branch not -; be a call or branch. - -(define_delay (eq_attr "type" "branch,jump") - [(and - (and - (eq_attr "type" "!branch,jump,call,marith,weird") ; required. - (eq_attr "type" "!load,loadd")) ; issue as-soon-as-possible. - (eq_attr "fpu" "no")) ; issue as-soon-as-possible. - (eq_attr "type" "!call,branch,jump") (nil)]) ; @@ was (const_int 1) - -; output_call supports an unconditional branch in the delay slot of -; a call. (@@ Support for this case is expected in reorg.c soon.) - -(define_delay (eq_attr "type" "call") - [(eq_attr "type" "!branch,call,marith,weird") ; required. - (nil) (nil)]) - -; An abstract block diagram of the function units for the m88100. -; -; * -; | -; +---v----+ -; | decode | -; +-vv-v-v-+ fpu -; ,----------'| | `----------------------. -; | | | | ,-----. -; load | store | | arith | | | -; | | | +-v-v-+ | dp source -; | | | | fp1 |---' -; store | | | div +-v-v-+ -; ,------. | | | ,-----. ,-----------' `-----------. -; | | | | | | | | | -; | +--v---v--+ ,---' | | +-v-v---+ +---v---+ -; | | stage 2 | | | `---| add 2 | | mul 2 | -; | +---------+ | +--v--+ +-------+ imul +-------+ -; | | stage 1 | | | alu | | add 3 | ,--------| mul 3 | -; | +---------+ | +--v--+ +-------+ | +-------+ -; | | stage 0 | | | | add 4 | | | mul 4 | -; | +--v---v--+ | | +---v---+ | +-------+ -; | | | | | | | | mul 5 | -; | * | | | | | +---v---+ -; | | | | | +----v----+ | -; | load | | | fp add `------>| fp last |<------' fp mul -; | | | | +---v-v--^+ -; | | | | | | | -; | | | | | `--' dp dest -; | | +--v-----v--+ | -; | `--->| writeback |<--------------------' -; | +--v-----v--+ -; | | | -; `------------------' * -; -; The decode unit need not be specified. -; Consideration of writeback contention is critical to superb scheduling. -; -; (define_function_unit NAME MULTIPLICITY SIMULTANEITY -; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) - -; Describing the '100 alu is currently not useful. -;(define_function_unit "alu" 1 0 (eq_attr "type" -; "!store,marith,weird") 1 0) -;(define_function_unit "alu" 1 0 (eq_attr "type" "marith,weird") 2 0) - -(define_function_unit "alu" 1 0 - (and (eq_attr "type" "loada,arith,mov") (eq_attr "cpu" "!m88100")) 2 0) -(define_function_unit "alu" 1 0 - (and (eq_attr "type" "marith,weird") (eq_attr "cpu" "!m88100")) 4 0) - -(define_function_unit "bit" 1 0 - (and (eq_attr "type" "bit") (eq_attr "cpu" "!m88100")) 2 2) - -(define_function_unit "mem100" 1 0 - (and (eq_attr "type" "store,loada") (eq_attr "cpu" "m88100")) 1 0) -(define_function_unit "mem100" 1 0 - (and (eq_attr "type" "load") (eq_attr "cpu" "m88100")) 3 0) -(define_function_unit "mem100" 1 0 - (and (eq_attr "type" "loadd") (eq_attr "cpu" "m88100")) 3 2) - -(define_function_unit "mem110" 1 0 - (and (eq_attr "type" "load,loadd") (eq_attr "cpu" "!m88100")) 3 2) -(define_function_unit "mem110" 1 0 - (and (eq_attr "type" "store") (eq_attr "cpu" "!m88100")) 1 2) - -; The times are adjusted to include fp1 and fplast, but then are further -; adjusted based on the actual generated code. The notation to the right -; is the total latency. A range denotes a group of instructions and/or -; conditions (the extra clock of fplast time with some sequences). - -(define_function_unit "fpmul100" 1 0 - (and (eq_attr "type" "spmul") (eq_attr "cpu" "m88100")) 4 0) ; 6-8 -(define_function_unit "fpmul100" 1 0 - (and (eq_attr "type" "dpmul") (eq_attr "cpu" "m88100")) 7 0) ; 9-10 -(define_function_unit "fpmul100" 1 0 - (and (eq_attr "type" "imul") (eq_attr "cpu" "m88100")) 3 0) ; 4 - -(define_function_unit "fpmul110" 1 0 - (and (eq_attr "type" "imul,spmul,dpmul") - (eq_attr "cpu" "!m88100")) 5 2) ; 3 - -(define_function_unit "fpadd100" 1 5 - (and (eq_attr "type" "spadd,spcmp") (eq_attr "cpu" "m88100")) 3 0) ; 5-6 -(define_function_unit "fpadd100" 1 5 - (and (eq_attr "type" "dpadd,dpcmp") (eq_attr "cpu" "m88100")) 4 0) ; 6-7 - -(define_function_unit "fpadd110" 1 0 - (and (eq_attr "type" "spadd,dpadd") (eq_attr "cpu" "!m88100")) 5 2) ; 3 -(define_function_unit "fpadd110" 1 0 - (and (eq_attr "type" "spcmp,dpcmp") (eq_attr "cpu" "!m88100")) 2 2) ; 1 - -(define_function_unit "fpadd100" 1 5 - (and (eq_attr "type" "spdiv") (eq_attr "cpu" "m88100")) 30 0) ; 30-31 -(define_function_unit "fpadd100" 1 5 - (and (eq_attr "type" "dpdiv") (eq_attr "cpu" "m88100")) 60 0) ; 60-61 -(define_function_unit "fpadd100" 1 5 - (and (eq_attr "type" "idiv") (eq_attr "cpu" "m88100")) 38 0) ; 38 - -(define_function_unit "div" 1 1 - (and (eq_attr "type" "spdiv") (eq_attr "cpu" "!m88100")) 25 2) ; 13 -(define_function_unit "div" 1 1 - (and (eq_attr "type" "dpdiv") (eq_attr "cpu" "!m88100")) 45 2) ; 23 -(define_function_unit "div" 1 1 - (and (eq_attr "type" "idiv") (eq_attr "cpu" "!m88100")) 35 2) ; 18 - -;; Superoptimizer sequences - -;; geu+: { r = ((unsigned_word) v0 >= (unsigned_word) v1) + v2; } -;; subu.co r5,r2,r3 -;; addu.cio r6,r4,r0 - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (minus:SI (match_operand:SI 1 "register_operand" "r") - (geu:SI (match_operand:SI 2 "register_operand" "r") - (match_operand:SI 3 "register_operand" "r"))))] - "" - [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1)) - (set (match_dup 0) - (plus:SI (match_dup 1) - (unspec:SI [(const_int 0) - (reg:CC 0)] 0)))] - "") - -;; leu+: { r = ((unsigned_word) v0 <= (unsigned_word) v1) + v2; } -;; subu.co r5,r3,r2 -;; addu.cio r6,r4,r0 - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (minus:SI (match_operand:SI 1 "register_operand" "r") - (leu:SI (match_operand:SI 3 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r"))))] - "" - [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1)) - (set (match_dup 0) - (plus:SI (match_dup 1) - (unspec:SI [(const_int 0) - (reg:CC 0)] 0)))] - "") - -;; eq0+: { r = (v0 == 0) + v1; } -;; subu.co r4,r0,r2 -;; addu.cio r5,r3,r0 - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (minus:SI (match_operand:SI 1 "register_operand" "r") - (eq:SI (match_operand:SI 2 "register_operand" "r") - (const_int 0))))] - "" - [(set (reg:CC 0) (unspec:CC [(const_int 0) (match_dup 2)] 1)) - (set (match_dup 0) - (plus:SI (match_dup 1) - (unspec:SI [(const_int 0) - (reg:CC 0)] 0)))] - "") - -;; ltu-: { r = v2 - ((unsigned_word) v0 < (unsigned_word) v1); } -;; subu.co r5,r2,r3 -;; subu.cio r6,r4,r0 - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (ltu:SI (match_operand:SI 2 "register_operand" "r") - (match_operand:SI 3 "register_operand" "r")) - (match_operand:SI 1 "register_operand" "r")))] - "" - [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1)) - (set (match_dup 0) - (minus:SI (match_dup 1) - (unspec:SI [(const_int 0) - (reg:CC 0)] 1)))] - "") - -;; gtu-: { r = v2 - ((unsigned_word) v0 > (unsigned_word) v1); } -;; subu.co r5,r3,r2 -;; subu.cio r6,r4,r0 - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (gtu:SI (match_operand:SI 3 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r")) - (match_operand:SI 1 "register_operand" "r")))] - "" - [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1)) - (set (match_dup 0) - (minus:SI (match_dup 1) - (unspec:SI [(const_int 0) - (reg:CC 0)] 1)))] - "") - -;; ne0-: { r = v1 - (v0 != 0); } -;; subu.co r4,r0,r2 -;; subu.cio r5,r3,r0 - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (ne:SI (match_operand:SI 2 "register_operand" "r") - (const_int 0)) - (match_operand:SI 1 "register_operand" "r")))] - "" - [(set (reg:CC 0) (unspec:CC [(const_int 0) (match_dup 2)] 1)) - (set (match_dup 0) - (minus:SI (match_dup 1) - (unspec:SI [(const_int 0) - (reg:CC 0)] 1)))] - "") - -;; ges0-: { r = v1 - ((signed_word) v0 >= 0); } -;; addu.co r4,r2,r2 -;; subu.cio r5,r3,r0 - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (minus:SI (match_operand:SI 1 "register_operand" "r") - (xor:SI (lshiftrt:SI - (match_operand:SI 2 "register_operand" "r") - (const_int 31)) - (const_int 1))))] - "" - [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 2)] 0)) - (set (match_dup 0) - (minus:SI (match_dup 1) - (unspec:SI [(const_int 0) - (reg:CC 0)] 1)))] - "") - -;; This rich set of complex patterns are mostly due to Torbjorn Granlund -;; (tege@sics.se). They've changed since then, so don't complain to him -;; if they don't work right. - -;; Regarding shifts, gen_lshlsi3 generates ASHIFT. The gen functions -;; produce the necessary insns to support TARGET_*_LARGE_SHIFT, so nothing -;; special needs to be done here. - -;; Optimize possible cases of the set instruction. - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (ashift:SI (const_int -1) - (match_operand:SI 1 "register_operand" "r")))] - "" - "set %0,%#r0,%1" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (ashift:SI (const_int -1) - (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "register_operand" "r")))] - "" - "set %0,%2,%1" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (match_operand:SI 1 "register_operand" "r") - (ashift:SI (const_int -1) - (match_operand:SI 2 "register_operand" "r"))))] - "" - "set %0,%1,%2" - [(set_attr "type" "bit")]) - -;; Optimize possible cases of the mak instruction. - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "int5_operand" "")) - (match_operand:SI 3 "immediate_operand" "n")))] - "mak_mask_p (INTVAL (operands[3]) >> INTVAL (operands[2]))" - "* -{ - operands[4] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) - >> INTVAL(operands[2])))); - return \"mak %0,%1,%4<%2>\"; -}" - [(set_attr "type" "bit")]) - -;; Optimize possible cases of output_and. - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (ashift:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "int5_operand" "") - (match_operand:SI 3 "int5_operand" "")) - (match_operand:SI 4 "int5_operand" "")))] - "INTVAL (operands[2]) + INTVAL (operands[3]) + INTVAL (operands[4]) == 32" - "* -{ - operands[2] - = GEN_INT (((1 << INTVAL (operands[2])) - 1) << INTVAL (operands[4])); - return output_and (operands); -}" - [(set_attr "type" "marith")]) ; arith,bit,marith. length is 1 or 2. - -;; Improve logical operations on compare words -;; -;; We define all logical operations on CCmode values to preserve the pairwise -;; relationship of the compare bits. This allows a future branch prediction -;; pass the degree of freedom needed to change and/bb0-le into or/bb1-gt. -;; THIS IS CURRENTLY FALSE! -;; -;; Opportunities arise when conditional expressions using && and || are made -;; unconditional. When these are used to branch, the sequence is -;; cmp/cmp/extu/extu/{and,or}/bcnd-{eq0,ne0}. When these are used to create -;; a value, the sequence is cmp/cmp/extu/extu/{and,or} for 1 or 0 or -;; cmp/cmp/ext/ext/{and,or} for -1 or 0. -;; -;; When the extracted conditions are the same, the define_split patterns -;; below change extu/extu/{and,or} into {and,or}/extu. If the reversed -;; conditions match, one compare word can be complemented, resulting in -;; {and.c,or.c}/extu. These changes are done for ext/ext/{and,or} as well. -;; If the conditions don't line up, one can be rotated. To keep the pairwise -;; relationship, it may be necessary to both rotate and complement. Rotating -;; makes branching cheaper, but doesn't help (or hurt) creating a value, so -;; we don't do this for ext/ext/{and,or}. -;; -;; These changes result in the sequence extu/bcnd-{eq0,ne0} which is combined -;; into an alternate form of bb0 and bb1. - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (neg:SI - (match_operator 1 "even_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)])) - (neg:SI - (match_operator 3 "relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)])))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "" - [(set (match_dup 5) - (ior:CCEVEN (match_dup 4) - (match_dup 2))) - (set (match_dup 0) - (neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0); - if (GET_CODE (operands[1]) == GET_CODE (operands[3])) - ; /* The conditions match. */ - else if (GET_CODE (operands[1]) - == reverse_condition (GET_CODE (operands[3]))) - /* Reverse the condition by complementing the compare word. */ - operands[4] = gen_rtx_NOT (CCmode, operands[4]); - else - { - /* Make the condition pairs line up by rotating the compare word. */ - int cv1 = condition_value (operands[1]); - int cv2 = condition_value (operands[3]); - - operands[4] = gen_rtx_ROTATE (CCmode, operands[4], - GEN_INT (((cv2 & ~1) - (cv1 & ~1)) - & 0x1f)); - /* Reverse the condition if needed. */ - if ((cv1 & 1) != (cv2 & 1)) - operands[4] = gen_rtx_NOT (CCmode, operands[4]); - }") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (neg:SI - (match_operator 1 "odd_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)])) - (neg:SI - (match_operator 3 "odd_relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)])))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "" - [(set (match_dup 5) - (and:CCEVEN (match_dup 4) - (match_dup 2))) - (set (match_dup 0) - (neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0); - if (GET_CODE (operands[1]) == GET_CODE (operands[3])) - ; /* The conditions match. */ - else - { - /* Make the condition pairs line up by rotating the compare word. */ - int cv1 = condition_value (operands[1]); - int cv2 = condition_value (operands[3]); - - operands[4] = gen_rtx_ROTATE (CCmode, operands[4], - GEN_INT ((cv2 - cv1) & 0x1f)); - }") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (neg:SI - (match_operator 1 "odd_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)])) - (neg:SI - (match_operator 3 "even_relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)])))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "" - [(set (match_dup 5) - (ior:CCEVEN (not:CC (match_dup 2)) - (match_dup 4))) - (set (match_dup 0) - (neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0); - if (GET_CODE (operands[1]) - == reverse_condition (GET_CODE (operands[3]))) - ; - else - { - /* Make the condition pairs line up by rotating the compare word. */ - int cv1 = condition_value (operands[1]); - int cv2 = condition_value (operands[3]); - - operands[2] = gen_rtx_ROTATE (CCmode, operands[2], - GEN_INT (((cv1 & ~1) - (cv2 & ~1)) - & 0x1f)); - }") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (match_operator 1 "even_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)]) - (match_operator 3 "relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)]))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "GET_CODE (operands[1]) == GET_CODE (operands[3]) - || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))" - [(set (match_dup 5) - (ior:CCEVEN (match_dup 4) - (match_dup 2))) - (set (match_dup 0) - (match_op_dup 1 [(match_dup 5) (const_int 0)]))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0); - /* Reverse the condition by complementing the compare word. */ - if (GET_CODE (operands[1]) != GET_CODE (operands[3])) - operands[4] = gen_rtx_NOT (CCmode, operands[4]);") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (match_operator 1 "odd_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)]) - (match_operator 3 "odd_relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)]))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "GET_CODE (operands[1]) == GET_CODE (operands[3])" - [(set (match_dup 5) - (and:CCEVEN (match_dup 4) - (match_dup 2))) - (set (match_dup 0) - (match_op_dup 1 [(match_dup 5) (const_int 0)]))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (match_operator 1 "odd_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)]) - (match_operator 3 "even_relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)]))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))" - [(set (match_dup 5) - (ior:CCEVEN (not:CC (match_dup 4)) - (match_dup 2))) - (set (match_dup 0) - (match_op_dup 1 [(match_dup 5) (const_int 0)]))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (and:SI (neg:SI - (match_operator 1 "even_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)])) - (neg:SI - (match_operator 3 "relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)])))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "" - [(set (match_dup 5) - (and:CCEVEN (match_dup 4) - (match_dup 2))) - (set (match_dup 0) - (neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0); - if (GET_CODE (operands[1]) == GET_CODE (operands[3])) - ; /* The conditions match. */ - else if (GET_CODE (operands[1]) - == reverse_condition (GET_CODE (operands[3]))) - /* Reverse the condition by complementing the compare word. */ - operands[4] = gen_rtx_NOT (CCmode, operands[4]); - else - { - /* Make the condition pairs line up by rotating the compare word. */ - int cv1 = condition_value (operands[1]); - int cv2 = condition_value (operands[3]); - operands[4] = gen_rtx_ROTATE (CCmode, operands[4], - GEN_INT (((cv2 & ~1) - (cv1 & ~1)) - & 0x1f)); - /* Reverse the condition if needed. */ - if ((cv1 & 1) != (cv2 & 1)) - operands[4] = gen_rtx_NOT (CCmode, operands[4]); - }") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (and:SI (neg:SI - (match_operator 1 "odd_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)])) - (neg:SI - (match_operator 3 "odd_relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)])))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "" - [(set (match_dup 5) - (ior:CCEVEN (match_dup 4) - (match_dup 2))) - (set (match_dup 0) - (neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0); - if (GET_CODE (operands[1]) == GET_CODE (operands[3])) - ; /* The conditions match. */ - else - { - /* Make the condition pairs line up by rotating the compare word. */ - int cv1 = condition_value (operands[1]); - int cv2 = condition_value (operands[3]); - operands[4] = gen_rtx_ROTATE (CCmode, operands[4], - GEN_INT ((cv2 - cv1) & 0x1f)); - }") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (and:SI (neg:SI - (match_operator 1 "odd_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)])) - (neg:SI - (match_operator 3 "even_relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)])))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "" - [(set (match_dup 5) - (and:CCEVEN (not:CC (match_dup 2)) - (match_dup 4))) - (set (match_dup 0) - (neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0); - if (GET_CODE (operands[1]) - == reverse_condition (GET_CODE (operands[3]))) - ; - else - { - /* Make the condition pairs line up by rotating the compare word. */ - int cv1 = condition_value (operands[1]); - int cv2 = condition_value (operands[3]); - operands[2] = gen_rtx_ROTATE (CCmode, operands[2], - GEN_INT (((cv1 & ~1) - (cv2 & ~1)) - & 0x1f)); - }") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (and:SI (match_operator 1 "even_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)]) - (match_operator 3 "relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)]))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "GET_CODE (operands[1]) == GET_CODE (operands[3]) - || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))" - [(set (match_dup 5) - (and:CCEVEN (match_dup 4) - (match_dup 2))) - (set (match_dup 0) - (match_op_dup 1 [(match_dup 5) (const_int 0)]))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0); - /* Reverse the condition by complementing the compare word. */ - if (GET_CODE (operands[1]) != GET_CODE (operands[3])) - operands[4] = gen_rtx_NOT (CCmode, operands[4]);") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (and:SI (match_operator 1 "odd_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)]) - (match_operator 3 "odd_relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)]))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "GET_CODE (operands[1]) == GET_CODE (operands[3])" - [(set (match_dup 5) - (ior:CCEVEN (match_dup 4) - (match_dup 2))) - (set (match_dup 0) - (match_op_dup 1 [(match_dup 5) (const_int 0)]))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);") - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (and:SI (match_operator 1 "odd_relop" - [(match_operand 2 "partial_ccmode_register_operand" "%r") - (const_int 0)]) - (match_operator 3 "even_relop" - [(match_operand 4 "partial_ccmode_register_operand" "r") - (const_int 0)]))) - (clobber (match_operand:SI 5 "register_operand" "=r"))] - "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))" - [(set (match_dup 5) - (and:CCEVEN (not:CC (match_dup 2)) - (match_dup 4))) - (set (match_dup 0) - (match_op_dup 3 [(match_dup 5) (const_int 0)]))] - "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);") - - -;; Logical operations on compare words. - -(define_insn "" - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (and:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r")) - (match_operand 2 "partial_ccmode_register_operand" "r")))] - "" - "and.c %0,%2,%1") - -(define_insn "" - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (and:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r") - (match_operand 2 "partial_ccmode_register_operand" "r")))] - "" - "and %0,%1,%2") - -(define_insn "" - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (ior:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r")) - (match_operand 2 "partial_ccmode_register_operand" "r")))] - "" - "or.c %0,%2,%1") - -(define_insn "" - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (ior:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r") - (match_operand 2 "partial_ccmode_register_operand" "r")))] - "" - "or %0,%1,%2") - -(define_insn "" - [(set (match_operand:CC 0 "register_operand" "=r") - (rotate:CC (match_operand:CC 1 "register_operand" "r") - (match_operand:CC 2 "int5_operand" "")))] - "" - "rot %0,%1,%2" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (rotate:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "r") - (match_operand:CC 2 "int5_operand" "")))] - "" - "rot %0,%1,%2" - [(set_attr "type" "bit")]) - -;; rotate/and[.c] and rotate/ior[.c] - -(define_split - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") - (match_operand:CC 2 "int5_operand" "")) - (match_operand 3 "partial_ccmode_register_operand" "r"))) - (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))] - "" - [(set (match_dup 4) - (rotate:CC (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (ior:CCEVEN (match_dup 4) (match_dup 3)))] - "") - -(define_insn "" - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") - (match_operand:CC 2 "int5_operand" "")) - (match_operand 3 "partial_ccmode_register_operand" "r"))) - (clobber (match_scratch:CCEVEN 4 "=r"))] - "" - "#") - -(define_split - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") - (match_operand:CC 2 "int5_operand" ""))) - (match_operand 3 "partial_ccmode_register_operand" "r"))) - (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))] - "" - [(set (match_dup 4) - (rotate:CC (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (ior:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))] - "") - -(define_insn "" - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") - (match_operand:CC 2 "int5_operand" ""))) - (match_operand 3 "partial_ccmode_register_operand" "r"))) - (clobber (match_scratch:CCEVEN 4 "=r"))] - "" - "#") - -(define_split - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") - (match_operand:CC 2 "int5_operand" "")) - (match_operand 3 "partial_ccmode_register_operand" "r"))) - (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))] - "" - [(set (match_dup 4) - (rotate:CC (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (and:CCEVEN (match_dup 4) (match_dup 3)))] - "") - -(define_insn "" - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") - (match_operand:CC 2 "int5_operand" "")) - (match_operand 3 "partial_ccmode_register_operand" "r"))) - (clobber (match_scratch:CCEVEN 4 "=r"))] - "" - "#") - -(define_split - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") - (match_operand:CC 2 "int5_operand" ""))) - (match_operand 3 "partial_ccmode_register_operand" "r"))) - (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))] - "" - [(set (match_dup 4) - (rotate:CC (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (and:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))] - "") - -(define_insn "" - [(set (match_operand:CCEVEN 0 "register_operand" "=r") - (and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") - (match_operand:CC 2 "int5_operand" ""))) - (match_operand 3 "partial_ccmode_register_operand" "r"))) - (clobber (match_scratch:CCEVEN 4 "=r"))] - "" - "#") - - -;; Recognize bcnd instructions for integer values. This is distinguished -;; from a conditional branch instruction (below) with SImode instead of -;; CCmode. - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 0 "relop_no_unsigned" - [(match_operand:SI 1 "register_operand" "r") - (const_int 0)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bcnd%. %R3%B0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -;; Recognize tests for sign and zero. - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 0 "equality_op" - [(match_operand:SI 1 "register_operand" "r") - (const_int -2147483648)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bcnd%. %R3%E0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 0 "equality_op" - [(zero_extract:SI - (match_operand:SI 1 "register_operand" "r") - (const_int 31) - (const_int 1)) - (const_int 0)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bcnd%. %R3%D0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -;; Recognize bcnd instructions for double integer values - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 0 "relop_no_unsigned" - [(sign_extend:DI - (match_operand:SI 1 "register_operand" "r")) - (const_int 0)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bcnd%. %R3%B0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 0 "equality_op" - [(zero_extend:DI - (match_operand:SI 1 "register_operand" "r")) - (const_int 0)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bcnd%. %R3%B0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -; @@ I doubt this is interesting until cmpdi is provided. Anyway, it needs -; to be reworked. -; -;(define_insn "" -; [(set (pc) -; (if_then_else -; (match_operator 0 "relop_no_unsigned" -; [(match_operand:DI 1 "register_operand" "r") -; (const_int 0)]) -; (match_operand 2 "pc_or_label_ref" "") -; (match_operand 3 "pc_or_label_ref" "")))] -; "" -; "* -;{ -; switch (GET_CODE (operands[0])) -; { -; case EQ: -; case NE: -; /* I'm not sure if it's safe to use .n here. */ -; return \"or %!,%1,%d1\;bcnd %R3%B0,%!,%P2%P3\"; -; case GE: -; case LT: -; return \"bcnd%. %R3%B0,%1,%P2%P3\"; -; case GT: -; { -; rtx op2 = operands[2]; -; operands[2] = operands[3]; -; operands[3] = op2; -; } -; case LE: -; if (GET_CODE (operands[3]) == LABEL_REF) -; { -; int label_num; -; operands[2] = gen_label_rtx (); -; label_num = XINT (operands[2], 3); -; output_asm_insn -; (\"bcnd%. %#lt0,%1,%2\;or %!,%1,%d1\;bcnd %#ne0,%!,%3\", operands); -; output_label (label_num); -; return \"\"; -; } -; else -; return \"bcnd%. %#lt0,%1,%2\;or %!,%1,%d1\;bcnd %#eq0,%!,%2\"; -; } -;}") - -;; Recognize bcnd instructions for single precision float values -;; Exclude relational operations as they must signal NaNs. - -;; @@ These bcnd insns for float and double values don't seem to be recognized. - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 0 "equality_op" - [(float_extend:DF - (match_operand:SF 1 "register_operand" "r")) - (const_int 0)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bcnd%. %R3%D0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 0 "equality_op" - [(match_operand:SF 1 "register_operand" "r") - (const_int 0)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bcnd%. %R3%D0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -;; Recognize bcnd instructions for double precision float values -;; Exclude relational operations as they must signal NaNs. - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 0 "equality_op" - [(match_operand:DF 1 "register_operand" "r") - (const_int 0)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "* -{ - int label_num; - - if (GET_CODE (operands[0]) == NE) - { - rtx op2 = operands[2]; - operands[2] = operands[3]; - operands[3] = op2; - } - if (GET_CODE (operands[3]) == LABEL_REF) - return \"bcnd 0x5,%1,%3\;bcnd %#ne0,%d1,%3\"; - - operands[3] = gen_label_rtx (); - label_num = XINT (operands[3], 3); - output_asm_insn (\"bcnd 0x5,%1,%3\;bcnd %#eq0,%d1,%2\", operands); - output_label (label_num); - return \"\"; -}" - [(set_attr "type" "weird") - (set_attr "length" "3")]) - -;; Recognize bb0 and bb1 instructions. These use two unusual template -;; patterns, %Lx and %Px. %Lx outputs a 1 if operand `x' is a LABEL_REF -;; otherwise it outputs a 0. It then may print ".n" if the delay slot -;; is used. %Px does noting if `x' is PC and outputs the operand if `x' -;; is a LABEL_REF. - -(define_insn "" - [(set (pc) - (if_then_else - (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r") - (const_int 1) - (match_operand:SI 1 "int5_operand" "")) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L2 (31-%1),%0,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r") - (const_int 1) - (match_operand:SI 1 "int5_operand" "")) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L3 (31-%1),%0,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r") - (const_int 1) - (match_operand:SI 1 "int5_operand" "")) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L2 (31-%1),%0,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r") - (const_int 1) - (match_operand:SI 1 "int5_operand" "")) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L3 (31-%1),%0,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (eq (and:SI (match_operand:SI 0 "reg_or_bbx_mask_operand" "%r") - (match_operand:SI 1 "reg_or_bbx_mask_operand" "n")) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "(GET_CODE (operands[0]) == CONST_INT) - != (GET_CODE (operands[1]) == CONST_INT)" - "bb%L3 %p1,%0,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (ne (and:SI (match_operand:SI 0 "reg_or_bbx_mask_operand" "%r") - (match_operand:SI 1 "reg_or_bbx_mask_operand" "n")) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "(GET_CODE (operands[0]) == CONST_INT) - != (GET_CODE (operands[1]) == CONST_INT)" - "bb%L2 %p1,%0,%P2%P3" - [(set_attr "type" "branch")]) - -;; The comparison operations store the comparison into a register and -;; record that register. The following Bxx or Sxx insn uses that -;; register as an input. To facilitate use of bcnd instead of cmp/bb1, -;; cmpsi records its operands and produces no code when any operand -;; is constant. In this case, the Bxx insns use gen_bcnd and the -;; Sxx insns use gen_test to ensure a cmp has been emitted. -;; -;; This could also be done for SFmode and DFmode having only beq and bne -;; use gen_bcnd. The others must signal NaNs. It seems though that zero -;; has already been copied into a register. -;; -;; cmpsi/beq and cmpsi/bne can always be done with bcnd if any operand -;; is a constant. (This idea is due to Torbjorn Granlund.) Others can -;; use bcnd only if an operand is zero. -;; -;; It is necessary to distinguish a register holding condition codes. -;; This is done by context. - -(define_expand "test" - [(set (match_dup 2) - (compare:CC (match_operand 0 "" "") - (match_operand 1 "" "")))] - "" - " -{ - if (m88k_compare_reg) - abort (); - - if (GET_CODE (operands[0]) == CONST_INT - && ! SMALL_INT (operands[0])) - operands[0] = force_reg (SImode, operands[0]); - - if (GET_CODE (operands[1]) == CONST_INT - && ! SMALL_INT (operands[1])) - operands[1] = force_reg (SImode, operands[1]); - - operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode); -}") - -; @@ The docs say don't do this. It's probably a nop since the insn looks -; identical to cmpsi against zero. Is there an advantage to providing -; this, perhaps with a different form? - -;(define_expand "tstsi" -; [(set (match_dup 1) -; (compare:CC (match_operand:SI 0 "register_operand" "") -; (const_int 0)))] -; "" -; " -;{ -; m88k_compare_reg = 0; -; m88k_compare_op0 = operands[0]; -; m88k_compare_op1 = const0_rtx; -; DONE; -;}") - -(define_expand "cmpsi" - [(set (match_dup 2) - (compare:CC (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "arith32_operand" "")))] - "" - " -{ - if (GET_CODE (operands[0]) == CONST_INT - || GET_CODE (operands[1]) == CONST_INT) - { - m88k_compare_reg = 0; - m88k_compare_op0 = operands[0]; - m88k_compare_op1 = operands[1]; - DONE; - } - operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode); -}") - -(define_expand "cmpsf" - [(set (match_dup 2) - (compare:CC (match_operand:SF 0 "register_operand" "") - (match_operand:SF 1 "register_operand" "")))] - "" - "operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);") - -(define_expand "cmpdf" - [(set (match_dup 2) - (compare:CC (match_operand:DF 0 "general_operand" "") - (match_operand:DF 1 "general_operand" "")))] - "" - " -{ - operands[0] = legitimize_operand (operands[0], DFmode); - operands[1] = legitimize_operand (operands[1], DFmode); - operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode); -}") - -; @@ Get back to this later on. -; -;(define_insn "cmpdi" -; [(set (cc0) -; (compare:CC (match_operand:DI 0 "register_operand" "r") -; (match_operand:DI 1 "register_operand" "r")))] -; "" -; "* -;{ -; if ((cc_status.mdep & MDEP_LS_CHANGE) != 0) -; abort (); /* output_move_double MDEP_LS_CHANGE bits were set. */ -; -; cc_status.mdep &= ~ MDEP_LS_MASK; -; -; operands[2] = gen_label_rtx (); -; /* Remember, %! is the condition code register and %@ is the -; literal synthesis register. */ -; -; output_asm_insn (\"cmp %!,%0,%1\;bb0 %#eq,%!,%l2\;cmp %!,%d0,%d1\", -; operands); -; -; output_asm_insn (\"extu %@,%!,4<8>\;clr %!,%!,4<4>\", operands); -; output_asm_insn (\"mak %@,%@,4<4>\;or %!,%!,%@\", operands); -; output_label (XINT (operands[2], 3)); -; return \"\"; -;}" - -;; The actual compare instructions. - -(define_insn "" - [(set (match_operand:CC 0 "register_operand" "=r") - (compare:CC (match_operand:SI 1 "register_operand" "rO") - (match_operand:SI 2 "arith_operand" "rI")))] - "" - "cmp %0,%r1,%2") - -(define_insn "" - [(set (match_operand:CC 0 "register_operand" "=r,r,r,r") - (compare:CC (match_operand:SF 1 "register_operand" "r,r,x,x") - (match_operand:SF 2 "real_or_0_operand" "r,G,x,G")))] - "" - "@ - fcmp.sss %0,%1,%2 - fcmp.sss %0,%1,%#r0 - fcmp.sss %0,%1,%2 - fcmp.sss %0,%1,%#x0" - [(set_attr "type" "spcmp")]) - -(define_insn "" - [(set (match_operand:CC 0 "register_operand" "=r,r") - (compare:CC (match_operand:DF 1 "register_operand" "r,x") - (float_extend:DF - (match_operand:SF 2 "register_operand" "r,x"))))] - "" - "fcmp.sds %0,%1,%2" - [(set_attr "type" "dpcmp")]) - -(define_insn "" - [(set (match_operand:CC 0 "register_operand" "=r,r") - (compare:CC (float_extend:DF - (match_operand:SF 1 "register_operand" "r,x")) - (match_operand:DF 2 "register_operand" "r,x")))] - "" - "fcmp.ssd %0,%1,%2" - [(set_attr "type" "dpcmp")]) - -(define_insn "" - [(set (match_operand:CC 0 "register_operand" "=r,r,r,r") - (compare:CC (match_operand:DF 1 "register_operand" "r,r,x,x") - (match_operand:DF 2 "real_or_0_operand" "r,G,x,G")))] - "" - "@ - fcmp.sdd %0,%1,%2 - fcmp.sds %0,%1,%#r0 - fcmp.sdd %0,%1,%2 - fcmp.sds %0,%1,%#x0" - [(set_attr "type" "dpcmp")]) - -;; Store condition code insns. The compare insns set a register -;; rather than cc0 and record that register for use here. See above -;; for the special treatment of cmpsi with a constant operand. - -;; @@ For the m88110, use fcmpu for bxx sxx inequality comparisons. - -(define_expand "seq" - [(set (match_operand:SI 0 "register_operand" "") - (match_dup 1))] - "" - "operands[1] = emit_test (EQ, SImode);") - -(define_expand "sne" - [(set (match_operand:SI 0 "register_operand" "") - (match_dup 1))] - "" - "operands[1] = emit_test (NE, SImode);") - -(define_expand "sgt" - [(set (match_operand:SI 0 "register_operand" "") - (match_dup 1))] - "" - "operands[1] = emit_test (GT, SImode);") - -(define_expand "sgtu" - [(set (match_operand:SI 0 "register_operand" "") - (match_dup 1))] - "" - "operands[1] = emit_test (GTU, SImode);") - -(define_expand "slt" - [(set (match_operand:SI 0 "register_operand" "") - (match_dup 1))] - "" - "operands[1] = emit_test (LT, SImode);") - -(define_expand "sltu" - [(set (match_operand:SI 0 "register_operand" "") - (match_dup 1))] - "" - "operands[1] = emit_test (LTU, SImode);") - -(define_expand "sge" - [(set (match_operand:SI 0 "register_operand" "") - (match_dup 1))] - "" - "operands[1] = emit_test (GE, SImode);") - -(define_expand "sgeu" - [(set (match_operand:SI 0 "register_operand" "") - (match_dup 1))] - "" - "operands[1] = emit_test (GEU, SImode);") - -(define_expand "sle" - [(set (match_operand:SI 0 "register_operand" "") - (match_dup 1))] - "" - "operands[1] = emit_test (LE, SImode);") - -(define_expand "sleu" - [(set (match_operand:SI 0 "register_operand" "") - (match_dup 1))] - "" - "operands[1] = emit_test (LEU, SImode);") - -;; The actual set condition code instruction. - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operator:SI 1 "relop" - [(match_operand:CC 2 "register_operand" "r") - (const_int 0)]))] - "" - "ext %0,%2,1<%C1>" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operator:SI 1 "even_relop" - [(match_operand:CCEVEN 2 "register_operand" "r") - (const_int 0)]))] - "" - "ext %0,%2,1<%C1>" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (not:SI (match_operator:SI 1 "odd_relop" - [(match_operand:CCEVEN 2 "register_operand" "r") - (const_int 0)])))] - "" - "ext %0,%2,1<%!%C1>" - [(set_attr "type" "bit")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operator:SI 1 "odd_relop" - [(match_operand:CCEVEN 2 "register_operand" "r") - (const_int 0)])) - (clobber (match_operand:SI 3 "register_operand" "=r"))] - "" - [(set (match_dup 3) (not:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]))) - (set (match_dup 0) (not:SI (match_dup 3)))] - "") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operator:SI 1 "odd_relop" - [(match_operand:CCEVEN 2 "register_operand" "r") - (const_int 0)])) - (clobber (match_scratch:SI 3 "=r"))] - "" - "#") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (neg:SI - (match_operator:SI 1 "relop" - [(match_operand:CC 2 "register_operand" "r") - (const_int 0)])))] - "" - "extu %0,%2,1<%C1>" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (neg:SI - (match_operator:SI 1 "even_relop" - [(match_operand:CCEVEN 2 "register_operand" "r") - (const_int 0)])))] - "" - "extu %0,%2,1<%C1>" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (neg:SI - (not:SI (match_operator:SI 1 "odd_relop" - [(match_operand:CCEVEN 2 "register_operand" "r") - (const_int 0)]))))] - "" - "extu %0,%2,1<%!%C1>" - [(set_attr "type" "bit")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "=r") - (neg:SI (match_operator:SI 1 "odd_relop" - [(match_operand:CCEVEN 2 "register_operand" "r") - (const_int 0)]))) - (clobber (match_operand:SI 3 "register_operand" "=r"))] - "" - [(set (match_dup 3) (neg:SI (not:SI (match_op_dup 1 [(match_dup 2) - (const_int 0)])))) - (set (match_dup 0) (xor:SI (match_dup 3) (const_int 1)))] - "") - -(define_insn - "" - [(set (match_operand:SI 0 "register_operand" "=r") - (neg:SI (match_operator:SI 1 "odd_relop" - [(match_operand:CCEVEN 2 "register_operand" "r") - (const_int 0)]))) - (clobber (match_scratch:SI 3 "=r"))] - "" - "#") - - - - -;; Conditional branch insns. The compare insns set a register -;; rather than cc0 and record that register for use here. See above -;; for the special case of cmpsi with a constant operand. - -(define_expand "bcnd" - [(set (pc) - (if_then_else (match_operand 0 "" "") - (label_ref (match_operand 1 "" "")) - (pc)))] - "" - "if (m88k_compare_reg) abort ();") - -(define_expand "bxx" - [(set (pc) - (if_then_else (match_operand 0 "" "") - (label_ref (match_operand 1 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) abort ();") - -(define_expand "beq" - [(set (pc) - (if_then_else (eq (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) - { - emit_bcnd (EQ, operands[0]); - DONE; - } - operands[1] = m88k_compare_reg;") - -(define_expand "bne" - [(set (pc) - (if_then_else (ne (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) - { - emit_bcnd (NE, operands[0]); - DONE; - } - operands[1] = m88k_compare_reg;") - -(define_expand "bgt" - [(set (pc) - (if_then_else (gt (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) - { - emit_bcnd (GT, operands[0]); - DONE; - } - operands[1] = m88k_compare_reg;") - -(define_expand "bgtu" - [(set (pc) - (if_then_else (gtu (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) - { - emit_jump_insn (gen_bxx (emit_test (GTU, VOIDmode), operands[0])); - DONE; - } - operands[1] = m88k_compare_reg;") - -(define_expand "blt" - [(set (pc) - (if_then_else (lt (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) - { - emit_bcnd (LT, operands[0]); - DONE; - } - operands[1] = m88k_compare_reg;") - -(define_expand "bltu" - [(set (pc) - (if_then_else (ltu (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) - { - emit_jump_insn (gen_bxx (emit_test (LTU, VOIDmode), operands[0])); - DONE; - } - operands[1] = m88k_compare_reg;") - -(define_expand "bge" - [(set (pc) - (if_then_else (ge (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) - { - emit_bcnd (GE, operands[0]); - DONE; - } - operands[1] = m88k_compare_reg;") - -(define_expand "bgeu" - [(set (pc) - (if_then_else (geu (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) - { - emit_jump_insn (gen_bxx (emit_test (GEU, VOIDmode), operands[0])); - DONE; - } - operands[1] = m88k_compare_reg;") - -(define_expand "ble" - [(set (pc) - (if_then_else (le (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) - { - emit_bcnd (LE, operands[0]); - DONE; - } - operands[1] = m88k_compare_reg;") - -(define_expand "bleu" - [(set (pc) - (if_then_else (leu (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "if (m88k_compare_reg == 0) - { - emit_jump_insn (gen_bxx (emit_test (LEU, VOIDmode), operands[0])); - DONE; - } - operands[1] = m88k_compare_reg;") - -;; The actual conditional branch instruction (both directions). This -;; uses two unusual template patterns, %Rx and %Px. %Rx is a prefix code -;; for the immediately following condition and reverses the condition iff -;; operand `x' is a LABEL_REF. %Px does nothing if `x' is PC and outputs -;; the operand if `x' is a LABEL_REF. - -(define_insn "" - [(set (pc) (if_then_else - (match_operator 0 "relop" - [(match_operand:CC 1 "register_operand" "r") - (const_int 0)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "* -{ - if (mostly_false_jump (insn, operands[0])) - return \"bb0%. %R2%C0,%1,%P2%P3\"; - else - return \"bb1%. %R3%C0,%1,%P2%P3\"; -}" - [(set_attr "type" "branch")]) - -;; -;; Here branch prediction is sacrificed. To get it back, you need -;; - CCODD (CC mode where the ODD bits are valid) -;; - several define_split that can apply De Morgan's Law. -;; - transformations between CCEVEN and CCODD modes. -;; - -(define_insn "" - [(set (pc) (if_then_else - (match_operator 0 "even_relop" - [(match_operand:CCEVEN 1 "register_operand" "r") - (const_int 0)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L2%. %C0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) (if_then_else - (match_operator 0 "odd_relop" - [(match_operand:CCEVEN 1 "register_operand" "r") - (const_int 0)]) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L3%. %!%C0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -;; Branch conditional on scc values. These arise from manipulations on -;; compare words above. -;; Are these really used ? - -(define_insn "" - [(set (pc) - (if_then_else - (ne (match_operator 0 "relop" - [(match_operand:CC 1 "register_operand" "r") - (const_int 0)]) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L2 %C0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (ne (match_operator 0 "even_relop" - [(match_operand:CCEVEN 1 "register_operand" "r") - (const_int 0)]) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L2 %C0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (ne (match_operator 0 "odd_relop" - [(match_operand:CCEVEN 1 "register_operand" "r") - (const_int 0)]) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L3 %!%C0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (eq (match_operator 0 "relop" - [(match_operand:CC 1 "register_operand" "r") - (const_int 0)]) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L3 %C0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (eq (match_operator 0 "even_relop" - [(match_operand:CCEVEN 1 "register_operand" "r") - (const_int 0)]) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L3 %C0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else - (eq (match_operator 0 "odd_relop" - [(match_operand:CCEVEN 1 "register_operand" "r") - (const_int 0)]) - (const_int 0)) - (match_operand 2 "pc_or_label_ref" "") - (match_operand 3 "pc_or_label_ref" "")))] - "" - "bb%L2 %!%C0,%1,%P2%P3" - [(set_attr "type" "branch")]) - -(define_insn "locate1" - [(set (match_operand:SI 0 "register_operand" "=r") - (high:SI (unspec:SI [(label_ref (match_operand 1 "" ""))] 0)))] - "" - "or.u %0,%#r0,%#hi16(%1#abdiff)") - -(define_insn "locate2" - [(parallel [(set (reg:SI 1) (pc)) - (set (match_operand:SI 0 "register_operand" "=r") - (lo_sum:SI (match_dup 0) - (unspec:SI - [(label_ref (match_operand 1 "" ""))] 0)))])] - "" - "bsr.n %1\;or %0,%0,%#lo16(%1#abdiff)\\n%1:" - [(set_attr "length" "2")]) - -;; SImode move instructions - -(define_expand "movsi" - [(set (match_operand:SI 0 "general_operand" "") - (match_operand:SI 1 "general_operand" ""))] - "" - " -{ - if (emit_move_sequence (operands, SImode, 0)) - DONE; -}") - -(define_expand "reload_insi" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:SI 1 "general_operand" "")) - (clobber (match_operand:SI 2 "register_operand" "=&r"))] - "" - " -{ - if (emit_move_sequence (operands, SImode, operands[2])) - DONE; - - /* We don't want the clobber emitted, so handle this ourselves. */ - emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); - DONE; -}") - -(define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,x,x,x,m") - (match_operand:SI 1 "move_operand" "rI,m,rO,J,M,x,r,x,m,x"))] - "(register_operand (operands[0], SImode) - || register_operand (operands[1], SImode) - || operands[1] == const0_rtx)" - "@ - or %0,%#r0,%1 - %V1ld\\t %0,%1 - %v0st\\t %r1,%0 - subu %0,%#r0,%n1 - set %0,%#r0,%s1 - mov.s %0,%1 - mov.s %0,%1 - mov %0,%1 - %V1ld\\t %0,%1 - %v0st\\t %1,%0" - [(set_attr "type" "arith,load,store,arith,bit,mov,mov,mov,load,store")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") - (match_operand:SI 1 "arith32_operand" "rI,J,L,M,n"))] - "" - "@ - or %0,%#r0,%1 - subu %0,%#r0,%n1 - or.u %0,%#r0,%X1 - set %0,%#r0,%s1 - or.u %0,%#r0,%X1\;or %0,%0,%x1" - [(set_attr "type" "arith,arith,arith,bit,marith")]) - -;; @@ Why the constraint "in"? Doesn't `i' include `n'? -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (lo_sum:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "immediate_operand" "in")))] - "" - "or %0,%1,%#lo16(%g2)") - -;; For PIC, symbol_refs are put inside unspec so that the optimizer won't -;; confuse them with real addresses. -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (lo_sum:SI (match_operand:SI 1 "register_operand" "r") - (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))] - "" - "or %0,%1,%#lo16(%g2)" - ;; Need to set length for this arith insn because operand2 - ;; is not an "arith_operand". - [(set_attr "length" "1")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (high:SI (match_operand 1 "" "")))] - "" - "or.u %0,%#r0,%#hi16(%g1)") - -;; For PIC, symbol_refs are put inside unspec so that the optimizer won't -;; confuse them with real addresses. -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))] - "" - "or.u %0,%#r0,%#hi16(%g1)" - ;; Need to set length for this arith insn because operand2 - ;; is not an arith_operand. - [(set_attr "length" "1")]) - -;; HImode move instructions - -(define_expand "movhi" - [(set (match_operand:HI 0 "general_operand" "") - (match_operand:HI 1 "general_operand" ""))] - "" - " -{ - if (emit_move_sequence (operands, HImode, 0)) - DONE; -}") - -(define_insn "" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") - (match_operand:HI 1 "move_operand" "rP,m,rO,N"))] - "(register_operand (operands[0], HImode) - || register_operand (operands[1], HImode) - || operands[1] == const0_rtx)" - "@ - or %0,%#r0,%h1 - %V1ld.hu\\t %0,%1 - %v0st.h\\t %r1,%0 - subu %0,%#r0,%H1" - [(set_attr "type" "arith,load,store,arith")]) - -(define_insn "" - [(set (match_operand:HI 0 "register_operand" "=r") - (subreg:HI (lo_sum:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "immediate_operand" "in")) 0))] - "!flag_pic" - "or %0,%1,%#lo16(%2)") - -;; QImode move instructions - -(define_expand "movqi" - [(set (match_operand:QI 0 "general_operand" "") - (match_operand:QI 1 "general_operand" ""))] - "" - " -{ - if (emit_move_sequence (operands, QImode, 0)) - DONE; -}") - -(define_insn "" - [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r") - (match_operand:QI 1 "move_operand" "rP,m,rO,N"))] - "(register_operand (operands[0], QImode) - || register_operand (operands[1], QImode) - || operands[1] == const0_rtx)" - "@ - or %0,%#r0,%q1 - %V1ld.bu\\t %0,%1 - %v0st.b\\t %r1,%0 - subu %r0,%#r0,%Q1" - [(set_attr "type" "arith,load,store,arith")]) - -(define_insn "" - [(set (match_operand:QI 0 "register_operand" "=r") - (subreg:QI (lo_sum:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "immediate_operand" "in")) 0))] - "!flag_pic" - "or %0,%1,%#lo16(%2)") - -;; DImode move instructions - -(define_expand "movdi" - [(set (match_operand:DI 0 "general_operand" "") - (match_operand:DI 1 "general_operand" ""))] - "" - " -{ - if (emit_move_sequence (operands, DImode, 0)) - DONE; -}") - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r,x") - (const_int 0))] - "" - "@ - or %0,%#r0,0\;or %d0,%#r0,0 - mov %0,%#x0" - [(set_attr "type" "marith,mov")]) - -(define_insn "" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,x,x,x,m") - (match_operand:DI 1 "nonimmediate_operand" "r,m,r,x,r,x,m,x"))] - "" - "@ - or %0,%#r0,%1\;or %d0,%#r0,%d1 - %V1ld.d\\t %0,%1 - %v0st.d\\t %1,%0 - mov.d %0,%1 - mov.d %0,%1 - mov %0,%1 - %V1ld.d\\t %0,%1 - %v0st.d\\t %1,%0" - [(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (subreg:DI (lo_sum:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "immediate_operand" "in")) 0))] - "!flag_pic" - "or %0,%1,%#lo16(%2)") - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (match_operand:DI 1 "immediate_operand" "n"))] - "" - "* return output_load_const_dimode (operands);" - [(set_attr "type" "marith") - (set_attr "length" "4")]) ; length is 2, 3 or 4. - -;; DFmode move instructions - -(define_expand "movdf" - [(set (match_operand:DF 0 "general_operand" "") - (match_operand:DF 1 "general_operand" ""))] - "" - " -{ - if (emit_move_sequence (operands, DFmode, 0)) - DONE; -}") - -(define_split - [(set (match_operand:DF 0 "register_operand" "=r") - (match_operand:DF 1 "register_operand" "r"))] - "reload_completed - && GET_CODE (operands[0]) == REG && !XRF_REGNO_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && !XRF_REGNO_P (REGNO (operands[1]))" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (match_dup 5))] - " -{ operands[2] = operand_subword (operands[0], 0, 0, DFmode); - operands[3] = operand_subword (operands[1], 0, 0, DFmode); - operands[4] = operand_subword (operands[0], 1, 0, DFmode); - operands[5] = operand_subword (operands[1], 1, 0, DFmode); }") - -;; @@ This pattern is incomplete and doesn't appear necessary. -;; -;; This pattern forces (set (reg:DF ...) (const_double ...)) -;; to be reloaded by putting the constant into memory. -;; It must come before the more general movdf pattern. - -;(define_insn "" -; [(set (match_operand:DF 0 "general_operand" "=r,o") -; (match_operand:DF 1 "" "G,G"))] -; "GET_CODE (operands[1]) == CONST_DOUBLE" -; "* -;{ -; switch (which_alternative) -; { -; case 0: -; return \"or %0,%#r0,0\;or %d0,%#r0,0\"; -; case 1: -; operands[1] = adjust_address (operands[0], SImode, 4); -; return \"%v0st\\t %#r0,%0\;st %#r0,%1\"; -; } -;}") - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (const_int 0))] - "" - "@ - or %0,%#r0,0\;or %d0,%#r0,0 - mov %0,%#x0" - [(set_attr "type" "marith,mov")]) - -(define_insn "" - [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m") - (match_operand:DF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))] - "" - "@ - or %0,%#r0,%1\;or %d0,%#r0,%d1 - %V1ld.d\\t %0,%1 - %v0st.d\\t %1,%0 - mov.d %0,%1 - mov.d %0,%1 - mov %0,%1 - %V1ld.d\\t %0,%1 - %v0st.d\\t %1,%0" - [(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r") - (subreg:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "immediate_operand" "in")) 0))] - "!flag_pic" - "or %0,%1,%#lo16(%2)") - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r") - (match_operand:DF 1 "immediate_operand" "F"))] - "" - "* return output_load_const_double (operands);" - [(set_attr "type" "marith") - (set_attr "length" "4")]) ; length is 2, 3, or 4. - -;; SFmode move instructions - -(define_expand "movsf" - [(set (match_operand:SF 0 "general_operand" "") - (match_operand:SF 1 "general_operand" ""))] - "" - " -{ - if (emit_move_sequence (operands, SFmode, 0)) - DONE; -}") - -;; @@ What happens to fconst0_rtx? -(define_insn "" - [(set (match_operand:SF 0 "register_operand" "=r,x") - (const_int 0))] - "" - "@ - or %0,%#r0,0 - mov %0,%#x0" - [(set_attr "type" "arith,mov")]) - -(define_insn "" - [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m") - (match_operand:SF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))] - "" - "@ - or %0,%#r0,%1 - %V1ld\\t %0,%1 - %v0st\\t %r1,%0 - mov.s %0,%1 - mov.s %0,%1 - mov %0,%1 - %V1ld\\t %0,%1 - %v0st\\t %r1,%0" - [(set_attr "type" "arith,load,store,mov,mov,mov,load,store")]) - -(define_insn "" - [(set (match_operand:SF 0 "register_operand" "=r") - (subreg:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "immediate_operand" "in")) 0))] - "!flag_pic" - "or %0,%1,%#lo16(%2)") - -(define_insn "" - [(set (match_operand:SF 0 "register_operand" "=r") - (match_operand:SF 1 "immediate_operand" "F"))] - "operands[1] != const0_rtx" - "* return output_load_const_float (operands);" - [(set_attr "type" "marith")]) ; length is 1 or 2. - -;; String/block move insn. See m88k.c for details. - -(define_expand "movstrsi" - [(parallel [(set (mem:BLK (match_operand:BLK 0 "" "")) - (mem:BLK (match_operand:BLK 1 "" ""))) - (use (match_operand:SI 2 "arith32_operand" "")) - (use (match_operand:SI 3 "immediate_operand" ""))])] - "" - " -{ - rtx dest_mem = operands[0]; - rtx src_mem = operands[1]; - operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); - operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); - expand_block_move (dest_mem, src_mem, operands); - DONE; -}") - -;; ??? We shouldn't be allowing such mode mismatches -(define_insn "" - [(set (match_operand 0 "register_operand" "=r") - (match_operand:BLK 1 "memory_operand" "m"))] - "" - "* -{ - switch (GET_MODE (operands[0])) - { - case QImode: - return \"%V1ld.bu\\t %0,%1\"; - case HImode: - return \"%V1ld.hu\\t %0,%1\"; - case SImode: - return \"%V1ld\\t %0,%1\"; - case DImode: - return \"%V1ld.d\\t %0,%1\"; - default: - abort (); - } -}" - [(set_attr "type" "load")]) - -(define_insn "" - [(set (match_operand:BLK 0 "memory_operand" "=m") - (match_operand 1 "register_operand" "r"))] - "" - "* -{ - switch (GET_MODE (operands[1])) - { - case QImode: - return \"%v0st.b\\t %1,%0\"; - case HImode: - return \"%v0st.h\\t %1,%0\"; - case SImode: - return \"%v0st\\t %1,%0\"; - case DImode: - return \"%v0st.d\\t %1,%0\"; - default: - abort (); - } -}" - [(set_attr "type" "store")]) - -;; Call a non-looping block move library function (e.g. __movstrSI96x64). -;; operand 0 is the function name -;; operand 1 is the destination pointer -;; operand 2 is the source pointer -;; operand 3 is the offset for the source and destination pointers -;; operand 4 is the first value to be loaded -;; operand 5 is the register to hold the value (r4 or r5) - -(define_expand "call_block_move" - [(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" ""))) - (set (match_operand 5 "register_operand" "") - (match_operand 4 "memory_operand" "")) - (set (reg:SI 2) (minus:SI (match_operand:SI 1 "register_operand" "") - (match_dup 3))) - (use (reg:SI 2)) - (use (reg:SI 3)) - (use (match_dup 5)) - (parallel [(set (reg:DI 2) - (call (mem:SI (match_operand 0 "" "")) - (const_int 0))) - (clobber (reg:SI 1))])] - "" - "") - -;; Call an SImode looping block move library function (e.g. __movstrSI64n68). -;; operands 0-5 as in the non-looping interface -;; operand 6 is the loop count - -(define_expand "call_movstrsi_loop" - [(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" ""))) - (set (match_operand:SI 5 "register_operand" "") - (match_operand 4 "memory_operand" "")) - (set (reg:SI 2) (minus:SI (match_operand:SI 1 "register_operand" "") - (match_dup 3))) - (set (reg:SI 6) (match_operand:SI 6 "immediate_operand" "")) - (use (reg:SI 2)) - (use (reg:SI 3)) - (use (match_dup 5)) - (use (reg:SI 6)) - (parallel [(set (reg:DI 2) - (call (mem:SI (match_operand 0 "" "")) - (const_int 0))) - (clobber (reg:SI 1))])] - "" - "") - -;;- zero extension instructions - -(define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] - "" - " -{ - if (GET_CODE (operands[1]) == MEM - && symbolic_address_p (XEXP (operands[1], 0))) - operands[1] - = legitimize_address (flag_pic, operands[1], 0, 0); -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (zero_extend:SI (match_operand:HI 1 "move_operand" "!r,n,m")))] - "GET_CODE (operands[1]) != CONST_INT" - "@ - mask %0,%1,0xffff - or %0,%#r0,%h1 - %V1ld.hu\\t %0,%1" - [(set_attr "type" "arith,arith,load")]) - -(define_expand "zero_extendqihi2" - [(set (match_operand:HI 0 "register_operand" "") - (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] - "" - " -{ - if (GET_CODE (operands[1]) == MEM - && symbolic_address_p (XEXP (operands[1], 0))) - operands[1] - = legitimize_address (flag_pic, operands[1], 0, 0); -}") - -(define_insn "" - [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (zero_extend:HI (match_operand:QI 1 "move_operand" "r,n,m")))] - "GET_CODE (operands[1]) != CONST_INT" - "@ - mask %0,%1,0xff - or %0,%#r0,%q1 - %V1ld.bu\\t %0,%1" - [(set_attr "type" "arith,arith,load")]) - -(define_expand "zero_extendqisi2" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] - "" - " -{ - if (GET_CODE (operands[1]) == MEM - && symbolic_address_p (XEXP (operands[1], 0))) - { - operands[1] - = legitimize_address (flag_pic, operands[1], 0, 0); - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_ZERO_EXTEND (SImode, operands[1]))); - DONE; - } -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (zero_extend:SI (match_operand:QI 1 "move_operand" "r,n,m")))] - "GET_CODE (operands[1]) != CONST_INT" - "@ - mask %0,%1,0xff - or %0,%#r0,%q1 - %V1ld.bu\\t %0,%1" - [(set_attr "type" "arith,arith,load")]) - -;;- sign extension instructions - -(define_expand "extendsidi2" - [(set (subreg:SI (match_operand:DI 0 "register_operand" "=r") 4) - (match_operand:SI 1 "general_operand" "g")) - (set (subreg:SI (match_dup 0) 0) - (ashiftrt:SI (subreg:SI (match_dup 0) 4) - (const_int 31)))] - "" - "") - -(define_expand "extendhisi2" - [(set (match_operand:SI 0 "register_operand" "") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] - "" - " -{ - if (GET_CODE (operands[1]) == MEM - && symbolic_address_p (XEXP (operands[1], 0))) - operands[1] - = legitimize_address (flag_pic, operands[1], 0, 0); -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") - (sign_extend:SI (match_operand:HI 1 "move_operand" "!r,P,N,m")))] - "GET_CODE (operands[1]) != CONST_INT" - "@ - ext %0,%1,16<0> - or %0,%#r0,%h1 - subu %0,%#r0,%H1 - %V1ld.h\\t %0,%1" - [(set_attr "type" "bit,arith,arith,load")]) - -(define_expand "extendqihi2" - [(set (match_operand:HI 0 "register_operand" "") - (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] - "" - " -{ - if (GET_CODE (operands[1]) == MEM - && symbolic_address_p (XEXP (operands[1], 0))) - operands[1] - = legitimize_address (flag_pic, operands[1], 0, 0); -}") - -(define_insn "" - [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") - (sign_extend:HI (match_operand:QI 1 "move_operand" "!r,P,N,m")))] - "GET_CODE (operands[1]) != CONST_INT" - "@ - ext %0,%1,8<0> - or %0,%#r0,%q1 - subu %0,%#r0,%Q1 - %V1ld.b\\t %0,%1" - [(set_attr "type" "bit,arith,arith,load")]) - -(define_expand "extendqisi2" - [(set (match_operand:SI 0 "register_operand" "") - (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] - "" - " -{ - if (GET_CODE (operands[1]) == MEM - && symbolic_address_p (XEXP (operands[1], 0))) - operands[1] - = legitimize_address (flag_pic, operands[1], 0, 0); -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") - (sign_extend:SI (match_operand:QI 1 "move_operand" "!r,P,N,m")))] - "GET_CODE (operands[1]) != CONST_INT" - "@ - ext %0,%1,8<0> - or %0,%#r0,%q1 - subu %0,%#r0,%Q1 - %V1ld.b\\t %0,%1" - [(set_attr "type" "bit,arith,arith,load")]) - -;; Conversions between float and double. - -;; The fadd instruction does not conform to IEEE 754 when used to -;; convert between float and double. In particular, the sign of -0 is -;; not preserved. Interestingly, fsub does conform. - -(define_expand "extendsfdf2" - [(set (match_operand:DF 0 "register_operand" "=r") - (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] - "" - "") - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r") - (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] - "! TARGET_88110" - "fsub.dss %0,%1,%#r0" - [(set_attr "type" "spadd")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")))] - "TARGET_88110" - "fcvt.ds %0,%1" - [(set_attr "type" "spadd")]) - -(define_expand "truncdfsf2" - [(set (match_operand:SF 0 "register_operand" "=r") - (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] - "" - "") - -(define_insn "" - [(set (match_operand:SF 0 "register_operand" "=r") - (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] - "! TARGET_88110" - "fsub.sds %0,%1,%#r0" - [(set_attr "type" "dpadd")]) - -(define_insn "" - [(set (match_operand:SF 0 "register_operand" "=r,x") - (float_truncate:SF (match_operand:DF 1 "register_operand" "r,x")))] - "TARGET_88110" - "fcvt.sd %0,%1" - [(set_attr "type" "dpadd")]) - -;; Conversions between floating point and integer - -(define_insn "floatsidf2" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (float:DF (match_operand:SI 1 "register_operand" "r,r")))] - "" - "flt.ds %0,%1" - [(set_attr "type" "spadd,dpadd")]) - -(define_insn "floatsisf2" - [(set (match_operand:SF 0 "register_operand" "=r,x") - (float:SF (match_operand:SI 1 "register_operand" "r,r")))] - "" - "flt.ss %0,%1" - [(set_attr "type" "spadd,spadd")]) - -(define_insn "fix_truncdfsi2" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (fix:SI (match_operand:DF 1 "register_operand" "r,x")))] - "" - "trnc.sd %0,%1" - [(set_attr "type" "dpadd,dpadd")]) - -(define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (fix:SI (match_operand:SF 1 "register_operand" "r,x")))] - "" - "trnc.ss %0,%1" - [(set_attr "type" "spadd,dpadd")]) - - -;;- arithmetic instructions -;;- add instructions - -(define_insn "addsi3" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (plus:SI (match_operand:SI 1 "add_operand" "%r,r") - (match_operand:SI 2 "add_operand" "rI,J")))] - "" - "@ - addu %0,%1,%2 - subu %0,%1,%n2") - -;; patterns for mixed mode floating point. -;; Do not define patterns that utilize mixed mode arithmetic that result -;; in narrowing the precision, because it loses accuracy, since the standard -;; requires double rounding, whereas the 88000 instruction only rounds once. - -(define_expand "adddf3" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (plus:DF (match_operand:DF 1 "general_operand" "%r,x") - (match_operand:DF 2 "general_operand" "r,x")))] - "" - " -{ - operands[1] = legitimize_operand (operands[1], DFmode); - operands[2] = legitimize_operand (operands[2], DFmode); -}") - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) - (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] - "" - "fadd.dss %0,%1,%2" - [(set_attr "type" "spadd")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (plus:DF (match_operand:DF 1 "register_operand" "r,x") - (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] - "" - "fadd.dds %0,%1,%2" - [(set_attr "type" "dpadd")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) - (match_operand:DF 2 "register_operand" "r,x")))] - "" - "fadd.dsd %0,%1,%2" - [(set_attr "type" "dpadd")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (plus:DF (match_operand:DF 1 "register_operand" "%r,x") - (match_operand:DF 2 "register_operand" "r,x")))] - "" - "fadd.ddd %0,%1,%2" - [(set_attr "type" "dpadd")]) - -(define_insn "addsf3" - [(set (match_operand:SF 0 "register_operand" "=r,x") - (plus:SF (match_operand:SF 1 "register_operand" "%r,x") - (match_operand:SF 2 "register_operand" "r,x")))] - "" - "fadd.sss %0,%1,%2" - [(set_attr "type" "spadd")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (match_operand:DI 1 "register_operand" "r") - (zero_extend:DI - (match_operand:SI 2 "register_operand" "r")))) - (clobber (reg:CC 0))] - "" - "addu.co %d0,%d1,%2\;addu.ci %0,%1,%#r0" - [(set_attr "type" "marith")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (zero_extend:DI - (match_operand:SI 1 "register_operand" "r")) - (match_operand:DI 2 "register_operand" "r"))) - (clobber (reg:CC 0))] - "" - "addu.co %d0,%1,%d2\;addu.ci %0,%#r0,%2" - [(set_attr "type" "marith")]) - -(define_insn "adddi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (match_operand:DI 1 "register_operand" "%r") - (match_operand:DI 2 "register_operand" "r"))) - (clobber (reg:CC 0))] - "" - "addu.co %d0,%d1,%d2\;addu.ci %0,%1,%2" - [(set_attr "type" "marith")]) - -;; Add with carry insns. - -(define_insn "" - [(parallel [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") - (match_operand:SI 2 "reg_or_0_operand" "rO"))) - (set (reg:CC 0) - (unspec:CC [(match_dup 1) (match_dup 2)] 0))])] - "" - "addu.co %r0,%r1,%r2") - -(define_insn "" - [(set (reg:CC 0) (unspec:CC [(match_operand:SI 0 "reg_or_0_operand" "rO") - (match_operand:SI 1 "reg_or_0_operand" "rO")] - 0))] - "" - "addu.co %#r0,%r0,%r1") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") - (unspec:SI [(match_operand:SI 2 "reg_or_0_operand" "rO") - (reg:CC 0)] 0)))] - "" - "addu.ci %r0,%r1,%r2") - -;;- subtract instructions - -(define_insn "subsi3" - [(set (match_operand:SI 0 "register_operand" "=r") - (minus:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith32_operand" "rI")))] - "" - "subu %0,%1,%2") - -;; patterns for mixed mode floating point -;; Do not define patterns that utilize mixed mode arithmetic that result -;; in narrowing the precision, because it loses accuracy, since the standard -;; requires double rounding, whereas the 88000 instruction only rounds once. - -(define_expand "subdf3" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (minus:DF (match_operand:DF 1 "general_operand" "r,x") - (match_operand:DF 2 "general_operand" "r,x")))] - "" - " -{ - operands[1] = legitimize_operand (operands[1], DFmode); - operands[2] = legitimize_operand (operands[2], DFmode); -}") - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) - (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] - "" - "fsub.dss %0,%1,%2" - [(set_attr "type" "spadd")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (minus:DF (match_operand:DF 1 "register_operand" "r,x") - (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] - "" - "fsub.dds %0,%1,%2" - [(set_attr "type" "dpadd")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) - (match_operand:DF 2 "register_operand" "r,x")))] - "" - "fsub.dsd %0,%1,%2" - [(set_attr "type" "dpadd")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (minus:DF (match_operand:DF 1 "register_operand" "r,x") - (match_operand:DF 2 "register_operand" "r,x")))] - "" - "fsub.ddd %0,%1,%2" - [(set_attr "type" "dpadd")]) - -(define_insn "subsf3" - [(set (match_operand:SF 0 "register_operand" "=r,x") - (minus:SF (match_operand:SF 1 "register_operand" "r,x") - (match_operand:SF 2 "register_operand" "r,x")))] - "" - "fsub.sss %0,%1,%2" - [(set_attr "type" "spadd")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (match_operand:DI 1 "register_operand" "r") - (zero_extend:DI - (match_operand:SI 2 "register_operand" "r")))) - (clobber (reg:CC 0))] - "" - "subu.co %d0,%d1,%2\;subu.ci %0,%1,%#r0" - [(set_attr "type" "marith")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (zero_extend:DI - (match_operand:SI 1 "register_operand" "r")) - (match_operand:DI 2 "register_operand" "r"))) - (clobber (reg:CC 0))] - "" - "subu.co %d0,%1,%d2\;subu.ci %0,%#r0,%2" - [(set_attr "type" "marith")]) - -(define_insn "subdi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "register_operand" "r"))) - (clobber (reg:CC 0))] - "" - "subu.co %d0,%d1,%d2\;subu.ci %0,%1,%2" - [(set_attr "type" "marith")]) - -;; Subtract with carry insns. - -(define_insn "" - [(parallel [(set (match_operand:SI 0 "register_operand" "=r") - (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") - (match_operand:SI 2 "reg_or_0_operand" "rO"))) - (set (reg:CC 0) - (unspec:CC [(match_dup 1) (match_dup 2)] 1))])] - "" - "subu.co %r0,%r1,%r2") - -(define_insn "" - [(set (reg:CC 0) (unspec:CC [(match_operand:SI 0 "reg_or_0_operand" "rO") - (match_operand:SI 1 "reg_or_0_operand" "rO")] - 1))] - "" - "subu.co %#r0,%r0,%r1") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") - (unspec:SI [(match_operand:SI 2 "reg_or_0_operand" "rO") - (reg:CC 0)] 1)))] - "" - "subu.ci %r0,%r1,%r2") - -;;- multiply instructions -;; -;; There is an unfounded silicon errata for E.1 requiring that an -;; immediate constant value in div/divu/mul instructions be less than -;; 0x800. This is no longer provided for. - -(define_insn "mulsi3" - [(set (match_operand:SI 0 "register_operand" "=r") - (mult:SI (match_operand:SI 1 "arith32_operand" "%r") - (match_operand:SI 2 "arith32_operand" "rI")))] - "" - "mul %0,%1,%2" - [(set_attr "type" "imul")]) - -(define_insn "umulsidi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) - (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] - "TARGET_88110" - "mulu.d %0,%1,%2" - [(set_attr "type" "imul")]) - -;; patterns for mixed mode floating point -;; Do not define patterns that utilize mixed mode arithmetic that result -;; in narrowing the precision, because it loses accuracy, since the standard -;; requires double rounding, whereas the 88000 instruction only rounds once. - -(define_expand "muldf3" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (mult:DF (match_operand:DF 1 "general_operand" "%r,x") - (match_operand:DF 2 "general_operand" "r,x")))] - "" - " -{ - operands[1] = legitimize_operand (operands[1], DFmode); - operands[2] = legitimize_operand (operands[2], DFmode); -}") - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) - (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] - "" - "fmul.dss %0,%1,%2" - [(set_attr "type" "spmul")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (mult:DF (match_operand:DF 1 "register_operand" "r,x") - (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] - "" - "fmul.dds %0,%1,%2" - [(set_attr "type" "spmul")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) - (match_operand:DF 2 "register_operand" "r,x")))] - "" - "fmul.dsd %0,%1,%2" - [(set_attr "type" "spmul")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (mult:DF (match_operand:DF 1 "register_operand" "%r,x") - (match_operand:DF 2 "register_operand" "r,x")))] - "" - "fmul.ddd %0,%1,%2" - [(set_attr "type" "dpmul")]) - -(define_insn "mulsf3" - [(set (match_operand:SF 0 "register_operand" "=r,x") - (mult:SF (match_operand:SF 1 "register_operand" "%r,x") - (match_operand:SF 2 "register_operand" "r,x")))] - "" - "fmul.sss %0,%1,%2" - [(set_attr "type" "spmul")]) - -;;- divide instructions -;; -;; The 88k div and divu instructions don't reliably trap on -;; divide-by-zero. A trap to vector 503 asserts divide-by-zero. The -;; general scheme for doing divide is to do a 4-way split based on the -;; sign of the two operand and do the appropriate negates. -;; -;; The conditional trap instruction is not used as this serializes the -;; processor. Instead a conditional branch and an unconditional trap -;; are used, but after the divu. Since the divu takes up to 38 cycles, -;; the conditional branch is essentially free. -;; -;; Two target options control how divide is done. One options selects -;; whether to do the branch and negate scheme instead of using the div -;; instruction; the other option selects whether to explicitly check -;; for divide-by-zero or take your chances. If the div instruction is -;; used, the O/S must complete the operation if the operands are -;; negative. The O/S will signal an overflow condition if the most -;; negative number (-2147483648) is divided by negative 1. -;; -;; There is an unfounded silicon errata for E.1 requiring that an -;; immediate constant value in div/divu/mul instructions be less than -;; 0x800. This is no longer provided for. - -;; Division by 0 trap -(define_insn "trap_divide_by_zero" - [(trap_if (const_int 1) (const_int 503))] - "" - "tb0 0,%#r0,503" - [(set_attr "type" "weird")]) - -;; Conditional division by 0 trap. -(define_expand "tcnd_divide_by_zero" - [(set (pc) - (if_then_else (eq (match_operand:SI 0 "register_operand" "") - (const_int 0)) - (pc) - (match_operand 1 "" ""))) - (trap_if (const_int 1) (const_int 503))] - "" - " -{ - emit_insn (gen_cmpsi (operands[0], const0_rtx)); - emit_jump_insn (gen_bne (operands[1])); - emit_insn (gen_trap_divide_by_zero ()); - DONE; -}") - -(define_expand "divsi3" - [(set (match_operand:SI 0 "register_operand" "") - (div:SI (match_operand:SI 1 "arith32_operand" "") - (match_operand:SI 2 "arith32_operand" "")))] - "" - " -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op2 = operands[2]; - rtx join_label; - - /* @@ This needs to be reworked. Torbjorn Granlund has suggested making - it a runtime (perhaps quite special). */ - - if (GET_CODE (op1) == CONST_INT) - op1 = force_reg (SImode, op1); - - else if (GET_CODE (op2) == CONST_INT - && ! SMALL_INT (operands[2])) - op2 = force_reg (SImode, op2); - - if (op2 == const0_rtx) - { - emit_insn (gen_trap_divide_by_zero ()); - emit_insn (gen_dummy (op0)); - DONE; - } - - if (TARGET_USE_DIV) - { - emit_move_insn (op0, gen_rtx_DIV (SImode, op1, op2)); - if (TARGET_CHECK_ZERO_DIV && GET_CODE (op2) != CONST_INT) - { - rtx label = gen_label_rtx (); - emit_insn (gen_tcnd_divide_by_zero (op2, label)); - emit_label (label); - emit_insn (gen_dummy (op0)); - } - DONE; - } - - join_label = gen_label_rtx (); - if (GET_CODE (op1) == CONST_INT) - { - int neg = FALSE; - rtx neg_op2 = gen_reg_rtx (SImode); - rtx label1 = gen_label_rtx (); - - if (INTVAL (op1) < 0) - { - neg = TRUE; - op1 = GEN_INT (-INTVAL (op1)); - } - op1 = force_reg (SImode, op1); - - emit_insn (gen_negsi2 (neg_op2, op2)); - emit_insn (gen_cmpsi (op2, const0_rtx)); - emit_jump_insn (gen_bgt (label1)); - /* constant / 0-or-negative */ - emit_move_insn (op0, gen_rtx_UDIV (SImode, op1, neg_op2)); - if (!neg) - emit_insn (gen_negsi2 (op0, op0)); - - if (TARGET_CHECK_ZERO_DIV) - emit_insn (gen_tcnd_divide_by_zero (op2, join_label)); - emit_jump_insn (gen_jump (join_label)); - emit_barrier (); - - emit_label (label1); /* constant / positive */ - emit_move_insn (op0, gen_rtx_UDIV (SImode, op1, op2)); - if (neg) - emit_insn (gen_negsi2 (op0, op0)); - } - - else if (GET_CODE (op2) == CONST_INT) - { - int neg = FALSE; - rtx neg_op1 = gen_reg_rtx (SImode); - rtx label1 = gen_label_rtx (); - - if (INTVAL (op2) < 0) - { - neg = TRUE; - op2 = GEN_INT (-INTVAL (op2)); - } - else if (! SMALL_INT (operands[2])) - op2 = force_reg (SImode, op2); - - emit_insn (gen_negsi2 (neg_op1, op1)); - emit_insn (gen_cmpsi (op1, const0_rtx)); - emit_jump_insn (gen_bge (label1)); - /* 0-or-negative / constant */ - emit_move_insn (op0, gen_rtx_UDIV (SImode, neg_op1, op2)); - if (!neg) - emit_insn (gen_negsi2 (op0, op0)); - - emit_jump_insn (gen_jump (join_label)); - emit_barrier (); - - emit_label (label1); /* positive / constant */ - emit_move_insn (op0, gen_rtx_UDIV (SImode, op1, op2)); - if (neg) - emit_insn (gen_negsi2 (op0, op0)); - } - - else - { - rtx neg_op1 = gen_reg_rtx (SImode); - rtx neg_op2 = gen_reg_rtx (SImode); - rtx label1 = gen_label_rtx (); - rtx label2 = gen_label_rtx (); - rtx label3 = gen_label_rtx (); - rtx label4 = NULL_RTX; - - emit_insn (gen_negsi2 (neg_op2, op2)); - emit_insn (gen_cmpsi (op2, const0_rtx)); - emit_jump_insn (gen_bgt (label1)); - - emit_insn (gen_negsi2 (neg_op1, op1)); - emit_insn (gen_cmpsi (op1, const0_rtx)); - emit_jump_insn (gen_bge (label2)); - /* negative / negative-or-0 */ - emit_move_insn (op0, gen_rtx_UDIV (SImode, neg_op1, neg_op2)); - - if (TARGET_CHECK_ZERO_DIV) - { - label4 = gen_label_rtx (); - emit_insn (gen_cmpsi (op2, const0_rtx)); - emit_jump_insn (gen_bne (join_label)); - emit_label (label4); - emit_insn (gen_trap_divide_by_zero ()); - } - emit_jump_insn (gen_jump (join_label)); - emit_barrier (); - - emit_label (label2); /* pos.-or-0 / neg.-or-0 */ - emit_move_insn (op0, gen_rtx_UDIV (SImode, op1, neg_op2)); - - if (TARGET_CHECK_ZERO_DIV) - { - emit_insn (gen_cmpsi (op2, const0_rtx)); - emit_jump_insn (gen_beq (label4)); - } - - emit_insn (gen_negsi2 (op0, op0)); - emit_jump_insn (gen_jump (join_label)); - emit_barrier (); - - emit_label (label1); - emit_insn (gen_negsi2 (neg_op1, op1)); - emit_insn (gen_cmpsi (op1, const0_rtx)); - emit_jump_insn (gen_bge (label3)); - /* negative / positive */ - emit_move_insn (op0, gen_rtx_UDIV (SImode, neg_op1, op2)); - emit_insn (gen_negsi2 (op0, op0)); - emit_jump_insn (gen_jump (join_label)); - emit_barrier (); - - emit_label (label3); /* positive-or-0 / positive */ - emit_move_insn (op0, gen_rtx_UDIV (SImode, op1, op2)); - } - - emit_label (join_label); - - emit_insn (gen_dummy (op0)); - DONE; -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (div:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith_operand" "rI")))] - "" - "div %0,%1,%2" - [(set_attr "type" "idiv")]) - -(define_expand "udivsi3" - [(set (match_operand:SI 0 "register_operand" "") - (udiv:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "arith32_operand" "")))] - "" - " -{ - rtx op2 = operands[2]; - - if (op2 == const0_rtx) - { - emit_insn (gen_trap_divide_by_zero ()); - emit_insn (gen_dummy (operands[0])); - DONE; - } - else if (GET_CODE (op2) != CONST_INT && TARGET_CHECK_ZERO_DIV) - { - rtx label = gen_label_rtx (); - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_UDIV (SImode, operands[1], op2))); - emit_insn (gen_tcnd_divide_by_zero (op2, label)); - emit_label (label); - emit_insn (gen_dummy (operands[0])); - DONE; - } -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (udiv:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith32_operand" "rI")))] - "operands[2] != const0_rtx" - "divu %0,%1,%2" - [(set_attr "type" "idiv")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (udiv:SI (match_operand:SI 1 "register_operand" "r") - (const_int 0)))] - "" - "tb0 0,%#r0,503" - [(set_attr "type" "weird")]) - -;; patterns for mixed mode floating point. -;; Do not define patterns that utilize mixed mode arithmetic that result -;; in narrowing the precision, because it loses accuracy, since the standard -;; requires double rounding, whereas the 88000 instruction only rounds once. - -(define_expand "divdf3" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (div:DF (match_operand:DF 1 "general_operand" "r,x") - (match_operand:DF 2 "general_operand" "r,x")))] - "" - " -{ - operands[1] = legitimize_operand (operands[1], DFmode); - if (real_power_of_2_operand (operands[2], DFmode)) - { - REAL_VALUE_TYPE r; - REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]); - if (!exact_real_inverse (DFmode, &r)) - abort (); - emit_insn (gen_muldf3 (operands[0], operands[1], - CONST_DOUBLE_FROM_REAL_VALUE (r, DFmode))); - DONE; - } - else if (! register_operand (operands[2], DFmode)) - operands[2] = force_reg (DFmode, operands[2]); -}") - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) - (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] - "" - "fdiv.dss %0,%1,%2" - [(set_attr "type" "dpdiv")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (div:DF (match_operand:DF 1 "register_operand" "r,x") - (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] - "" - "fdiv.dds %0,%1,%2" - [(set_attr "type" "dpdiv")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) - (match_operand:DF 2 "register_operand" "r,x")))] - "" - "fdiv.dsd %0,%1,%2" - [(set_attr "type" "dpdiv")]) - -(define_insn "divsf3" - [(set (match_operand:SF 0 "register_operand" "=r,x") - (div:SF (match_operand:SF 1 "register_operand" "r,x") - (match_operand:SF 2 "register_operand" "r,x")))] - "" - "fdiv.sss %0,%1,%2" - [(set_attr "type" "spdiv")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=r,x") - (div:DF (match_operand:DF 1 "register_operand" "r,x") - (match_operand:DF 2 "register_operand" "r,x")))] - "" - "fdiv.ddd %0,%1,%2" - [(set_attr "type" "dpdiv")]) - -;; - remainder instructions, don't define, since the hardware doesn't have any -;; direct support, and GNU can synthesis them out of div/mul just fine. - -;;- load effective address, must come after add, so that we favor using -;; addu reg,reg,reg instead of: lda reg,reg,reg (addu doesn't require -;; the data unit), and also future 88k chips might not support unscaled -;; lda instructions. - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:SI 1 "address_operand" "p"))] - "m88k_gp_threshold > 0 && symbolic_address_p (operands[1])" - "addu %0,%a1") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:HI 1 "address_operand" "p"))] - "" - "lda.h %0,%a1" - [(set_attr "type" "loada")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:SI 1 "address_operand" "p"))] - "" - "lda %0,%a1" - [(set_attr "type" "loada")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:DI 1 "address_operand" "p"))] - "" - "lda.d %0,%a1" - [(set_attr "type" "loada")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:SF 1 "address_operand" "p"))] - "" - "lda %0,%a1" - [(set_attr "type" "loada")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:DF 1 "address_operand" "p"))] - "" - "lda.d %0,%a1" - [(set_attr "type" "loada")]) - -;;- and instructions (with complement also) -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (and:SI (not:SI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "register_operand" "r")))] - "" - "and.c %0,%2,%1") - -;; If the operation is being performed on a 32-bit constant such that -;; it cannot be done in one insn, do it in two. We may lose a bit on -;; CSE in pathological cases, but it seems better doing it this way. - -(define_expand "andsi3" - [(set (match_operand:SI 0 "register_operand" "") - (and:SI (match_operand:SI 1 "arith32_operand" "") - (match_operand:SI 2 "arith32_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - int value = INTVAL (operands[2]); - - if (! (SMALL_INTVAL (value) - || (value & 0xffff0000) == 0xffff0000 - || (value & 0xffff) == 0xffff - || (value & 0xffff) == 0 - || integer_ok_for_set (~value))) - { - emit_insn (gen_andsi3 (operands[0], operands[1], - GEN_INT (value | 0xffff))); - operands[1] = operands[0]; - operands[2] = GEN_INT (value | 0xffff0000); - } - } -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (and:SI (match_operand:SI 1 "arith32_operand" "%r,r") - (match_operand:SI 2 "arith32_operand" "rIJL,rn")))] - "" - "* return output_and (operands);" - [(set_attr "type" "arith,marith")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI (not:DI (match_operand:DI 1 "register_operand" "r")) - (match_operand:DI 2 "register_operand" "r")))] - "" - "and.c %d0,%d2,%d1\;and.c %0,%2,%1" - [(set_attr "type" "marith")]) - -(define_insn "anddi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI (match_operand:DI 1 "arith64_operand" "%r") - (match_operand:DI 2 "arith64_operand" "rn")))] - "" - "* -{ - rtx xoperands[10]; - - xoperands[0] = operand_subword (operands[0], 1, 0, DImode); - xoperands[1] = operand_subword (operands[1], 1, 0, DImode); - xoperands[2] = operand_subword (operands[2], 1, 0, DImode); - - output_asm_insn (output_and (xoperands), xoperands); - - operands[0] = operand_subword (operands[0], 0, 0, DImode); - operands[1] = operand_subword (operands[1], 0, 0, DImode); - operands[2] = operand_subword (operands[2], 0, 0, DImode); - - return output_and (operands); -}" - [(set_attr "type" "marith") - (set_attr "length" "4")]) ; length is 2, 3, or 4. - -;;- Bit set (inclusive or) instructions (with complement also) -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (not:SI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "register_operand" "r")))] - "" - "or.c %0,%2,%1") - -(define_expand "iorsi3" - [(set (match_operand:SI 0 "register_operand" "") - (ior:SI (match_operand:SI 1 "arith32_operand" "") - (match_operand:SI 2 "arith32_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - int value = INTVAL (operands[2]); - - if (! (SMALL_INTVAL (value) - || (value & 0xffff) == 0 - || integer_ok_for_set (value))) - { - emit_insn (gen_iorsi3 (operands[0], operands[1], - GEN_INT (value & 0xffff0000))); - operands[1] = operands[0]; - operands[2] = GEN_INT (value & 0xffff); - } - } -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") - (ior:SI (match_operand:SI 1 "arith32_operand" "%r,r,r,r") - (match_operand:SI 2 "arith32_operand" "rI,L,M,n")))] - "" - "@ - or %0,%1,%2 - or.u %0,%1,%X2 - set %0,%1,%s2 - or.u %0,%1,%X2\;or %0,%0,%x2" - [(set_attr "type" "arith,arith,bit,marith")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r")) - (match_operand:DI 2 "register_operand" "r")))] - "" - "or.c %d0,%d2,%d1\;or.c %0,%2,%1" - [(set_attr "type" "marith")]) - -(define_insn "iordi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (ior:DI (match_operand:DI 1 "arith64_operand" "%r") - (match_operand:DI 2 "arith64_operand" "rn")))] - "" - "* -{ - rtx xoperands[10]; - - xoperands[0] = operand_subword (operands[0], 1, 0, DImode); - xoperands[1] = operand_subword (operands[1], 1, 0, DImode); - xoperands[2] = operand_subword (operands[2], 1, 0, DImode); - - output_asm_insn (output_ior (xoperands), xoperands); - - operands[0] = operand_subword (operands[0], 0, 0, DImode); - operands[1] = operand_subword (operands[1], 0, 0, DImode); - operands[2] = operand_subword (operands[2], 0, 0, DImode); - - return output_ior (operands); -}" - [(set_attr "type" "marith") - (set_attr "length" "4")]) ; length is 2, 3, or 4. - -;;- xor instructions (with complement also) -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%r") - (match_operand:SI 2 "register_operand" "r"))))] - "" - "xor.c %0,%1,%2") - -(define_expand "xorsi3" - [(set (match_operand:SI 0 "register_operand" "") - (xor:SI (match_operand:SI 1 "arith32_operand" "") - (match_operand:SI 2 "arith32_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - int value = INTVAL (operands[2]); - - if (! (SMALL_INTVAL (value) - || (value & 0xffff) == 0)) - { - emit_insn (gen_xorsi3 (operands[0], operands[1], - GEN_INT (value & 0xffff0000))); - operands[1] = operands[0]; - operands[2] = GEN_INT (value & 0xffff); - } - } -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (xor:SI (match_operand:SI 1 "arith32_operand" "%r,r,r") - (match_operand:SI 2 "arith32_operand" "rI,L,n")))] - "" - "@ - xor %0,%1,%2 - xor.u %0,%1,%X2 - xor.u %0,%1,%X2\;xor %0,%0,%x2" - [(set_attr "type" "arith,arith,marith")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (not:DI (xor:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "register_operand" "r"))))] - "" - "xor.c %d0,%d1,%d2\;xor.c %0,%1,%2" - [(set_attr "type" "marith")]) - -(define_insn "xordi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (xor:DI (match_operand:DI 1 "arith64_operand" "%r") - (match_operand:DI 2 "arith64_operand" "rn")))] - "" - "* -{ - rtx xoperands[10]; - - xoperands[0] = operand_subword (operands[0], 1, 0, DImode); - xoperands[1] = operand_subword (operands[1], 1, 0, DImode); - xoperands[2] = operand_subword (operands[2], 1, 0, DImode); - - output_asm_insn (output_xor (xoperands), xoperands); - - operands[0] = operand_subword (operands[0], 0, 0, DImode); - operands[1] = operand_subword (operands[1], 0, 0, DImode); - operands[2] = operand_subword (operands[2], 0, 0, DImode); - - return output_xor (operands); -}" - [(set_attr "type" "marith") - (set_attr "length" "4")]) ; length is 2, 3, or 4. - -;;- ones complement instructions -(define_insn "one_cmplsi2" - [(set (match_operand:SI 0 "register_operand" "=r") - (not:SI (match_operand:SI 1 "register_operand" "r")))] - "" - "xor.c %0,%1,%#r0") - -(define_insn "one_cmpldi2" - [(set (match_operand:DI 0 "register_operand" "=r") - (not:DI (match_operand:DI 1 "register_operand" "r")))] - "" - "xor.c %d0,%d1,%#r0\;xor.c %0,%1,%#r0" - [(set_attr "type" "marith")]) - -;; Optimized special cases of shifting. -;; Must precede the general case. - -;; @@ What about HImode shifted by 8? - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") - (const_int 24)))] - "! SCALED_ADDRESS_P (XEXP (operands[1], 0))" - "%V1ld.b\\t %0,%1" - [(set_attr "type" "load")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") - (const_int 24)))] - "! SCALED_ADDRESS_P (XEXP (operands[1], 0))" - "%V1ld.bu\\t %0,%1" - [(set_attr "type" "load")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") - (const_int 16)))] - "! SCALED_ADDRESS_P (XEXP (operands[1], 0))" - "%V1ld.h\\t %0,%1" - [(set_attr "type" "load")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") - (const_int 16)))] - "! SCALED_ADDRESS_P (XEXP (operands[1], 0))" - "%V1ld.hu\\t %0,%1" - [(set_attr "type" "load")]) - -;;- arithmetic shift instructions. - -;; @@ Do the optimized patterns with -1 get used? Perhaps operand 1 should -;; be arith32_operand? - -;; Use tbnd to support TARGET_TRAP_LARGE_SHIFT. -(define_insn "tbnd" - [(trap_if (gtu (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "arith_operand" "rI")) - (const_int 7))] - "" - "tbnd %r0,%1" - [(set_attr "type" "weird")]) - -;; Just in case the optimizer decides to fold away the test. -(define_insn "" - [(trap_if (const_int 1) (const_int 7))] - "" - "tbnd %#r31,0" - [(set_attr "type" "weird")]) - -(define_expand "ashlsi3" - [(set (match_operand:SI 0 "register_operand" "") - (ashift:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "arith32_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - if ((unsigned) INTVAL (operands[2]) > 31) - { - if (TARGET_TRAP_LARGE_SHIFT) - emit_insn (gen_tbnd (force_reg (SImode, operands[2]), - GEN_INT (31))); - else - emit_move_insn (operands[0], const0_rtx); - DONE; - } - } - - else if (TARGET_TRAP_LARGE_SHIFT) - emit_insn (gen_tbnd (operands[2], GEN_INT (31))); - - else if (TARGET_HANDLE_LARGE_SHIFT) - { - rtx reg = gen_reg_rtx (SImode); - emit_insn (gen_cmpsi (operands[2], GEN_INT (31))); - emit_insn (gen_sleu (reg)); - emit_insn (gen_andsi3 (reg, operands[1], reg)); - operands[1] = reg; - } -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (ashift:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "arith5_operand" "r,K")))] - "" - "@ - mak %0,%1,%2 - mak %0,%1,0<%2>" - [(set_attr "type" "bit")]) - -(define_expand "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "arith32_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - if ((unsigned) INTVAL (operands[2]) > 31) - { - if (TARGET_TRAP_LARGE_SHIFT) - { - emit_insn (gen_tbnd (force_reg (SImode, operands[2]), - GEN_INT (31))); - DONE; - } - else - operands[2] = GEN_INT (31); - } - } - - else if (TARGET_TRAP_LARGE_SHIFT) - emit_insn (gen_tbnd (operands[2], GEN_INT (31))); - - else if (TARGET_HANDLE_LARGE_SHIFT) - { - rtx reg = gen_reg_rtx (SImode); - emit_insn (gen_cmpsi (operands[2], GEN_INT (31))); - emit_insn (gen_sgtu (reg)); - emit_insn (gen_iorsi3 (reg, operands[2], reg)); - operands[2] = reg; - } -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "arith5_operand" "r,K")))] - "" - "@ - ext %0,%1,%2 - ext %0,%1,0<%2>" - [(set_attr "type" "bit")]) - -;;- logical shift instructions. Logical shift left becomes arithmetic -;; shift left. - -(define_expand "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "arith32_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - if ((unsigned) INTVAL (operands[2]) > 31) - { - if (TARGET_TRAP_LARGE_SHIFT) - emit_insn (gen_tbnd (force_reg (SImode, operands[2]), - GEN_INT (31))); - else - emit_move_insn (operands[0], const0_rtx); - DONE; - } - } - - else if (TARGET_TRAP_LARGE_SHIFT) - emit_insn (gen_tbnd (operands[2], GEN_INT (31))); - - else if (TARGET_HANDLE_LARGE_SHIFT) - { - rtx reg = gen_reg_rtx (SImode); - emit_insn (gen_cmpsi (operands[2], GEN_INT (31))); - emit_insn (gen_sleu (reg)); - emit_insn (gen_andsi3 (reg, operands[1], reg)); - operands[1] = reg; - } -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "arith5_operand" "r,K")))] - "" - "@ - extu %0,%1,%2 - extu %0,%1,0<%2>" - [(set_attr "type" "bit")]) - -;;- rotate instructions - -(define_expand "rotlsi3" - [(set (match_operand:SI 0 "register_operand" "") - (rotatert:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "arith32_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned) INTVAL (operands[2]) >= 32) - operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32); - else - { - rtx op = gen_reg_rtx (SImode); - emit_insn (gen_negsi2 (op, operands[2])); - operands[2] = op; - } -}") - -(define_insn "rotrsi3" - [(set (match_operand:SI 0 "register_operand" "=r") - (rotatert:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith_operand" "rI")))] - "" - "rot %0,%1,%2" - [(set_attr "type" "bit")]) - -;; find first set. - -;; The ff1 instruction searches from the most significant bit while ffs -;; searches from the least significant bit. The bit index and treatment of -;; zero also differ. This amazing sequence was discovered using the GNU -;; Superoptimizer. - -(define_insn "ffssi2" - [(set (match_operand:SI 0 "register_operand" "=r,&r") - (ffs:SI (match_operand:SI 1 "register_operand" "0,r"))) - (clobber (reg:CC 0)) - (clobber (match_scratch:SI 2 "=r,X"))] - "" - "@ - subu.co %2,%#r0,%1\;and %2,%2,%1\;addu.ci %2,%2,%2\;ff1 %0,%2 - subu.co %0,%#r0,%1\;and %0,%0,%1\;addu.ci %0,%0,%0\;ff1 %0,%0" - [(set_attr "type" "marith") - (set_attr "length" "4")]) - -;; Bit field instructions. - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extract:SI (match_operand:SI 1 "register_operand" "r") - (const_int 32) - (const_int 0)))] - "" - "or %0,%#r0,%1") - -(define_insn "extv" - [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extract:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "int5_operand" "") - (match_operand:SI 3 "int5_operand" "")))] - "" - "* -{ - operands[4] = GEN_INT ((32 - INTVAL (operands[2])) - INTVAL (operands[3])); - return \"ext %0,%1,%2<%4>\"; /* <(32-%2-%3)> */ -}" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extract:SI (match_operand:SI 1 "register_operand" "r") - (const_int 32) - (const_int 0)))] - "" - "or %0,%#r0,%1") - -(define_insn "extzv" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extract:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "int5_operand" "") - (match_operand:SI 3 "int5_operand" "")))] - "" - "* -{ - operands[4] = GEN_INT ((32 - INTVAL (operands[2])) - INTVAL (operands[3])); - return \"extu %0,%1,%2<%4>\"; /* <(32-%2-%3)> */ -}" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") - (match_operand:SI 1 "int5_operand" "") - (match_operand:SI 2 "int5_operand" "")) - (const_int 0))] - "" - "* -{ - operands[3] = GEN_INT ((32 - INTVAL (operands[1])) - INTVAL (operands[2])); - return \"clr %0,%0,%1<%3>\"; /* <(32-%1-%2)> */ -}" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") - (match_operand:SI 1 "int5_operand" "") - (match_operand:SI 2 "int5_operand" "")) - (const_int -1))] - "" - "* -{ - operands[3] = GEN_INT ((32 - INTVAL (operands[1])) - INTVAL (operands[2])); - return \"set %0,%0,%1<%3>\"; /* <(32-%1-%2)> */ -}" - [(set_attr "type" "bit")]) - -(define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") - (match_operand:SI 1 "int5_operand" "") - (match_operand:SI 2 "int5_operand" "")) - (match_operand:SI 3 "int32_operand" "n"))] - "" - "* -{ - int value = INTVAL (operands[3]); - - if (INTVAL (operands[1]) < 32) - value &= (1 << INTVAL (operands[1])) - 1; - - operands[2] = GEN_INT (32 - (INTVAL(operands[1]) + INTVAL(operands[2]))); - - value <<= INTVAL (operands[2]); - operands[3] = GEN_INT (value); - - if (SMALL_INTVAL (value)) - return \"clr %0,%0,%1<%2>\;or %0,%0,%3\"; - else if ((value & 0x0000ffff) == 0) - return \"clr %0,%0,%1<%2>\;or.u %0,%0,%X3\"; - else - return \"clr %0,%0,%1<%2>\;or.u %0,%0,%X3\;or %0,%0,%x3\"; -}" - [(set_attr "type" "marith") - (set_attr "length" "3")]) ; may be 2 or 3. - -;; negate insns -(define_insn "negsi2" - [(set (match_operand:SI 0 "register_operand" "=r") - (neg:SI (match_operand:SI 1 "arith_operand" "rI")))] - "" - "subu %0,%#r0,%1") - -(define_insn "" - [(set (match_operand:SF 0 "register_operand" "=r,x") - (float_truncate:SF (neg:DF (match_operand:DF 1 "register_operand" "r,x"))))] - "" - "@ - fsub.ssd %0,%#r0,%1 - fsub.ssd %0,%#x0,%1" - [(set_attr "type" "dpadd")]) - -(define_insn "negdf2" - [(set (match_operand:DF 0 "register_operand" "=&r,r") - (neg:DF (match_operand:DF 1 "register_operand" "r,0")))] - "" - "@ - xor.u %0,%1,0x8000\;or %d0,%#r0,%d1 - xor.u %0,%0,0x8000" - [(set_attr "type" "marith,arith")]) - -(define_insn "negsf2" - [(set (match_operand:SF 0 "register_operand" "=r") - (neg:SF (match_operand:SF 1 "register_operand" "r")))] - "" - "xor.u %0,%1,0x8000") - -;; absolute value insns for floating-point (integer abs can be done using the -;; machine-independent sequence). - -(define_insn "absdf2" - [(set (match_operand:DF 0 "register_operand" "=&r,r") - (abs:DF (match_operand:DF 1 "register_operand" "r,0")))] - "" - "@ - and.u %0,%1,0x7fff\;or %d0,%#r0,%d1 - and.u %0,%0,0x7fff" - [(set_attr "type" "marith,arith")]) - -(define_insn "abssf2" - [(set (match_operand:SF 0 "register_operand" "=r") - (abs:SF (match_operand:SF 1 "register_operand" "r")))] - "" - "and.u %0,%1,0x7fff") - -;; Subroutines of "casesi". - -;; Operand 0 is index -;; operand 1 is the minimum bound -;; operand 2 is the maximum bound - minimum bound + 1 -;; operand 3 is CODE_LABEL for the table; -;; operand 4 is the CODE_LABEL to go to if index out of range. - -(define_expand "casesi" - ;; We don't use these for generating the RTL, but we must describe - ;; the operands here. - [(match_operand:SI 0 "general_operand" "") - (match_operand:SI 1 "immediate_operand" "") - (match_operand:SI 2 "immediate_operand" "") - (match_operand 3 "" "") - (match_operand 4 "" "")] - "" - " -{ - register rtx index_diff = gen_reg_rtx (SImode); - register rtx low = GEN_INT (-INTVAL (operands[1])); - register rtx label = gen_rtx_LABEL_REF (Pmode, operands[3]); - register rtx base = NULL_RTX; - - if (! CASE_VECTOR_INSNS) - /* These instructions are likely to be scheduled and made loop invariant. - This decreases the cost of the dispatch at the expense of the default - case. */ - base = force_reg (SImode, memory_address_noforce (SImode, label)); - - /* Compute the index difference and handle the default case. */ - emit_insn (gen_addsi3 (index_diff, - force_reg (SImode, operands[0]), - ADD_INT (low) ? low : force_reg (SImode, low))); - emit_insn (gen_cmpsi (index_diff, operands[2])); - /* It's possible to replace this branch with sgtu/iorsi3 and adding a -1 - entry to the table. However, that doesn't seem to win on the m88110. */ - emit_jump_insn (gen_bgtu (operands[4])); - - if (CASE_VECTOR_INSNS) - /* Call the jump that will branch to the appropriate case. */ - emit_jump_insn (gen_casesi_enter (label, index_diff, operands[3])); - else - /* Load the table entry and jump to it. */ - emit_jump_insn (gen_casesi_jump (gen_reg_rtx (SImode), base, index_diff, operands[3])); - - /* Claim that flow drops into the table so it will be adjacent by not - emitting a barrier. */ - DONE; -}") - -(define_expand "casesi_jump" - [(set (match_operand:SI 0 "" "") - (mem:SI (plus:SI (match_operand:SI 1 "" "") - (mult:SI (match_operand:SI 2 "" "") - (const_int 4))))) - (parallel [(set (pc) (match_dup 0)) - (use (label_ref (match_operand 3 "" "")))])] - "" - "") - -(define_insn "" - [(set (pc) (match_operand:SI 0 "register_operand" "r")) - (use (label_ref (match_operand 1 "" "")))] - "" - "jmp%. %0" - [(set_attr "type" "jump")]) - -;; The bsr.n instruction is directed to the END of the table. See -;; ASM_OUTPUT_CASE_END. - -(define_insn "casesi_enter" - [(set (pc) (match_operand 0 "" "")) - (use (match_operand:SI 1 "register_operand" "r")) - ;; The USE here is so that at least one jump-insn will refer to the label, - ;; to keep it alive in jump_optimize. - (use (label_ref (match_operand 2 "" ""))) - (clobber (reg:SI 1))] - "" - "* -{ - if (flag_delayed_branch) - return \"bsr.n %0e\;lda %#r1,%#r1[%1]\"; - m88k_case_index = REGNO (operands[1]); - return \"bsr %0e\"; -}" - [(set_attr "type" "weird") - (set_attr "length" "3")]) ; Including the "jmp r1". - -;;- jump to subroutine -(define_expand "call" - [(parallel [(call (match_operand:SI 0 "" "") - (match_operand 1 "" "")) - (clobber (reg:SI 1))])] - "" - " -{ - if (GET_CODE (operands[0]) == MEM - && ! call_address_operand (XEXP (operands[0], 0), SImode)) - operands[0] = gen_rtx_MEM (GET_MODE (operands[0]), - force_reg (Pmode, XEXP (operands[0], 0))); -}") - -(define_insn "" - [(parallel [(call (mem:SI (match_operand:SI 0 "call_address_operand" "rQ")) - (match_operand 1 "" "")) - (clobber (reg:SI 1))])] - "" - "* return output_call (operands, operands[0]);" - [(set_attr "type" "call")]) - -(define_expand "call_value" - [(parallel [(set (match_operand 0 "register_operand" "") - (call (match_operand:SI 1 "" "") - (match_operand 2 "" ""))) - (clobber (reg:SI 1))])] - "" - " -{ - if (GET_CODE (operands[1]) == MEM - && ! call_address_operand (XEXP (operands[1], 0), SImode)) - operands[1] = gen_rtx_MEM (GET_MODE (operands[1]), - force_reg (Pmode, XEXP (operands[1], 0))); -}") - -(define_insn "" - [(parallel [(set (match_operand 0 "register_operand" "=r") - (call (mem:SI - (match_operand:SI 1 "call_address_operand" "rQ")) - (match_operand 2 "" ""))) - (clobber (reg:SI 1))])] - "" - "* return output_call (operands, operands[1]);" - [(set_attr "type" "call")]) - -;; Nop instruction and others - -(define_insn "nop" - [(const_int 0)] - "" - "ff0 %#r0,%#r0" - [(set_attr "type" "bit")]) - -(define_insn "return" - [(return)] - "reload_completed" - "jmp%. %#r1" - [(set_attr "type" "jump")]) - -(define_expand "prologue" - [(const_int 0)] - "" - "m88k_expand_prologue (); DONE;") - -(define_expand "epilogue" - [(return)] - "! null_prologue ()" - "m88k_expand_epilogue ();") - -(define_insn "blockage" - [(unspec_volatile [(const_int 0)] 0)] - "" - "" - [(set_attr "length" "0")]) - -(define_insn "indirect_jump" - [(set (pc) (match_operand:SI 0 "register_operand" "r"))] - "" - "jmp%. %0" - [(set_attr "type" "jump")]) - -(define_insn "jump" - [(set (pc) - (label_ref (match_operand 0 "" "")))] - "" - "br%. %l0" - [(set_attr "type" "jump")]) - -;; This insn is used for some loop tests, typically loops reversed when -;; strength reduction is used. It is actually created when the instruction -;; combination phase combines the special loop test. Since this insn -;; is both a jump insn and has an output, it must deal with its own -;; reloads, hence the `m' constraints. The `!' constraints direct reload -;; to not choose the register alternatives in the event a reload is needed. - -(define_expand "decrement_and_branch_until_zero" - [(parallel [(set (pc) - (if_then_else - (match_operator 0 "relop_no_unsigned" - [(match_operand:SI 1 "register_operand" "") - (const_int 0)]) - (label_ref (match_operand 2 "" "")) - (pc))) - (set (match_dup 1) - (plus:SI (match_dup 1) - (match_operand:SI 3 "add_operand" ""))) - (clobber (match_scratch:SI 4 "")) - (clobber (match_scratch:SI 5 "=X,X,&r,&r"))])] - "" - "") - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 0 "relop_no_unsigned" - [(match_operand:SI 1 "register_operand" "+!r,!r,m,m") - (const_int 0)]) - (label_ref (match_operand 2 "" "")) - (pc))) - (set (match_dup 1) - (plus:SI (match_dup 1) - (match_operand:SI 3 "add_operand" "rI,J,rI,J"))) - (clobber (match_scratch:SI 4 "=X,X,&r,&r")) - (clobber (match_scratch:SI 5 "=X,X,&r,&r"))] - "find_reg_note (insn, REG_NONNEG, 0)" - "@ - bcnd.n %B0,%1,%2\;addu %1,%1,%3 - bcnd.n %B0,%1,%2\;subu %1,%1,%n3 - ld %4,%1\;addu %5,%4,%3\;bcnd.n %B0,%4,%2\;st %5,%1 - ld %4,%1\;subu %5,%4,%n3\;bcnd.n %B0,%4,%2\;st %5,%1" - [(set_attr "type" "weird") - (set_attr "length" "2,2,4,4")]) - -;; Special insn to serve as the last insn of a define_expand. This insn -;; will generate no code. - -(define_expand "dummy" - [(set (match_operand 0 "" "") (match_dup 0))] - "" - "") diff --git a/gcc/config/m88k/openbsd.h b/gcc/config/m88k/openbsd.h deleted file mode 100644 index 56891e8f083..00000000000 --- a/gcc/config/m88k/openbsd.h +++ /dev/null @@ -1,67 +0,0 @@ -/* Configuration file for an m88k OpenBSD target. - Copyright (C) 2000 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* Identify the compiler. */ -#undef VERSION_INFO1 -#define VERSION_INFO1 "Motorola m88k, " - -/* Macros to be automatically defined. */ -#define CPP_PREDEFINES \ - "-D__m88k__ -D__unix__ -D__OpenBSD__ -D__CLASSIFY_TYPE__=2 -Asystem=unix -Asystem=OpenBSD -Acpu=m88k -Amachine=m88k" - -/* If -m88000 is in effect, add -Dmc88000; similarly for -m88100 and -m88110. - However, reproduce the effect of -Dmc88100 previously in CPP_PREDEFINES. - Here, the CPU_DEFAULT is assumed to be -m88100. */ -#undef CPP_SPEC -#define CPP_SPEC "%{m88000:-D__mc88000__} \ - %{!m88000:%{m88100:%{m88110:-D__mc88000__}}} \ - %{!m88000:%{!m88100:%{m88110:-D__mc88110__}}} \ - %{!m88000:%{!m88110:-D__mc88100__ -D__mc88100}} \ - %{posix:-D_POSIX_SOURCE} \ - %{pthread:-D_POSIX_THREADS}" - -/* Layout of source language data types. */ - -/* This must agree with <machine/ansi.h> */ -#undef SIZE_TYPE -#define SIZE_TYPE "unsigned int" - -#undef PTRDIFF_TYPE -#define PTRDIFF_TYPE "int" - -#undef WCHAR_TYPE -#define WCHAR_TYPE "int" - -#undef WCHAR_TYPE_SIZE -#define WCHAR_TYPE_SIZE 32 - -/* Every structure or union's size must be a multiple of 2 bytes. */ -#undef STRUCTURE_SIZE_BOUNDARY -#define STRUCTURE_SIZE_BOUNDARY 16 - -/* Stack & calling: aggregate returns. */ - -/* Don't default to pcc-struct-return, because gcc is the only compiler, and - we want to retain compatibility with older gcc versions. */ -#define DEFAULT_PCC_STRUCT_RETURN 0 - -#undef SET_ASM_OP -#define SET_ASM_OP "\t.def\t" - diff --git a/gcc/config/m88k/sysv4.h b/gcc/config/m88k/sysv4.h deleted file mode 100644 index 64695d1b726..00000000000 --- a/gcc/config/m88k/sysv4.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Definitions of target machine for GNU compiler. - Motorola 88100 in an 88open ABI environment. - Copyright (C) 1990, 1991, 2000, 2001 Free Software Foundation, Inc. - - Written by Ron Guilmette (rfg@netcom.com). - Contributed to FSF by Network Computing Devices. - - Other contributions by Vince Guarna (vguarna@urbana.mcd.mot.com), - Ray Essick (essick@i88.isc.com), Wilson Tien (wtien@urbana.mcd.mot.com), - and Tom Wood (Tom_Wood@NeXT.com) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* DWARF_DEBUGGING_INFO defined in svr4.h. */ - -#ifndef NO_BUGS -#define AS_BUG_DOT_LABELS -#define AS_BUG_POUND_TYPE -#endif - -/* TODO: convert includes to ${tm_file} list in config.gcc. */ -#include "m88k/m88k.h" - -/* Identify the compiler. */ -#undef VERSION_INFO1 -#define VERSION_INFO1 "88open ABI" - -/* Default switches */ -#undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_CHECK_ZERO_DIV | \ - MASK_OCS_DEBUG_INFO | \ - MASK_SVR4) - -/* Cpp spec. These pre-assertions are needed for SVR4 as they occur - often in the system header files. __svr4__ is our extension. */ - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES \ - "-Dm88000 -Dm88k -Dunix -D__svr4__ -Amachine=m88k -Acpu=m88k -Asystem=unix -Asystem=svr4" - -/* For the AT&T SVR4 port, the function is _mcount. */ -#undef FUNCTION_PROFILER -#define FUNCTION_PROFILER(FILE, LABELNO) \ - output_function_profiler (FILE, LABELNO, "_mcount", 1) - -/* Override svr4.h and m88k.h. */ -#undef INIT_SECTION_ASM_OP -#define INIT_SECTION_ASM_OP "\tsection\t.init,\"xa\",#progbits" -#undef FINI_SECTION_ASM_OP -#define FINI_SECTION_ASM_OP "\tsection\t.fini,\"xa\",#progbits" - -/* Define the pseudo-ops used to switch to the .ctors and .dtors sections. - - Note that we want to give these sections the SHF_WRITE attribute - because these sections will actually contain data (i.e. tables of - addresses of functions in the current root executable or shared library - file) and, in the case of a shared library, the relocatable addresses - will have to be properly resolved/relocated (and then written into) by - the dynamic linker when it actually attaches the given shared library - to the executing process. (Note that on SVR4, you may wish to use the - `-z text' option to the ELF linker, when building a shared library, as - an additional check that you are doing everything right. But if you do - use the `-z text' option when building a shared library, you will get - errors unless the .ctors and .dtors sections are marked as writable - via the SHF_WRITE attribute.) */ - -#undef CTORS_SECTION_ASM_OP -#define CTORS_SECTION_ASM_OP "\tsection\t.ctors,\"aw\"" -#undef DTORS_SECTION_ASM_OP -#define DTORS_SECTION_ASM_OP "\tsection\t.dtors,\"aw\"" diff --git a/gcc/config/m88k/t-luna b/gcc/config/m88k/t-luna deleted file mode 100644 index ddbfa73da12..00000000000 --- a/gcc/config/m88k/t-luna +++ /dev/null @@ -1,10 +0,0 @@ -# Specify how to create the *.asm files - -MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ - moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ - moveDI96x.asm - -$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh - $(srcdir)/config/m88k/m88k-move.sh -no-tdesc - -LIB2FUNCS_EXTRA = $(MOVE_ASM) diff --git a/gcc/config/m88k/t-luna-gas b/gcc/config/m88k/t-luna-gas deleted file mode 100644 index 2b2d72784be..00000000000 --- a/gcc/config/m88k/t-luna-gas +++ /dev/null @@ -1,11 +0,0 @@ -# Specify how to create the *.asm files - -MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ - moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ - moveDI96x.asm - -$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh - $(SHELL) $(srcdir)/config/m88k/m88k-move.sh -no-tdesc - -LIB2FUNCS_EXTRA = $(MOVE_ASM) -T_CPPFLAGS = -DUSE_GAS diff --git a/gcc/config/m88k/t-m88k b/gcc/config/m88k/t-m88k deleted file mode 100644 index c4406233d97..00000000000 --- a/gcc/config/m88k/t-m88k +++ /dev/null @@ -1,10 +0,0 @@ -# Specify how to create the *.asm files - -MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ - moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ - moveDI96x.asm - -$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh - $(srcdir)/config/m88k/m88k-move.sh - -LIB2FUNCS_EXTRA = $(MOVE_ASM) diff --git a/gcc/config/m88k/t-sysv4 b/gcc/config/m88k/t-sysv4 deleted file mode 100644 index 858fdc0476e..00000000000 --- a/gcc/config/m88k/t-sysv4 +++ /dev/null @@ -1,20 +0,0 @@ -# Specify how to create the *.asm files - -MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ - moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ - moveDI96x.asm - -# Use the -abi option for version 03.00 syntax. - -$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh - $(srcdir)/config/m88k/m88k-move.sh -abi - -LIB2FUNCS_EXTRA = $(MOVE_ASM) - -# We need to use -fPIC when we are using gcc to compile the routines in -# crtstuff.c. This is only really needed when we are going to use gcc/g++ -# to produce a shared library, but since we don't know ahead of time when -# we will be doing that, we just always use -fPIC when compiling the -# routines in crtstuff.c. - -CRTSTUFF_T_CFLAGS=-fPIC diff --git a/gcc/config/mcore/gfloat.h b/gcc/config/mcore/gfloat.h deleted file mode 100644 index b64dd75417e..00000000000 --- a/gcc/config/mcore/gfloat.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Output routines for Motorola MCore processor - Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* float.h for the M*Core microprocessor. It uses IEEE floating point. - * float is 32 bit IEEE-754 format - * double is 64 bit IEEE-754 format - * long double is not defined right now... - */ -#ifndef __FLOAT_H___ -#define __FLOAT_H___ - -#define FLT_RADIX 2 -#define FLT_ROUNDS 1 - -#define FLT_MANT_DIG 24 -#define FLT_DIG 6 -#define FLT_EPSILON ((float)1.19209290e-07) -#define FLT_MIN_EXP (-125) -#define FLT_MIN ((float)1.17549435e-38) -#define FLT_MIN_10_EXP (-37) -#define FLT_MAX_EXP 128 -#define FLT_MAX ((float)3.40282347e+38) -#define FLT_MAX_10_EXP 38 - -#define DBL_MANT_DIG 53 -#define DBL_DIG 15 -#define DBL_EPSILON 2.2204460492503131e-16 -#define DBL_MIN_EXP (-1021) -#define DBL_MIN 2.2250738585072014e-308 -#define DBL_MIN_10_EXP (-307) -#define DBL_MAX_EXP 1024 -#define DBL_MAX 1.7976931348623157e+308 -#define DBL_MAX_10_EXP 308 - - -/* No definitions for LDBL at this time. */ - -#undef LDBL_MANT_DIG -#undef LDBL_DIG -#undef LDBL_EPSILON -#undef LDBL_MIN_EXP -#undef LDBL_MIN -#undef LDBL_MIN_10_EXP -#undef LDBL_MAX_EXP -#undef LDBL_MAX -#undef LDBL_MAX_10_EXP - -#endif /* __FLOAT_H__ */ diff --git a/gcc/config/mips/rtems64.h b/gcc/config/mips/rtems64.h deleted file mode 100644 index bd9535658d1..00000000000 --- a/gcc/config/mips/rtems64.h +++ /dev/null @@ -1,37 +0,0 @@ -/* Definitions for rtems targeting a MIPS ORION using ecoff. - Copyright (C) 1996, 1997, 1998, 1999, 2000, 2002 Free Software Foundation, Inc. - Contributed by Joel Sherrill (joel@OARcorp.com). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* Specify predefined symbols in preprocessor. */ -#define TARGET_OS_CPP_BUILTINS() \ -do { \ - builtin_define ("__rtems__"); \ - builtin_assert ("system=rtems"); \ -} while (0) - -#undef EXTRA_SECTIONS -#define EXTRA_SECTIONS in_sdata - -#undef EXTRA_SECTION_FUNCTIONS -#define EXTRA_SECTION_FUNCTIONS \ - SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) - -#undef STARTFILE_SPEC -#undef ENDFILE_SPEC diff --git a/gcc/config/mips/sni-gas.h b/gcc/config/mips/sni-gas.h deleted file mode 100644 index 5515bfd3c39..00000000000 --- a/gcc/config/mips/sni-gas.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Enable debugging. */ -#define DBX_DEBUGGING_INFO 1 -#define SDB_DEBUGGING_INFO 1 -#define MIPS_DEBUGGING_INFO 1 -#define DWARF_DEBUGGING_INFO 1 - -#undef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG - -/* We need to use .esize and .etype instead of .size and .type to - avoid conflicting with ELF directives. These are only recognized - by gas, anyhow, not the native assembler. */ -#undef PUT_SDB_SIZE -#define PUT_SDB_SIZE(a) \ -do { \ - extern FILE *asm_out_text_file; \ - fprintf (asm_out_text_file, "\t.esize\t"); \ - fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) (a)); \ - fprintf (asm_out_text_file, ";"); \ -} while (0) - -#undef PUT_SDB_TYPE -#define PUT_SDB_TYPE(a) \ -do { \ - extern FILE *asm_out_text_file; \ - fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a)); \ -} while (0) - - -/* This is how to equate one symbol to another symbol. The syntax used is - `SYM1=SYM2'. Note that this is different from the way equates are done - with most svr4 assemblers, where the syntax is `.set SYM1,SYM2'. */ - -#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ - do { fprintf ((FILE), "\t"); \ - assemble_name (FILE, LABEL1); \ - fprintf (FILE, " = "); \ - assemble_name (FILE, LABEL2); \ - fprintf (FILE, "\n"); \ - } while (0) diff --git a/gcc/config/mips/sni-svr4.h b/gcc/config/mips/sni-svr4.h deleted file mode 100644 index f912759a16b..00000000000 --- a/gcc/config/mips/sni-svr4.h +++ /dev/null @@ -1,88 +0,0 @@ -/* Definitions of target machine for GNU compiler. SNI SINIX version. - Copyright (C) 1996, 1997, 1999, 2000, 2002 Free Software Foundation, Inc. - Contributed by Marco Walther (Marco.Walther@mch.sni.de). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#define MIPS_SVR4 - -#define TARGET_OS_CPP_BUILTINS() \ - do { \ - builtin_define_std ("host_mips"); \ - builtin_define_std ("SYSTYPE_SVR4"); \ - builtin_define_std ("unix"); \ - builtin_define_std ("mips"); \ - builtin_define_std ("sinix"); \ - builtin_define_std ("SNI"); \ - builtin_assert ("system=unix"); \ - builtin_assert ("system=svr4"); \ - builtin_assert ("machine=mips"); \ -} while (0) - -#define LINK_SPEC "\ -%{G*} \ -%{!mgas: \ - %{dy} %{dn}}" - -#define LIB_SPEC "\ - %{p:-lprof1} \ - %{!p:%{pg:-lprof1} \ - %{!pg:-L/usr/ccs/lib/ -lc /usr/ccs/lib/crtn.o%s}}" - -#define STARTFILE_SPEC "\ - %{pg:gcrt0.o%s} \ - %{!pg:%{p:mcrt0.o%s} \ - %{!p:/usr/ccs/lib/crt1.o /usr/ccs/lib/crti.o /usr/ccs/lib/values-Xt.o%s}}" - -/* Mips System V.4 doesn't have a getpagesize() function needed by the - trampoline code, so use the POSIX sysconf function to get it. - This is only done when compiling the trampoline code. */ - -#ifdef L_trampoline -#include <unistd.h> - -#define getpagesize() sysconf(_SC_PAGE_SIZE) -#endif /* L_trampoline */ - -#define OBJECT_FORMAT_ELF - -#define TARGET_DEFAULT MASK_ABICALLS -#define ABICALLS_ASM_OP "\t.option pic2" - -#define MACHINE_TYPE "SNI running SINIX 5.42" - -#define MIPS_DEFAULT_GVALUE 0 - -#define NM_FLAGS "-p" - -#define ASM_GLOBAL ".rdata\n\t\t.globl\t" - -#include "mips/mips.h" - -/* We do not want to run mips-tfile! */ -#undef ASM_FINAL_SPEC - -#undef OBJECT_FORMAT_COFF - -/* We don't support debugging info for now. */ -#undef DBX_DEBUGGING_INFO -#undef SDB_DEBUGGING_INFO -#undef MIPS_DEBUGGING_INFO -#undef PREFERRED_DEBUGGING_TYPE - -#define DWARF2_UNWIND_INFO 0 diff --git a/gcc/config/mips/t-ecoff b/gcc/config/mips/t-ecoff deleted file mode 100644 index f5e3805375d..00000000000 --- a/gcc/config/mips/t-ecoff +++ /dev/null @@ -1,59 +0,0 @@ -LIB1ASMSRC = mips/mips16.S -LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \ - _m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \ - _m16fltsisf _m16fixsfsi \ - _m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \ - _m16extsfdf2 _m16trdfsf2 \ - _m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \ - _m16fltsidf _m16fixdfsi \ - _m16retsf _m16retdf \ - _m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \ - _m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \ - _m16stubsf9 _m16stubsf10 \ - _m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \ - _m16stubdf9 _m16stubdf10 - -# We must build libgcc2.a with -G 0, in case the user wants to link -# without the $gp register. -TARGET_LIBGCC2_CFLAGS = -G 0 - -# Build the libraries for both hard and soft floating point - -MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3 -MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3 -MULTILIB_MATCHES = EL=mel EB=meb -MULTILIB_MATCHES = msingle-float=m4650 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib - -# Add additional dependencies to recompile selected modules whenever the -# tm.h file changes. The files compiled are: -# -# gcc.c (*_SPEC changes) -# toplev.c (new switches + assembly output changes) -# sdbout.c (debug format changes) -# dbxout.c (debug format changes) -# dwarfout.c (debug format changes) -# final.c (assembly output changes) -# varasm.c (assembly output changes) -# cse.c (cost functions) -# insn-output.c (possible ifdef changes in tm.h) -# regclass.c (fixed/call used register changes) -# explow.c (GO_IF_LEGITIMATE_ADDRESS) -# recog.c (GO_IF_LEGITIMATE_ADDRESS) -# reload.c (GO_IF_LEGITIMATE_ADDRESS) - -gcc.o: $(CONFIG2_H) -toplev.o: $(CONFIG2_H) -sdbout.o: $(CONFIG2_H) -dbxout.o: $(CONFIG2_H) -dwarfout.o: $(CONFIG2_H) -final.o: $(CONFIG2_H) -varasm.o: $(CONFIG2_H) -cse.o: $(CONFIG2_H) -insn-output.o: $(CONFIG2_H) -regclass.o: $(CONFIG2_H) -explow.o: $(CONFIG2_H) -recog.o: $(CONFIG2_H) -reload.o: $(CONFIG2_H) diff --git a/gcc/config/mn10200/lib1funcs.asm b/gcc/config/mn10200/lib1funcs.asm deleted file mode 100644 index 90ae1beba80..00000000000 --- a/gcc/config/mn10200/lib1funcs.asm +++ /dev/null @@ -1,604 +0,0 @@ -/* libgcc routines for Matsushita mn10200. - Copyright (C) 1997 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by the -Free Software Foundation; either version 2, or (at your option) any -later version. - -In addition to the permissions in the GNU General Public License, the -Free Software Foundation gives you unlimited permission to link the -compiled version of this file into combinations with other programs, -and to distribute those combinations without any restriction coming -from the use of this file. (The General Public License restrictions -do apply in other respects; for example, they cover modification of -the file, and distribution when not linked into a combine -executable.) - -This file is distributed in the hope that it will be useful, but -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifdef L_divhi3 - /* Derive signed division/modulo from unsigned "divu" instruction. */ - .text - .globl ___divhi3 - .type ___divhi3,@function -___divhi3: - - /* We're going to need some scratch registers, so save d2/d3 - into the stack. */ - add -8,a3 - movx d2,(0,a3) - movx d3,(4,a3) - - /* Loading zeros into registers now allows us to use them - in the compare instructions, which saves a total of - two bytes (egad). */ - sub d3,d3 - sub d2,d2 - sub a0,a0 - - /* If first operand is negative, then make it positive. - It will be contained in d2 just before .L1. - - a0 tells us if the first operand was negated. */ - cmp d2,d0 - bge .L0 - sub d0,d2 - mov 1,a0 - bra .L1 -.L0: - mov d0,d2 -.L1: - /* If the second operand is negative, then make it positive. - It will be contained in d3 just before .L3. - - d0 tells us if the second operand was negated. */ - cmp d3,d1 - bge .L2 - sub d1,d3 - mov 1,d0 - bra .L3 -.L2: - sub d0,d0 - mov d1,d3 -.L3: - /* Loading d1 with zero here allows us to save one byte - in the comparison below. */ - - sub d1,d1 - - /* Make sure to clear the mdr register, then do the unsigned - division. Result will be in d2/mdr. */ - mov d1,mdr - divu d3,d2 - - /* Negate the remainder based on the first argument negation - flag only. */ - cmp d1,a0 - beq .L4 - mov mdr,d3 - sub d3,d1 - bra .L5 -.L4: - mov mdr,d1 - -.L5: - /* Negate the result if either, but not both of the inputs - were negated. */ - mov a0,d3 - xor d3,d0 - beq .L6 - sub d0,d0 - sub d2,d0 - bra .L7 -.L6: - mov d2,d0 -.L7: - - /* Restore our scratch registers, deallocate our stack and return. */ - movx (0,a3),d2 - movx (4,a3),d3 - add 8,a3 - rts - .size ___divhi3,.-___divhi3 -#endif - -#ifdef L_modhi3 - .text - .globl ___modhi3 - .type ___modhi3,@function -___modhi3: - jsr ___divhi3 - mov d1,d0 - rts - .size ___modhi3,.-___modhi3 -#endif - -#ifdef L_addsi3 - .text - .globl ___addsi3 - .type ___addsi3,@function -___addsi3: - add -4,a3 - movx d2,(0,a3) - mov (8,a3),d2 - add d2,d0 - mov (10,a3),d2 - addc d2,d1 - movx (0,a3),d2 - add 4,a3 - rts - - .size ___addsi3,.-___addsi3 -#endif - -#ifdef L_subsi3 - .text - .globl ___subsi3 - .type ___subsi3,@function -___subsi3: - add -4,a3 - movx d2,(0,a3) - mov (8,a3),d2 - sub d2,d0 - mov (10,a3),d2 - subc d2,d1 - movx (0,a3),d2 - add 4,a3 - rts - - .size ___subsi3,.-___subsi3 -#endif - -#ifdef L_mulsi3 - .text - .globl ___mulsi3 - .type ___mulsi3,@function -___mulsi3: - add -4,a3 - mov a1,(0,a3) - mov d0,a0 - /* Multiply arg0 msb with arg1 lsb. - arg0 msb is in register d1, - arg1 lsb is in memory. */ - mov (8,a3),d0 - mulu d0,d1 - mov d1,a1 - - /* Multiply arg0 lsb with arg1 msb. - arg0 msb is in register a0, - arg1 lsb is in memory. */ - mov a0,d0 - mov (10,a3),d1 - mulu d0,d1 - - /* Add the cross products. */ - add d1,a1 - - /* Now multiply arg0 lsb with arg1 lsb. */ - mov (8,a3),d1 - mulu d1,d0 - - /* Add in the upper 16 bits to the cross product sum. */ - mov mdr,d1 - add a1,d1 - mov (0,a3),a1 - add 4,a3 - rts - - .size ___mulsi3,.-___mulsi3 -#endif - -#ifdef L_ashlsi3 - .text - .globl ___ashlsi3 - .type ___ashlsi3,@function -___ashlsi3: - mov (4,a3),a0 - cmp 0,a0 - beq .L0 -.L1: - add d0,d0 - addc d1,d1 - add -1,a0 - bne .L1 -.L0: - rts - - .size ___ashlsi3,.-___ashlsi3 -#endif - -#ifdef L_lshrsi3 - .text - .globl ___lshrsi3 - .type ___lshrsi3,@function -___lshrsi3: - mov (4,a3),a0 - cmp 0,a0 - beq .L0 -.L1: - lsr d1 - ror d0 - add -1,a0 - bne .L1 -.L0: - rts - - .size ___lshrsi3,.-___lshrsi3 -#endif - -#ifdef L_ashrsi3 - .text - .globl ___ashrsi3 - .type ___ashrsi3,@function -___ashrsi3: - mov (4,a3),a0 - cmp 0,a0 - beq .L0 -.L1: - asr d1 - ror d0 - add -1,a0 - bne .L1 -.L0: - rts - - .size ___ashrsi3,.-___ashrsi3 -#endif - -/* All functions beyond this point pass their arguments in registers! */ -#ifdef L_negsi2_d0 - .text - .globl ___negsi2_d0 - .type ___negsi2_d0,@function -___negsi2_d0: - add -8,a3 - movx d3,(0,a3) - movx d2,(4,a3) - mov d0,d2 - mov d1,d3 - sub d0,d0 - sub d1,d1 - sub d2,d0 - subc d3,d1 - movx (0,a3),d3 - movx (4,a3),d2 - add 8,a3 - rts - - .size ___negsi2_d0,.-___negsi2_d0 -#endif - -#ifdef L_negsi2_d2 - .text - .globl ___negsi2_d2 - .type ___negsi2_d2,@function -___negsi2_d2: - add -8,a3 - movx d1,(0,a3) - movx d0,(4,a3) - mov d2,d0 - mov d3,d1 - sub d2,d2 - sub d3,d3 - sub d0,d2 - subc d1,d3 - movx (0,a3),d1 - movx (4,a3),d0 - add 8,a3 - rts - - .size ___negsi2_d2,.-___negsi2_d2 -#endif - -#ifdef L_zero_extendpsisi2_d0 - .text - .globl ___zero_extendpsisi2_d0 - .type ___zero_extendpsisi2_d0,@function -___zero_extendpsisi2_d0: - add -4,a3 - movx d0,(0,a3) - movbu (2,a3),d1 - add 4,a3 - rts - - .size ___zero_extendpsisi2_d0,.-___zero_extendpsisi2_d0 -#endif - -#ifdef L_zero_extendpsisi2_d2 - .text - .globl ___zero_extendpsisi2_d2 - .type ___zero_extendpsisi2_d2,@function -___zero_extendpsisi2_d2: - add -4,a3 - movx d2,(0,a3) - movbu (2,a3),d3 - add 4,a3 - rts - - .size ___zero_extendpsisi2_d2,.-___zero_extendpsisi2_d2 -#endif - -#ifdef L_sign_extendpsisi2_d0 - .text - .globl ___sign_extendpsisi2_d0 - .type ___sign_extendpsisi2_d0,@function -___sign_extendpsisi2_d0: - add -4,a3 - movx d0,(0,a3) - movb (2,a3),d1 - add 4,a3 - rts - - .size ___sign_extendpsisi2_d0,.-___sign_extendpsisi2_d0 -#endif - -#ifdef L_sign_extendpsisi2_d2 - .text - .globl ___sign_extendpsisi2_d2 - .type ___sign_extendpsisi2_d2,@function -___sign_extendpsisi2_d2: - add -4,a3 - movx d2,(0,a3) - movb (2,a3),d3 - add 4,a3 - rts - - .size ___sign_extendpsisi2_d2,.-___sign_extendpsisi2_d2 -#endif - -#ifdef L_truncsipsi2_d0_d0 - .text - .globl ___truncsipsi2_d0_d0 - .type ___truncsipsi2_d0_d0,@function -___truncsipsi2_d0_d0: - add -4,a3 - mov d0,(a3) - mov d1,(2,a3) - movx (0,a3),d0 - add 4,a3 - rts - - .size ___truncsipsi2_d0_d0,.-___truncsipsi2_d0_d0 -#endif - -#ifdef L_truncsipsi2_d0_d1 - .text - .globl ___truncsipsi2_d0_d1 - .type ___truncsipsi2_d0_d1,@function -___truncsipsi2_d0_d1: - add -4,a3 - mov d0,(a3) - mov d1,(2,a3) - movx (0,a3),d1 - add 4,a3 - rts - - .size ___truncsipsi2_d0_d1,.-___truncsipsi2_d0_d1 -#endif - -#ifdef L_truncsipsi2_d0_d2 - .text - .globl ___truncsipsi2_d0_d2 - .type ___truncsipsi2_d0_d2,@function -___truncsipsi2_d0_d2: - add -4,a3 - mov d0,(a3) - mov d1,(2,a3) - movx (0,a3),d2 - add 4,a3 - rts - - .size ___truncsipsi2_d0_d2,.-___truncsipsi2_d0_d2 -#endif - -#ifdef L_truncsipsi2_d0_d3 - .text - .globl ___truncsipsi2_d0_d3 - .type ___truncsipsi2_d0_d3,@function -___truncsipsi2_d0_d3: - add -4,a3 - mov d0,(a3) - mov d1,(2,a3) - movx (0,a3),d3 - add 4,a3 - rts - - .size ___truncsipsi2_d0_d3,.-___truncsipsi2_d0_d3 -#endif - -#ifdef L_truncsipsi2_d2_d0 - .text - .globl ___truncsipsi2_d2_d0 - .type ___truncsipsi2_d2_d0,@function -___truncsipsi2_d2_d0: - add -4,a3 - mov d2,(a3) - mov d3,(2,a3) - movx (0,a3),d0 - add 4,a3 - rts - - .size ___truncsipsi2_d2_d0,.-___truncsipsi2_d2_d0 -#endif - -#ifdef L_truncsipsi2_d2_d1 - .text - .globl ___truncsipsi2_d2_d1 - .type ___truncsipsi2_d2_d1,@function -___truncsipsi2_d2_d1: - add -4,a3 - mov d2,(a3) - mov d3,(2,a3) - movx (0,a3),d1 - add 4,a3 - rts - - .size ___truncsipsi2_d2_d1,.-___truncsipsi2_d2_d1 -#endif - -#ifdef L_truncsipsi2_d2_d2 - .text - .globl ___truncsipsi2_d2_d2 - .type ___truncsipsi2_d2_d2,@function -___truncsipsi2_d2_d2: - add -4,a3 - mov d2,(a3) - mov d3,(2,a3) - movx (0,a3),d2 - add 4,a3 - rts - - .size ___truncsipsi2_d2_d2,.-___truncsipsi2_d2_d2 -#endif - -#ifdef L_truncsipsi2_d2_d3 - .text - .globl ___truncsipsi2_d2_d3 - .type ___truncsipsi2_d2_d3,@function -___truncsipsi2_d2_d3: - add -4,a3 - mov d2,(a3) - mov d3,(2,a3) - movx (0,a3),d3 - add 4,a3 - rts - - .size ___truncsipsi2_d2_d3,.-___truncsipsi2_d2_d3 -#endif - - -#ifdef L_cmpsi2 - .text - .globl ___cmpsi2 - .type ___cmpsi2,@function -___cmpsi2: - add -4,a3 - mov a1,(0,a3) - mov (10,a3),a1 - mov (8,a3),a0 - cmp a1,d1 - blt .L9 - bgt .L6 - cmp a0,d0 - bcc .L5 -.L9: - sub d0,d0 - jmp .L8 -.L5: - cmp a0,d0 - bhi .L6 - mov 1,d0 - jmp .L8 -.L6: - mov 2,d0 -.L8: - mov (0,a3),a1 - add 4,a3 - rts - .size ___cmpsi2,.-___cmpsi2 -#endif - -#ifdef L_ucmpsi2 - .text - .globl ___ucmpsi2 - .type ___ucmpsi2,@function -___ucmpsi2: - add -4,a3 - mov a1,(0,a3) - mov (10,a3),a1 - mov (8,a3),a0 - cmp a1,d1 - bcs .L9 - bhi .L6 - cmp a0,d0 - bcc .L5 -.L9: - sub d0,d0 - jmp .L8 -.L5: - cmp a0,d0 - bhi .L6 - mov 1,d0 - jmp .L8 -.L6: - mov 2,d0 -.L8: - mov (0,a3),a1 - add 4,a3 - rts - .size ___ucmpsi2,.-___ucmpsi2 -#endif - - -#ifdef L_prologue - .text - .globl ___prologue - .type ___prologue,@function -___prologue: - mov (0,a3),a0 - add -16,a3 - movx d2,(4,a3) - movx d3,(8,a3) - mov a1,(12,a3) - mov a2,(16,a3) - mov a0,(0,a3) - rts - .size ___prologue,.-___prologue -#endif - -#ifdef L_epilogue_a0 - .text - .globl ___epilogue_a0 - .type ___epilogue_a0,@function -___epilogue_a0: - mov (0,a3),a0 - movx (4,a3),d2 - movx (8,a3),d3 - mov (12,a3),a1 - mov (16,a3),a2 - add 16,a3 - mov a0,(0,a3) - rts - .size ___epilogue_a0,.-___epilogue_a0 -#endif - -#ifdef L_epilogue_d0 - .text - .globl ___epilogue_d0 - .type ___epilogue_d0,@function -___epilogue_d0: - movx (0,a3),d0 - movx (4,a3),d2 - movx (8,a3),d3 - mov (12,a3),a1 - mov (16,a3),a2 - add 16,a3 - movx d0,(0,a3) - rts - .size ___epilogue_d0,.-___epilogue_d0 -#endif - -#ifdef L_epilogue_noreturn - .text - .globl ___epilogue_noreturn - .type ___epilogue_noreturn,@function -___epilogue_noreturn: - movx (0,a3),d2 - movx (4,a3),d3 - mov (8,a3),a1 - mov (12,a3),a2 - add 16,a3 - rts - .size ___epilogue_noreturn,.-___epilogue_noreturn -#endif diff --git a/gcc/config/mn10200/mn10200-protos.h b/gcc/config/mn10200/mn10200-protos.h deleted file mode 100644 index 4f82d61fd38..00000000000 --- a/gcc/config/mn10200/mn10200-protos.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Definitions of target machine for GNU compiler. Matsushita MN10200 series - Copyright (C) 2000 Free Software Foundation, Inc. - Contributed by Jeff Law (law@cygnus.com). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifdef RTX_CODE -extern void print_operand PARAMS ((FILE *, rtx, int)); -extern void print_operand_address PARAMS ((FILE *, rtx)); -extern void notice_update_cc PARAMS ((rtx, rtx)); -extern enum reg_class secondary_reload_class PARAMS ((enum reg_class, - enum machine_mode, - rtx, int)); -extern const char *emit_a_shift PARAMS ((rtx, rtx *)); -extern const char *output_tst PARAMS ((rtx, rtx)); -extern int expand_a_shift PARAMS ((enum machine_mode, int, rtx[])); - -extern int call_address_operand PARAMS ((rtx, enum machine_mode)); -extern int extendpsi_operand PARAMS ((rtx, enum machine_mode)); -extern int psimode_truncation_operand PARAMS ((rtx, enum machine_mode)); -extern int constant_memory_operand PARAMS ((rtx, enum machine_mode)); -extern int nshift_operator PARAMS ((rtx, enum machine_mode)); -#endif /* RTX_CODE */ - -#ifdef TREE_CODE -extern struct rtx_def *function_arg PARAMS ((CUMULATIVE_ARGS *, - enum machine_mode, tree, int)); -extern struct rtx_def *mn10200_va_arg PARAMS ((tree, tree)); -extern int function_arg_partial_nregs PARAMS ((CUMULATIVE_ARGS *, - enum machine_mode, tree, int)); -#endif /* TREE_CODE */ - -extern void asm_file_start PARAMS ((FILE *)); -extern void expand_prologue PARAMS ((void)); -extern void expand_epilogue PARAMS ((void)); -extern int total_frame_size PARAMS ((void)); diff --git a/gcc/config/mn10200/mn10200.c b/gcc/config/mn10200/mn10200.c deleted file mode 100644 index 4116c016e55..00000000000 --- a/gcc/config/mn10200/mn10200.c +++ /dev/null @@ -1,1662 +0,0 @@ -/* Subroutines for insn-output.c for Matsushita MN10200 series - Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 - Free Software Foundation, Inc. - Contributed by Jeff Law (law@cygnus.com). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#include "config.h" -#include "system.h" -#include "coretypes.h" -#include "tm.h" -#include "rtl.h" -#include "tree.h" -#include "regs.h" -#include "hard-reg-set.h" -#include "real.h" -#include "insn-config.h" -#include "conditions.h" -#include "output.h" -#include "insn-attr.h" -#include "flags.h" -#include "recog.h" -#include "expr.h" -#include "function.h" -#include "obstack.h" -#include "ggc.h" -#include "toplev.h" -#include "tm_p.h" -#include "target.h" -#include "target-def.h" - -/* Global registers known to hold the value zero. - - Normally we'd depend on CSE and combine to put zero into a - register and re-use it. - - However, on the mn10x00 processors we implicitly use the constant - zero in tst instructions, so we might be able to do better by - loading the value into a register in the prologue, then re-useing - that register throughout the function. - - We could perform similar optimizations for other constants, but with - gcse due soon, it doesn't seem worth the effort. - - These variables hold a rtx for a register known to hold the value - zero throughout the entire function, or NULL if no register of - the appropriate class has such a value throughout the life of the - function. */ -rtx zero_dreg; -rtx zero_areg; - -static void count_tst_insns PARAMS ((int *)); -static bool mn10200_rtx_costs PARAMS ((rtx, int, int, int *)); - -/* Note whether or not we need an out of line epilogue. */ -static int out_of_line_epilogue; - -/* Initialize the GCC target structure. */ -#undef TARGET_ASM_ALIGNED_HI_OP -#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" - -#undef TARGET_RTX_COSTS -#define TARGET_RTX_COSTS mn10200_rtx_costs - -struct gcc_target targetm = TARGET_INITIALIZER; - -/* Indicate this file was compiled by gcc and what optimization - level was used. */ -void -asm_file_start (file) - FILE *file; -{ - fprintf (file, "#\tGCC For the Matsushita MN10200\n"); - if (optimize) - fprintf (file, "# -O%d\n", optimize); - else - fprintf (file, "\n\n"); - output_file_directive (file, main_input_filename); -} - -/* Print operand X using operand code CODE to assembly language output file - FILE. */ - -void -print_operand (file, x, code) - FILE *file; - rtx x; - int code; -{ - switch (code) - { - case 'b': - case 'B': - /* These are normal and reversed branches. */ - switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) - { - case NE: - fprintf (file, "ne"); - break; - case EQ: - fprintf (file, "eq"); - break; - case GE: - fprintf (file, "ge"); - break; - case GT: - fprintf (file, "gt"); - break; - case LE: - fprintf (file, "le"); - break; - case LT: - fprintf (file, "lt"); - break; - case GEU: - fprintf (file, "cc"); - break; - case GTU: - fprintf (file, "hi"); - break; - case LEU: - fprintf (file, "ls"); - break; - case LTU: - fprintf (file, "cs"); - break; - default: - abort (); - } - break; - case 'C': - /* This is used for the operand to a call instruction; - if it's a REG, enclose it in parens, else output - the operand normally. */ - if (GET_CODE (x) == REG) - { - fputc ('(', file); - print_operand (file, x, 0); - fputc (')', file); - } - else - print_operand (file, x, 0); - break; - - /* These are the least significant word in a 32bit value. - 'o' allows us to sign extend a constant if doing so - makes for more compact code. */ - case 'L': - case 'o': - switch (GET_CODE (x)) - { - case MEM: - fputc ('(', file); - output_address (XEXP (x, 0)); - fputc (')', file); - break; - - case REG: - fprintf (file, "%s", reg_names[REGNO (x)]); - break; - - case SUBREG: - fprintf (file, "%s", reg_names[subreg_regno (x)]); - break; - - case CONST_DOUBLE: - if (code == 'L') - { - long val; - REAL_VALUE_TYPE rv; - - REAL_VALUE_FROM_CONST_DOUBLE (rv, x); - REAL_VALUE_TO_TARGET_SINGLE (rv, val); - print_operand_address (file, GEN_INT (val & 0xffff)); - } - else - { - long val; - REAL_VALUE_TYPE rv; - - REAL_VALUE_FROM_CONST_DOUBLE (rv, x); - REAL_VALUE_TO_TARGET_SINGLE (rv, val); - - val &= 0xffff; - val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000; - print_operand_address (file, GEN_INT (val)); - } - break; - - case CONST_INT: - if (code == 'L') - print_operand_address (file, GEN_INT ((INTVAL (x) & 0xffff))); - else - { - unsigned int val = INTVAL (x) & 0xffff; - val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000; - print_operand_address (file, GEN_INT (val)); - } - break; - default: - abort (); - } - break; - - /* Similarly, but for the most significant word. */ - case 'H': - case 'h': - switch (GET_CODE (x)) - { - case MEM: - fputc ('(', file); - x = adjust_address (x, HImode, 2); - output_address (XEXP (x, 0)); - fputc (')', file); - break; - - case REG: - fprintf (file, "%s", reg_names[REGNO (x) + 1]); - break; - - case SUBREG: - fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); - break; - - case CONST_DOUBLE: - if (code == 'H') - { - long val; - REAL_VALUE_TYPE rv; - - REAL_VALUE_FROM_CONST_DOUBLE (rv, x); - REAL_VALUE_TO_TARGET_SINGLE (rv, val); - - print_operand_address (file, GEN_INT ((val >> 16) & 0xffff)); - } - else - { - long val; - REAL_VALUE_TYPE rv; - - REAL_VALUE_FROM_CONST_DOUBLE (rv, x); - REAL_VALUE_TO_TARGET_SINGLE (rv, val); - - val = (val >> 16) & 0xffff; - val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000; - - print_operand_address (file, GEN_INT (val)); - } - break; - - case CONST_INT: - if (code == 'H') - print_operand_address (file, - GEN_INT ((INTVAL (x) >> 16) & 0xffff)); - else - { - unsigned int val = (INTVAL (x) >> 16) & 0xffff; - val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000; - - print_operand_address (file, GEN_INT (val)); - } - break; - default: - abort (); - } - break; - - /* Output ~CONST_INT. */ - case 'N': - if (GET_CODE (x) != CONST_INT) - abort (); - fprintf (file, "%d", ~INTVAL (x)); - break; - - /* An address which can not be register indirect, if it is - register indirect, then turn it into reg + disp. */ - case 'A': - if (GET_CODE (x) != MEM) - abort (); - if (GET_CODE (XEXP (x, 0)) == REG) - x = gen_rtx_PLUS (PSImode, XEXP (x, 0), GEN_INT (0)); - else - x = XEXP (x, 0); - fputc ('(', file); - output_address (x); - fputc (')', file); - break; - - case 'Z': - print_operand (file, XEXP (x, 1), 0); - break; - - /* More cases where we can sign-extend a CONST_INT if it - results in more compact code. */ - case 's': - case 'S': - if (GET_CODE (x) == CONST_INT) - { - int val = INTVAL (x); - - if (code == 's') - x = GEN_INT (((val & 0xffff) ^ (~0x7fff)) + 0x8000); - else - x = GEN_INT (((val & 0xff) ^ (~0x7f)) + 0x80); - } - /* FALL THROUGH */ - default: - switch (GET_CODE (x)) - { - case MEM: - fputc ('(', file); - output_address (XEXP (x, 0)); - fputc (')', file); - break; - - case REG: - fprintf (file, "%s", reg_names[REGNO (x)]); - break; - - case SUBREG: - fprintf (file, "%s", reg_names[subreg_regno (x)]); - break; - - case CONST_INT: - case CONST_DOUBLE: - case SYMBOL_REF: - case CONST: - case LABEL_REF: - case CODE_LABEL: - print_operand_address (file, x); - break; - default: - abort (); - } - break; - } -} - -/* Output assembly language output for the address ADDR to FILE. */ - -void -print_operand_address (file, addr) - FILE *file; - rtx addr; -{ - switch (GET_CODE (addr)) - { - case REG: - print_operand (file, addr, 0); - break; - case PLUS: - { - rtx base, index; - /* The base and index could be in any order, so we have - to figure out which is the base and which is the index. - Uses the same code as GO_IF_LEGITIMATE_ADDRESS. */ - if (REG_P (XEXP (addr, 0)) - && REG_OK_FOR_BASE_P (XEXP (addr, 0))) - base = XEXP (addr, 0), index = XEXP (addr, 1); - else if (REG_P (XEXP (addr, 1)) - && REG_OK_FOR_BASE_P (XEXP (addr, 1))) - base = XEXP (addr, 1), index = XEXP (addr, 0); - else - abort (); - print_operand (file, index, 0); - fputc (',', file); - print_operand (file, base, 0);; - break; - } - case SYMBOL_REF: - output_addr_const (file, addr); - break; - default: - output_addr_const (file, addr); - break; - } -} - -/* Count the number of tst insns which compare an address register - with zero. */ -static void -count_tst_insns (areg_countp) - int *areg_countp; -{ - rtx insn; - - /* Assume no tst insns exist. */ - *areg_countp = 0; - - /* If not optimizing, then quit now. */ - if (!optimize) - return; - - /* Walk through all the insns. */ - for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) - { - rtx pat; - - /* Ignore anything that is not a normal INSN. */ - if (GET_CODE (insn) != INSN) - continue; - - /* Ignore anything that isn't a SET. */ - pat = PATTERN (insn); - if (GET_CODE (pat) != SET) - continue; - - /* Check for a tst insn. */ - if (SET_DEST (pat) == cc0_rtx - && GET_CODE (SET_SRC (pat)) == REG - && REGNO_REG_CLASS (REGNO (SET_SRC (pat))) == ADDRESS_REGS) - (*areg_countp)++; - } -} - -/* Return the total size (in bytes) of the current function's frame. - This is the size of the register save area + the size of locals, - spills, etc. */ -int -total_frame_size () -{ - unsigned int size = get_frame_size (); - unsigned int outgoing_args_size = current_function_outgoing_args_size; - int i; - - /* First figure out if we're going to use an out of line - prologue, if so we have to make space for all the - registers, even if we don't use them. */ - if (optimize && !current_function_needs_context && !frame_pointer_needed) - { - int inline_count, outline_count; - - /* Compute how many bytes an inline prologue would take. - - Each address register store takes two bytes, each data register - store takes three bytes. */ - inline_count = 0; - if (regs_ever_live[5]) - inline_count += 2; - if (regs_ever_live[6]) - inline_count += 2; - if (regs_ever_live[2]) - inline_count += 3; - if (regs_ever_live[3]) - inline_count += 3; - - /* If this function has any stack, then the stack adjustment - will take two (or more) bytes. */ - if (size || outgoing_args_size - || regs_ever_live[5] || regs_ever_live[6] - || regs_ever_live[2] || regs_ever_live[3]) - inline_count += 2; - - /* Multiply the current count by two and add one to account for the - epilogue insns. */ - inline_count = inline_count * 2 + 1; - - /* Now compute how many bytes an out of line sequence would take. */ - /* A relaxed jsr will be three bytes. */ - outline_count = 3; - - /* If there are outgoing arguments, then we will need a stack - pointer adjustment after the call to the prologue, two - more bytes. */ - outline_count += (outgoing_args_size == 0 ? 0 : 2); - - /* If there is some local frame to allocate, it will need to be - done before the call to the prologue, two more bytes. */ - if (get_frame_size () != 0) - outline_count += 2; - - /* Now account for the epilogue, multiply the base count by two, - then deal with optimizing away the rts instruction. */ - outline_count = outline_count * 2 + 1; - - if (get_frame_size () == 0 && outgoing_args_size == 0) - outline_count -= 1; - - /* If an out of line prologue is smaller, use it. */ - if (inline_count > outline_count) - return size + outgoing_args_size + 16; - } - - - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) - { - if ((regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i]) - || (i == FRAME_POINTER_REGNUM && frame_pointer_needed)) - size += 4; - } - - return (size + outgoing_args_size); -} - -/* Expand the prologue into RTL. */ -void -expand_prologue () -{ - unsigned int size = total_frame_size (); - unsigned int outgoing_args_size = current_function_outgoing_args_size; - int offset, i; - - zero_areg = NULL_RTX; - zero_dreg = NULL_RTX; - - /* If optimizing, see if we should do an out of line prologue/epilogue - sequence. - - We don't support out of line prologues if the current function - needs a context or frame pointer. */ - if (optimize && !current_function_needs_context && !frame_pointer_needed) - { - int inline_count, outline_count, areg_count; - - /* We need to end the current sequence so that count_tst_insns can - look at all the insns in this function. Normally this would be - unsafe, but it's OK in the prologue/epilogue expanders. */ - end_sequence (); - - /* Get a count of the number of tst insns which use address - registers (it's not profitable to try and improve tst insns - which use data registers). */ - count_tst_insns (&areg_count); - - /* Now start a new sequence. */ - start_sequence (); - - /* Compute how many bytes an inline prologue would take. - - Each address register store takes two bytes, each data register - store takes three bytes. */ - inline_count = 0; - if (regs_ever_live[5]) - inline_count += 2; - if (regs_ever_live[6]) - inline_count += 2; - if (regs_ever_live[2]) - inline_count += 3; - if (regs_ever_live[3]) - inline_count += 3; - - /* If this function has any stack, then the stack adjustment - will take two (or more) bytes. */ - if (size || outgoing_args_size - || regs_ever_live[5] || regs_ever_live[6] - || regs_ever_live[2] || regs_ever_live[3]) - inline_count += 2; - - /* Multiply the current count by two and add one to account for the - epilogue insns. */ - inline_count = inline_count * 2 + 1; - - /* Now compute how many bytes an out of line sequence would take. */ - /* A relaxed jsr will be three bytes. */ - outline_count = 3; - - /* If there are outgoing arguments, then we will need a stack - pointer adjustment after the call to the prologue, two - more bytes. */ - outline_count += (outgoing_args_size == 0 ? 0 : 2); - - /* If there is some local frame to allocate, it will need to be - done before the call to the prologue, two more bytes. */ - if (get_frame_size () != 0) - outline_count += 2; - - /* Now account for the epilogue, multiply the base count by two, - then deal with optimizing away the rts instruction. */ - outline_count = outline_count * 2 + 1; - - if (get_frame_size () == 0 && outgoing_args_size == 0) - outline_count -= 1; - - /* If an out of line prologue is smaller, use it. */ - if (inline_count > outline_count) - { - if (get_frame_size () != 0) - emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (-size + outgoing_args_size + 16))); - emit_insn (gen_outline_prologue_call ()); - - if (outgoing_args_size) - emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (-outgoing_args_size))); - - out_of_line_epilogue = 1; - - /* Determine if it is profitable to put the value zero into a register - for the entire function. If so, set ZERO_DREG and ZERO_AREG. */ - - /* First see if we could load the value into a data register - since that's the most efficient way. */ - if (areg_count > 1 - && (!regs_ever_live[2] || !regs_ever_live[3])) - { - if (!regs_ever_live[2]) - { - regs_ever_live[2] = 1; - zero_dreg = gen_rtx_REG (HImode, 2); - } - if (!regs_ever_live[3]) - { - regs_ever_live[3] = 1; - zero_dreg = gen_rtx_REG (HImode, 3); - } - } - - /* Now see if we could load the value into an address register. */ - if (zero_dreg == NULL_RTX - && areg_count > 2 - && (!regs_ever_live[5] || !regs_ever_live[6])) - { - if (!regs_ever_live[5]) - { - regs_ever_live[5] = 1; - zero_areg = gen_rtx_REG (HImode, 5); - } - if (!regs_ever_live[6]) - { - regs_ever_live[6] = 1; - zero_areg = gen_rtx_REG (HImode, 6); - } - } - - if (zero_dreg) - emit_move_insn (zero_dreg, const0_rtx); - - if (zero_areg) - emit_move_insn (zero_areg, const0_rtx); - - return; - } - } - - out_of_line_epilogue = 0; - - /* Temporarily stuff the static chain onto the stack so we can - use a0 as a scratch register during the prologue. */ - if (current_function_needs_context) - { - emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (-4))); - emit_move_insn (gen_rtx_MEM (PSImode, stack_pointer_rtx), - gen_rtx_REG (PSImode, STATIC_CHAIN_REGNUM)); - } - - if (frame_pointer_needed) - { - /* Store a2 into a0 temporarily. */ - emit_move_insn (gen_rtx_REG (PSImode, 4), frame_pointer_rtx); - - /* Set up the frame pointer. */ - emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); - } - - /* Make any necessary space for the saved registers and local frame. */ - if (size) - emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (-size))); - - /* Save the callee saved registers. They're saved into the top - of the frame, using the stack pointer. */ - for (i = 0, offset = outgoing_args_size; - i < FIRST_PSEUDO_REGISTER; i++) - { - if ((regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i]) - || (i == FRAME_POINTER_REGNUM && frame_pointer_needed)) - { - int regno; - - /* If we're saving the frame pointer, then it will be found in - register 4 (a0). */ - regno = (i == FRAME_POINTER_REGNUM && frame_pointer_needed) ? 4 : i; - - emit_move_insn (gen_rtx_MEM (PSImode, - plus_constant (stack_pointer_rtx, - offset)), - gen_rtx_REG (PSImode, regno)); - offset += 4; - } - } - - /* Now put the static chain back where the rest of the function - expects to find it. - - Note that we may eliminate all references to this later, so we - mark the static chain as maybe dead. */ - if (current_function_needs_context) - { - rtx insn; - - insn = emit_move_insn (gen_rtx_REG (PSImode, STATIC_CHAIN_REGNUM), - gen_rtx (MEM, PSImode, - gen_rtx_PLUS (PSImode, - stack_pointer_rtx, - GEN_INT (size)))); - REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, - const0_rtx, - REG_NOTES (insn)); - - } -} - -/* Expand the epilogue into RTL. */ -void -expand_epilogue () -{ - unsigned int size; - unsigned int outgoing_args_size = current_function_outgoing_args_size; - int offset, i, temp_regno; - rtx basereg; - - size = total_frame_size (); - - if (DECL_RESULT (current_function_decl) - && POINTER_TYPE_P (TREE_TYPE (DECL_RESULT (current_function_decl)))) - temp_regno = 0; - else - temp_regno = 4; - - /* Emit an out of line epilogue sequence if it's profitable to do so. */ - if (out_of_line_epilogue) - { - /* If there were no outgoing arguments and no local frame, then - we will be able to omit the rts at the end of this function, - so just jump to the epilogue_noreturn routine. */ - if (get_frame_size () == 0 && outgoing_args_size == 0) - { - emit_jump_insn (gen_outline_epilogue_jump ()); - return; - } - - if (outgoing_args_size) - emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (outgoing_args_size))); - - if (temp_regno == 0) - emit_insn (gen_outline_epilogue_call_d0 ()); - else if (temp_regno == 4) - emit_insn (gen_outline_epilogue_call_a0 ()); - - if (get_frame_size () != 0) - emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (size - outgoing_args_size - 16))); - emit_jump_insn (gen_return_internal ()); - return; - } - - /* Registers are restored from the frame pointer if we have one, - else they're restored from the stack pointer. Figure out - the appropriate offset to the register save area for both cases. */ - if (frame_pointer_needed) - { - basereg = frame_pointer_rtx; - offset = -(size - outgoing_args_size); - } - else - { - basereg = stack_pointer_rtx; - offset = outgoing_args_size; - } - - /* Restore each register. */ - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) - { - if ((regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i]) - || (i == FRAME_POINTER_REGNUM && frame_pointer_needed)) - { - int regno; - - /* Restore the frame pointer (if it exists) into a temporary - register. */ - regno = ((i == FRAME_POINTER_REGNUM && frame_pointer_needed) - ? temp_regno : i); - - emit_move_insn (gen_rtx_REG (PSImode, regno), - gen_rtx_MEM (PSImode, - plus_constant (basereg, offset))); - offset += 4; - } - } - - if (frame_pointer_needed) - { - /* Deallocate this frame's stack. */ - emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); - /* Restore the old frame pointer. */ - emit_move_insn (frame_pointer_rtx, gen_rtx_REG (PSImode, temp_regno)); - } - else if (size) - { - /* Deallocate this function's stack. */ - emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (size))); - } - - /* If we had to allocate a slot to save the context pointer, - then it must be deallocated here. */ - if (current_function_needs_context) - emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (4))); - - /* Emit the return insn, if this function had no stack, then we - can use the standard return (which allows more optimizations), - else we have to use the special one which inhibits optimizations. */ - if (size == 0 && !current_function_needs_context) - emit_jump_insn (gen_return ()); - else - emit_jump_insn (gen_return_internal ()); -} - -/* Update the condition code from the insn. */ - -void -notice_update_cc (body, insn) - rtx body; - rtx insn; -{ - switch (get_attr_cc (insn)) - { - case CC_NONE: - /* Insn does not affect CC at all. */ - break; - - case CC_NONE_0HIT: - /* Insn does not change CC, but the 0'th operand has been changed. */ - if (cc_status.value1 != 0 - && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) - cc_status.value1 = 0; - break; - - case CC_SET_ZN: - /* Insn sets the Z,N flags of CC to recog_data.operand[0]. - V,C is in an unusable state. */ - CC_STATUS_INIT; - cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; - cc_status.value1 = recog_data.operand[0]; - break; - - case CC_SET_ZNV: - /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. - C is in an unusable state. */ - CC_STATUS_INIT; - cc_status.flags |= CC_NO_CARRY; - cc_status.value1 = recog_data.operand[0]; - break; - - case CC_COMPARE: - /* The insn is a compare instruction. */ - CC_STATUS_INIT; - cc_status.value1 = SET_SRC (body); - break; - - case CC_CLOBBER: - /* Insn doesn't leave CC in a usable state. */ - CC_STATUS_INIT; - break; - - default: - CC_STATUS_INIT; - break; - } -} - -/* Return true if OP is a valid call operand. Valid call operands - are SYMBOL_REFs and REGs. */ -int -call_address_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG); -} - -/* Return true if OP is a memory operand with a constant address. - A special PSImode move pattern uses this predicate. */ -int -constant_memory_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return GET_CODE (op) == MEM && CONSTANT_ADDRESS_P (XEXP (op, 0)); -} - -/* Return true if OP is valid for a psi mode truncation operand. - It must either be a memory operand which is valid for a PSImode - address, or if it is not a memory operand at all. */ -int -psimode_truncation_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (general_operand (op, mode) - && (GET_CODE (op) != MEM - || memory_address_p (PSImode, XEXP (op, 0)))); -} - -/* What (if any) secondary registers are needed to move IN with mode - MODE into a register from in register class CLASS. - - We might be able to simplify this. */ -enum reg_class -secondary_reload_class (class, mode, in, input) - enum reg_class class; - enum machine_mode mode; - rtx in; - int input; -{ - /* Memory loads less than a full word wide can't have an - address or stack pointer destination. They must use - a data register as an intermediate register. */ - if (input - && GET_CODE (in) == MEM - && (mode == QImode) - && class == ADDRESS_REGS) - return DATA_REGS; - - /* Address register stores which are not PSImode need a scratch register. */ - if (! input - && GET_CODE (in) == MEM - && (mode != PSImode) - && class == ADDRESS_REGS) - return DATA_REGS; - - /* Otherwise assume no secondary reloads are needed. */ - return NO_REGS; -} - - -/* Shifts. - - We devote a fair bit of code to getting efficient shifts since we can only - shift one bit at a time, and each single bit shift may take multiple - instructions. - - The basic shift methods: - - * loop shifts -- emit a loop using one (or two on H8S) bit shifts; - this is the default. SHIFT_LOOP - - * inlined shifts -- emit straight line code for the shift; this is - used when a straight line shift is about the same size or smaller - than a loop. We allow the inline version to be slightly longer in - some cases as it saves a register. SHIFT_INLINE - - * There other oddballs. Not worth explaining. SHIFT_SPECIAL - - - HImode shifts: - - 1-4 do them inline - - 5-7 If ashift, then multiply, else loop. - - 8-14 - If ashift, then multiply, if lshiftrt, then divide, else loop. - 15 - rotate the bit we want into the carry, clear the destination, - (use mov 0,dst, not sub as sub will clobber the carry), then - move bit into place. - - Don't Panic, it's not nearly as bad as the H8 shifting code!!! */ - -int -nshift_operator (x, mode) - rtx x; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - switch (GET_CODE (x)) - { - case ASHIFTRT: - case LSHIFTRT: - case ASHIFT: - return 1; - - default: - return 0; - } -} - -/* Called from the .md file to emit code to do shifts. - Returns a boolean indicating success - (currently this is always TRUE). */ - -int -expand_a_shift (mode, code, operands) - enum machine_mode mode; - int code; - rtx operands[]; -{ - emit_move_insn (operands[0], operands[1]); - - /* need a loop to get all the bits we want - we generate the - code at emit time, but need to allocate a scratch reg now */ - - emit_insn (gen_rtx_PARALLEL - (VOIDmode, - gen_rtvec (2, - gen_rtx_SET (VOIDmode, operands[0], - gen_rtx (code, mode, - operands[0], operands[2])), - gen_rtx_CLOBBER (VOIDmode, - gen_rtx_SCRATCH (HImode))))); - - return 1; -} - -/* Shift algorithm determination. - - There are various ways of doing a shift: - SHIFT_INLINE: If the amount is small enough, just generate as many one-bit - shifts as we need. - SHIFT_SPECIAL: Hand crafted assembler. - SHIFT_LOOP: If the above methods fail, just loop. */ - -enum shift_alg -{ - SHIFT_INLINE, - SHIFT_SPECIAL, - SHIFT_LOOP, - SHIFT_MAX -}; - -/* Symbols of the various shifts which can be used as indices. */ - -enum shift_type - { - SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT - }; - -/* Symbols of the various modes which can be used as indices. */ - -enum shift_mode - { - HIshift - }; - -/* For single bit shift insns, record assembler and what bits of the - condition code are valid afterwards (represented as various CC_FOO - bits, 0 means CC isn't left in a usable state). */ - -struct shift_insn -{ - const char *assembler; - int cc_valid; -}; - -/* Assembler instruction shift table. - - These tables are used to look up the basic shifts. - They are indexed by cpu, shift_type, and mode. -*/ - -static const struct shift_insn shift_one[3][3] = -{ - { -/* SHIFT_ASHIFT */ - { "add\t%0,%0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, - }, -/* SHIFT_LSHIFTRT */ - { - { "lsr\t%0", CC_NO_CARRY }, - }, -/* SHIFT_ASHIFTRT */ - { - { "asr\t%0", CC_NO_CARRY }, - }, -}; - -static enum shift_alg get_shift_alg PARAMS ((enum shift_type, - enum machine_mode, int, - const char **, int *)); - -/* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best - algorithm for doing the shift. The assembler code is stored in ASSEMBLER. - We don't achieve maximum efficiency in all cases, but the hooks are here - to do so. - - For now we just use lots of switch statements. Since we don't even come - close to supporting all the cases, this is simplest. If this function ever - gets too big, perhaps resort to a more table based lookup. Of course, - at this point you may just wish to do it all in rtl. */ - -static enum shift_alg -get_shift_alg (shift_type, mode, count, assembler_p, cc_valid_p) - enum shift_type shift_type; - enum machine_mode mode; - int count; - const char **assembler_p; - int *cc_valid_p; -{ - /* The default is to loop. */ - enum shift_alg alg = SHIFT_LOOP; - enum shift_mode shift_mode; - - /* We don't handle negative shifts or shifts greater than the word size, - they should have been handled already. */ - - if (count < 0 || count > GET_MODE_BITSIZE (mode)) - abort (); - - switch (mode) - { - case HImode: - shift_mode = HIshift; - break; - default: - abort (); - } - - /* Assume either SHIFT_LOOP or SHIFT_INLINE. - It is up to the caller to know that looping clobbers cc. */ - *assembler_p = shift_one[shift_type][shift_mode].assembler; - *cc_valid_p = shift_one[shift_type][shift_mode].cc_valid; - - /* Now look for cases we want to optimize. */ - - switch (shift_mode) - { - case HIshift: - if (count <= 4) - return SHIFT_INLINE; - else if (count < 15 && shift_type != SHIFT_ASHIFTRT) - { - switch (count) - { - case 5: - if (shift_type == SHIFT_ASHIFT) - *assembler_p = "mov 32,%4\n\tmul %4,%0"; - else if (shift_type == SHIFT_LSHIFTRT) - *assembler_p - = "sub %4,%4\n\tmov %4,mdr\n\tmov 32,%4\n\tdivu %4,%0"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - case 6: - if (shift_type == SHIFT_ASHIFT) - *assembler_p = "mov 64,%4\n\tmul %4,%0"; - else if (shift_type == SHIFT_LSHIFTRT) - *assembler_p - = "sub %4,%4\n\tmov %4,mdr\n\tmov 64,%4\n\tdivu %4,%0"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - case 7: - if (shift_type == SHIFT_ASHIFT) - *assembler_p = "mov 128,%4\n\tmul %4,%0"; - else if (shift_type == SHIFT_LSHIFTRT) - *assembler_p - = "sub %4,%4\n\tmov %4,mdr\n\tmov 128,%4\n\tdivu %4,%0"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - case 8: - if (shift_type == SHIFT_ASHIFT) - *assembler_p = "mov 256,%4\n\tmul %4,%0"; - else if (shift_type == SHIFT_LSHIFTRT) - *assembler_p - = "sub %4,%4\n\tmov %4,mdr\n\tmov 256,%4\n\tdivu %4,%0"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - case 9: - if (shift_type == SHIFT_ASHIFT) - *assembler_p = "mov 512,%4\n\tmul %4,%0"; - else if (shift_type == SHIFT_LSHIFTRT) - *assembler_p - = "sub %4,%4\n\tmov %4,mdr\n\tmov 512,%4\n\tdivu %4,%0"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - case 10: - if (shift_type == SHIFT_ASHIFT) - *assembler_p = "mov 1024,%4\n\tmul %4,%0"; - else if (shift_type == SHIFT_LSHIFTRT) - *assembler_p - = "sub %4,%4\n\tmov %4,mdr\n\tmov 1024,%4\n\tdivu %4,%0"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - case 11: - if (shift_type == SHIFT_ASHIFT) - *assembler_p = "mov 2048,%4\n\tmul %4,%0"; - else if (shift_type == SHIFT_LSHIFTRT) - *assembler_p - = "sub %4,%4\n\tmov %4,mdr\n\tmov 2048,%4\n\tdivu %4,%0"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - case 12: - if (shift_type == SHIFT_ASHIFT) - *assembler_p = "mov 4096,%4\n\tmul %4,%0"; - else if (shift_type == SHIFT_LSHIFTRT) - *assembler_p - = "sub %4,%4\n\tmov %4,mdr\n\tmov 4096,%4\n\tdivu %4,%0"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - case 13: - if (shift_type == SHIFT_ASHIFT) - *assembler_p = "mov 8192,%4\n\tmul %4,%0"; - else if (shift_type == SHIFT_LSHIFTRT) - *assembler_p - = "sub %4,%4\n\tmov %4,mdr\n\tmov 8192,%4\n\tdivu %4,%0"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - case 14: - if (shift_type == SHIFT_ASHIFT) - *assembler_p = "mov 16384,%4\n\tmul %4,%0"; - else if (shift_type == SHIFT_LSHIFTRT) - *assembler_p - = "sub %4,%4\n\tmov %4,mdr\n\tmov 16384,%4\n\tdivu %4,%0"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - } - } - else if (count == 15) - { - if (shift_type == SHIFT_ASHIFTRT) - { - *assembler_p = "add\t%0,%0\n\tsubc\t%0,%0\n"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - } - if (shift_type == SHIFT_LSHIFTRT) - { - *assembler_p = "add\t%0,%0\n\tmov 0,%0\n\trol %0\n"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - } - if (shift_type == SHIFT_ASHIFT) - { - *assembler_p = "ror\t%0\n\tmov 0,%0\n\tror %0\n"; - *cc_valid_p = CC_NO_CARRY; - return SHIFT_SPECIAL; - } - } - break; - - default: - abort (); - } - - return alg; -} - -/* Emit the assembler code for doing shifts. */ - -const char * -emit_a_shift (insn, operands) - rtx insn ATTRIBUTE_UNUSED; - rtx *operands; -{ - static int loopend_lab; - const char *assembler; - int cc_valid; - rtx shift = operands[3]; - enum machine_mode mode = GET_MODE (shift); - enum rtx_code code = GET_CODE (shift); - enum shift_type shift_type; - enum shift_mode shift_mode; - - loopend_lab++; - - switch (mode) - { - case HImode: - shift_mode = HIshift; - break; - default: - abort (); - } - - switch (code) - { - case ASHIFTRT: - shift_type = SHIFT_ASHIFTRT; - break; - case LSHIFTRT: - shift_type = SHIFT_LSHIFTRT; - break; - case ASHIFT: - shift_type = SHIFT_ASHIFT; - break; - default: - abort (); - } - - if (GET_CODE (operands[2]) != CONST_INT) - { - /* Indexing by reg, so have to loop and test at top */ - output_asm_insn ("mov %2,%4", operands); - output_asm_insn ("cmp 0,%4", operands); - fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab); - - /* Get the assembler code to do one shift. */ - get_shift_alg (shift_type, mode, 1, &assembler, &cc_valid); - } - else - { - int n = INTVAL (operands[2]); - enum shift_alg alg; - - /* If the count is negative, make it 0. */ - if (n < 0) - n = 0; - /* If the count is too big, truncate it. - ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to - do the intuitive thing. */ - else if (n > GET_MODE_BITSIZE (mode)) - n = GET_MODE_BITSIZE (mode); - - alg = get_shift_alg (shift_type, mode, n, &assembler, &cc_valid); - - - switch (alg) - { - case SHIFT_INLINE: - /* Emit one bit shifts. */ - while (n > 0) - { - output_asm_insn (assembler, operands); - n -= 1; - } - - /* Keep track of CC. */ - if (cc_valid) - { - cc_status.value1 = operands[0]; - cc_status.flags |= cc_valid; - } - return ""; - - case SHIFT_SPECIAL: - output_asm_insn (assembler, operands); - - /* Keep track of CC. */ - if (cc_valid) - { - cc_status.value1 = operands[0]; - cc_status.flags |= cc_valid; - } - return ""; - } - - { - fprintf (asm_out_file, "\tmov %d,%s\n", n, - reg_names[REGNO (operands[4])]); - fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); - output_asm_insn (assembler, operands); - output_asm_insn ("add -1,%4", operands); - fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); - return ""; - } - } - - fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); - output_asm_insn (assembler, operands); - output_asm_insn ("add -1,%4", operands); - fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); - fprintf (asm_out_file, ".Lle%d:\n", loopend_lab); - - return ""; -} - -/* Return an RTX to represent where a value with mode MODE will be returned - from a function. If the result is 0, the argument is pushed. */ - -rtx -function_arg (cum, mode, type, named) - CUMULATIVE_ARGS *cum; - enum machine_mode mode; - tree type; - int named; -{ - rtx result = 0; - int size, align; - - /* We only support using 2 data registers as argument registers. */ - int nregs = 2; - - /* Only pass named arguments in registers. */ - if (!named) - return NULL_RTX; - - /* Figure out the size of the object to be passed. We lie and claim - PSImode values are only two bytes since they fit in a single - register. */ - if (mode == BLKmode) - size = int_size_in_bytes (type); - else if (mode == PSImode) - size = 2; - else - size = GET_MODE_SIZE (mode); - - /* Figure out the alignment of the object to be passed. */ - align = size; - - cum->nbytes = (cum->nbytes + 1) & ~1; - - /* Don't pass this arg via a register if all the argument registers - are used up. */ - if (cum->nbytes + size > nregs * UNITS_PER_WORD) - return 0; - - switch (cum->nbytes / UNITS_PER_WORD) - { - case 0: - result = gen_rtx_REG (mode, 0); - break; - case 1: - result = gen_rtx_REG (mode, 1); - break; - default: - result = 0; - } - - return result; -} - -/* Return the number of registers to use for an argument passed partially - in registers and partially in memory. */ - -int -function_arg_partial_nregs (cum, mode, type, named) - CUMULATIVE_ARGS *cum; - enum machine_mode mode; - tree type; - int named; -{ - int size, align; - - /* We only support using 2 data registers as argument registers. */ - int nregs = 2; - - return 0; - /* Only pass named arguments in registers. */ - if (!named) - return 0; - - /* Figure out the size of the object to be passed. */ - if (mode == BLKmode) - size = int_size_in_bytes (type); - else if (mode == PSImode) - size = 2; - else - size = GET_MODE_SIZE (mode); - - /* Figure out the alignment of the object to be passed. */ - align = size; - - cum->nbytes = (cum->nbytes + 1) & ~1; - - /* Don't pass this arg via a register if all the argument registers - are used up. */ - if (cum->nbytes > nregs * UNITS_PER_WORD) - return 0; - - if (cum->nbytes + size <= nregs * UNITS_PER_WORD) - return 0; - - /* Don't pass this arg via a register if it would be split between - registers and memory. */ - if (type == NULL_TREE - && cum->nbytes + size > nregs * UNITS_PER_WORD) - return 0; - - return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD; -} - -rtx -mn10200_va_arg (valist, type) - tree valist, type; -{ - HOST_WIDE_INT align, rsize; - tree t, ptr, pptr; - - /* Compute the rounded size of the type. */ - align = PARM_BOUNDARY / BITS_PER_UNIT; - rsize = (((int_size_in_bytes (type) + align - 1) / align) * align); - - t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, - build_int_2 ((rsize > 8 ? 4 : rsize), 0)); - TREE_SIDE_EFFECTS (t) = 1; - - ptr = build_pointer_type (type); - - /* "Large" types are passed by reference. */ - if (rsize > 8) - { - pptr = build_pointer_type (ptr); - t = build1 (NOP_EXPR, pptr, t); - TREE_SIDE_EFFECTS (t) = 1; - - t = build1 (INDIRECT_REF, ptr, t); - TREE_SIDE_EFFECTS (t) = 1; - } - else - { - t = build1 (NOP_EXPR, ptr, t); - TREE_SIDE_EFFECTS (t) = 1; - } - - /* Calculate! */ - return force_reg (Pmode, expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL)); -} - -const char * -output_tst (operand, insn) - rtx operand, insn; -{ - - rtx temp; - int past_call = 0; - - /* Only tst insns using address registers can be optimized. */ - if (REGNO_REG_CLASS (REGNO (operand)) != ADDRESS_REGS) - return "cmp 0,%0"; - - /* If testing an address register against zero, we can do better if - we know there's a register already holding the value zero. First - see if a global register has been set to zero, else we do a search - for a register holding zero, if both of those fail, then we use a - compare against zero. */ - if (zero_dreg || zero_areg) - { - rtx xoperands[2]; - xoperands[0] = operand; - xoperands[1] = zero_dreg ? zero_dreg : zero_areg; - - output_asm_insn ("cmp %1,%0", xoperands); - return ""; - } - - /* We can save a byte if we can find a register which has the value - zero in it. */ - temp = PREV_INSN (insn); - while (temp) - { - rtx set; - - /* We allow the search to go through call insns. We record - the fact that we've past a CALL_INSN and reject matches which - use call clobbered registers. */ - if (GET_CODE (temp) == CODE_LABEL - || GET_CODE (temp) == JUMP_INSN - || GET_CODE (temp) == BARRIER) - break; - - if (GET_CODE (temp) == CALL_INSN) - past_call = 1; - - if (GET_CODE (temp) == NOTE) - { - temp = PREV_INSN (temp); - continue; - } - - /* It must be an insn, see if it is a simple set. */ - set = single_set (temp); - if (!set) - { - temp = PREV_INSN (temp); - continue; - } - - /* Are we setting a register to zero? - - If it's a call clobbered register, have we past a call? */ - if (REG_P (SET_DEST (set)) - && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) - && !reg_set_between_p (SET_DEST (set), temp, insn) - && (!past_call - || !call_used_regs[REGNO (SET_DEST (set))])) - { - rtx xoperands[2]; - xoperands[0] = operand; - xoperands[1] = SET_DEST (set); - - output_asm_insn ("cmp %1,%0", xoperands); - return ""; - } - temp = PREV_INSN (temp); - } - return "cmp 0,%0"; -} - -/* Return nonzero if OP is a valid operand for a {zero,sign}_extendpsisi - instruction. - - It accepts anything that is a general operand or the sum of the - stack pointer and a general operand. */ -int -extendpsi_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (general_operand (op, mode) - || (GET_CODE (op) == PLUS - && XEXP (op, 0) == stack_pointer_rtx - && general_operand (XEXP (op, 1), VOIDmode))); -} - -static bool -mn10200_rtx_costs (x, code, outer_code, total) - rtx x; - int code, outer_code ATTRIBUTE_UNUSED; - int *total; -{ - switch (code) - { - case CONST_INT: - /* Zeros are extremely cheap. */ - if (INTVAL (x) == 0) - *total = 0; - /* If it fits in 8 bits, then it's still relatively cheap. */ - else if (INT_8_BITS (INTVAL (x))) - *total = 1; - /* This is the "base" cost, includes constants where either the - upper or lower 16bits are all zeros. */ - else if (INT_16_BITS (INTVAL (x)) - || (INTVAL (x) & 0xffff) == 0 - || (INTVAL (x) & 0xffff0000) == 0) - *total = 2; - else - *total = 4; - return true; - - case CONST: - case LABEL_REF: - case SYMBOL_REF: - /* These are more costly than a CONST_INT, but we can relax them, - so they're less costly than a CONST_DOUBLE. */ - *total = 6; - return true; - - case CONST_DOUBLE: - /* We don't optimize CONST_DOUBLEs well nor do we relax them well, - so their cost is very high. */ - *total = 8; - return true; - - /* ??? This probably needs more work. The definitions below were first - taken from the H8 port, then tweaked slightly to improve code density - on various sample codes. */ - case MOD: - case DIV: - *total = 8; - return true; - - case MULT: - *total = (GET_MODE (x) == SImode ? 20 : 8); - return true; - - default: - return false; - } -} diff --git a/gcc/config/mn10200/mn10200.h b/gcc/config/mn10200/mn10200.h deleted file mode 100644 index 7ea4bb3f398..00000000000 --- a/gcc/config/mn10200/mn10200.h +++ /dev/null @@ -1,933 +0,0 @@ -/* Definitions of target machine for GNU compiler. - Matsushita MN10200 series - Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 - Free Software Foundation, Inc. - Contributed by Jeff Law (law@cygnus.com). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - - -/* Get rid of svr4.h stuff we don't want/need. */ -#undef ASM_SPEC -#undef ASM_FINAL_SPEC -#undef LIB_SPEC -#undef ENDFILE_SPEC -#undef LINK_SPEC -#undef STARTFILE_SPEC - -/* Names to predefine in the preprocessor for this target machine. */ - -#define TARGET_CPU_CPP_BUILTINS() \ - do \ - { \ - builtin_define ("__mn10200__"); \ - builtin_define ("__MN10200__"); \ - } \ - while (0) - -/* Run-time compilation parameters selecting different hardware subsets. */ - -/* We don't have any switched on the mn10200. Though there are some things - that might be worth a switch: - - -mspace to optimize even more for space. - - -mrelax to enable the relaxing linker. */ - -extern int target_flags; - -/* Macros used in the machine description to test the flags. */ - -/* Macro to define tables used to set the flags. - This is a list in braces of pairs in braces, - each pair being { "NAME", VALUE } - where VALUE is the bits to set or minus the bits to clear. - An empty string NAME is used to identify the default VALUE. */ - -#define TARGET_SWITCHES \ - {{ "", TARGET_DEFAULT, 0}} - -#ifndef TARGET_DEFAULT -#define TARGET_DEFAULT 0 -#endif - -/* Print subsidiary information on the compiler version in use. */ - -#define TARGET_VERSION fprintf (stderr, " (MN10200)"); - - -/* Target machine storage layout */ - -/* Define this if most significant bit is lowest numbered - in instructions that operate on numbered bit-fields. - This is not true on the Matsushita MN10300. */ -#define BITS_BIG_ENDIAN 0 - -/* Define this if most significant byte of a word is the lowest numbered. */ -/* This is not true on the Matsushita MN10200. */ -#define BYTES_BIG_ENDIAN 0 - -/* Define this if most significant word of a multiword number is lowest - numbered. - This is not true on the Matsushita MN10200. */ -#define WORDS_BIG_ENDIAN 0 - -/* This is a white lie. Registers are really 24bits, but most operations - only operate on 16 bits. GCC chokes badly if we set this to a value - that is not a power of two. */ -/* Width of a word, in units (bytes). */ -#define UNITS_PER_WORD 2 - -/* Width in bits of a pointer. - See also the macro `Pmode' defined below. - - This differs from Pmode because we need to allocate 32bits of space - to hold the 24bit pointers on this machine. */ -#define POINTER_SIZE 32 - -/* Allocation boundary (in *bits*) for storing arguments in argument list. */ -#define PARM_BOUNDARY 16 - -/* The stack goes in 16 bit lumps. */ -#define STACK_BOUNDARY 16 - -/* Allocation boundary (in *bits*) for the code of a function. - 8 is the minimum boundary; it's unclear if bigger alignments - would improve performance. */ -#define FUNCTION_BOUNDARY 8 - -/* No data type wants to be aligned rounder than this. */ -#define BIGGEST_ALIGNMENT 16 - -/* Alignment of field after `int : 0' in a structure. */ -#define EMPTY_FIELD_BOUNDARY 16 - -/* Seems to be how the Matsushita compiler does things, and there's - no real reason to be different. */ -#define STRUCTURE_SIZE_BOUNDARY 16 -#undef PCC_BITFIELD_TYPE_MATTERS - -/* Define this if move instructions will actually fail to work - when given unaligned data. */ -#define STRICT_ALIGNMENT 1 - -/* Define this as 1 if `char' should by default be signed; else as 0. */ -#define DEFAULT_SIGNED_CHAR 0 - -/* Standard register usage. */ - -/* Number of actual hardware registers. - The hardware registers are assigned numbers for the compiler - from 0 to just below FIRST_PSEUDO_REGISTER. - - All registers that the compiler knows about must be given numbers, - even those that are not normally considered general registers. - - XXX Long term we should probably expose the MDR register, we use - it for division, multiplication, and some extension operations. */ - -#define FIRST_PSEUDO_REGISTER 8 - -/* 1 for registers that have pervasive standard uses - and are not available for the register allocator. */ - -#define FIXED_REGISTERS \ - { 0, 0, 0, 0, 0, 0, 0, 1} - -/* 1 for registers not available across function calls. - These must include the FIXED_REGISTERS and also any - registers that can be used without being saved. - The latter must include the registers where values are returned - and the register where structure-value addresses are passed. - Aside from that, you can include as many other registers as you - like. */ - -#define CALL_USED_REGISTERS \ - { 1, 1, 0, 0, 1, 0, 0, 1} - -#define REG_ALLOC_ORDER \ - { 0, 1, 4, 2, 3, 5, 6, 7} - -/* Return number of consecutive hard regs needed starting at reg REGNO - to hold something of mode MODE. - - This is ordinarily the length in words of a value of mode MODE - but can be less for certain modes in special long registers. */ - -#define HARD_REGNO_NREGS(REGNO, MODE) \ - ((MODE) == PSImode ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ - / UNITS_PER_WORD)) - -/* Value is 1 if hard register REGNO can hold a value of machine-mode - MODE. - - We allow any register to hold a PSImode value. We allow any register - to hold values <= 16 bits. For values > 16 bits we require aligned - register pairs. */ -#define HARD_REGNO_MODE_OK(REGNO, MODE) \ - ((MODE) == PSImode ? 1 : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 2) - -/* Value is 1 if it is a good idea to tie two pseudo registers - when one has mode MODE1 and one has mode MODE2. - If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, - for any hard reg, then this must be 0 for correct output. */ -#define MODES_TIEABLE_P(MODE1, MODE2) \ - (MODE1 == MODE2 || (GET_MODE_SIZE (MODE1) <= 2 && GET_MODE_SIZE (MODE2) <= 2)) - -/* 4 data, and effectively 2 address registers is small as far as I'm - concerned. Especially since we use 2 data registers for argument - passing and return values. - - We used to define CLASS_LIKELY_SPILLED_P as true for DATA_REGS too, - but we've made improvements to the port which greatly reduce register - pressure. As a result we no longer need to define CLASS_LIKELY_SPILLED_P - for DATA_REGS (and by not defining it we get significantly better code). */ -#define SMALL_REGISTER_CLASSES 1 -#define CLASS_LIKELY_SPILLED_P(CLASS) (CLASS == ADDRESS_REGS) - -/* Define the classes of registers for register constraints in the - machine description. Also define ranges of constants. - - One of the classes must always be named ALL_REGS and include all hard regs. - If there is more than one class, another class must be named NO_REGS - and contain no registers. - - The name GENERAL_REGS must be the name of a class (or an alias for - another name such as ALL_REGS). This is the class of registers - that is allowed by "g" or "r" in a register constraint. - Also, registers outside this class are allocated only when - instructions express preferences for them. - - The classes must be numbered in nondecreasing order; that is, - a larger-numbered class must never be contained completely - in a smaller-numbered class. - - For any two classes, it is very desirable that there be another - class that represents their union. */ - -enum reg_class { - NO_REGS, DATA_REGS, ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES -}; - -#define N_REG_CLASSES (int) LIM_REG_CLASSES - -/* Give names of register classes as strings for dump file. */ - -#define REG_CLASS_NAMES \ -{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \ - "GENERAL_REGS", "ALL_REGS", "LIM_REGS" } - -/* Define which registers fit in which classes. - This is an initializer for a vector of HARD_REG_SET - of length N_REG_CLASSES. */ - -#define REG_CLASS_CONTENTS \ -{ {0}, /* No regs */ \ - {0x0f}, /* DATA_REGS */ \ - {0xf0}, /* ADDRESS_REGS */ \ - {0xff}, /* GENERAL_REGS */ \ - {0xff}, /* ALL_REGS */ \ -} - -/* The same information, inverted: - Return the class number of the smallest class containing - reg number REGNO. This could be a conditional expression - or could index an array. */ - -#define REGNO_REG_CLASS(REGNO) \ - ((REGNO) < 4 ? DATA_REGS : ADDRESS_REGS) - -/* The class value for index registers, and the one for base regs. */ - -#define INDEX_REG_CLASS DATA_REGS -#define BASE_REG_CLASS ADDRESS_REGS - -/* Get reg_class from a letter such as appears in the machine description. */ - -#define REG_CLASS_FROM_LETTER(C) \ - ((C) == 'd' ? DATA_REGS : \ - (C) == 'a' ? ADDRESS_REGS : NO_REGS) - -/* Macros to check register numbers against specific register classes. */ - -/* These assume that REGNO is a hard or pseudo reg number. - They give nonzero only if REGNO is a hard reg of the suitable class - or a pseudo reg currently allocated to a suitable hard reg. - Since they use reg_renumber, they are safe only once reg_renumber - has been allocated, which happens in local-alloc.c. */ - -#define REGNO_OK_FOR_BASE_P(regno) \ - (((regno) > 3 && regno < FIRST_PSEUDO_REGISTER) \ - || (reg_renumber[regno] > 3 && reg_renumber[regno] < FIRST_PSEUDO_REGISTER)) - -#define REGNO_OK_FOR_INDEX_P(regno) \ - (IN_RANGE ((regno), 0, 3) \ - || (reg_renumber[regno] >= 0 && reg_renumber[regno] < 4)) - - -/* Given an rtx X being reloaded into a reg required to be - in class CLASS, return the class of reg to actually use. - In general this is just CLASS; but on some machines - in some cases it is preferable to use a more restrictive class. */ - -#define PREFERRED_RELOAD_CLASS(X,CLASS) \ - ((GET_MODE (X) != PSImode && GET_MODE (X) != VOIDmode) ? DATA_REGS : CLASS) - -/* We want to use DATA_REGS for anything that is not PSImode. */ -#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ - ((MODE != PSImode && MODE != VOIDmode) ? DATA_REGS : CLASS) - -/* We have/need secondary reloads on the mn10200. Mostly to deal - with problems using address registers. */ -#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ - secondary_reload_class(CLASS,MODE,IN, 1) - -#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,IN) \ - secondary_reload_class(CLASS,MODE,IN, 0) - -/* Return the maximum number of consecutive registers - needed to represent mode MODE in a register of class CLASS. */ - -#define CLASS_MAX_NREGS(CLASS, MODE) \ - ((MODE) == PSImode ? 1 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) - -/* The letters I, J, K, L, M, N, O, P in a register constraint string - can be used to stand for particular ranges of immediate operands. - This macro defines what the ranges are. - C is the letter, and VALUE is a constant value. - Return 1 if VALUE is in the range specified by C. */ - -#define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100) -#define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000) - -#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0) -#define CONST_OK_FOR_J(VALUE) ((VALUE) >= 1 && (VALUE) <= 3) -#define CONST_OK_FOR_K(VALUE) ((VALUE) >= 1 && (VALUE) <= 4) -#define CONST_OK_FOR_L(VALUE) ((VALUE) == 15) -#define CONST_OK_FOR_M(VALUE) ((VALUE) == 255) - -#define CONST_OK_FOR_LETTER_P(VALUE, C) \ - ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \ - (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \ - (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \ - (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \ - (C) == 'M' ? CONST_OK_FOR_M (VALUE) : 0) - -/* Similar, but for floating constants, and defining letters G and H. - Here VALUE is the CONST_DOUBLE rtx itself. - - `G' is a floating-point zero. */ - -#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ - ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ - && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \ - : 0) - - - -/* Stack layout; function entry, exit and calling. */ - -/* Define this if pushing a word on the stack - makes the stack pointer a smaller address. */ - -#define STACK_GROWS_DOWNWARD - -/* Define this if the nominal address of the stack frame - is at the high-address end of the local variables; - that is, each additional local variable allocated - goes at a more negative offset in the frame. */ - -#define FRAME_GROWS_DOWNWARD - -/* Offset within stack frame to start allocating local variables at. - If FRAME_GROWS_DOWNWARD, this is the offset to the END of the - first local allocated. Otherwise, it is the offset to the BEGINNING - of the first local allocated. */ - -#define STARTING_FRAME_OFFSET 0 - -/* Offset of first parameter from the argument pointer register value. */ -/* Is equal to the size of the saved fp + pc, even if an fp isn't - saved since the value is used before we know. */ - -#define FIRST_PARM_OFFSET(FNDECL) (current_function_needs_context ? 8 : 4) - -/* Specify the registers used for certain standard purposes. - The values of these macros are register numbers. */ - -/* Register to use for pushing function arguments. */ -#define STACK_POINTER_REGNUM 7 - -/* Base register for access to local variables of the function. */ -#define FRAME_POINTER_REGNUM 6 - -/* Base register for access to arguments of the function. */ -#define ARG_POINTER_REGNUM 6 - -/* Register in which static-chain is passed to a function. */ -#define STATIC_CHAIN_REGNUM 4 - -/* Value should be nonzero if functions must have frame pointers. - Zero means the frame pointer need not be set up (and parms - may be accessed via the stack pointer) in functions that seem suitable. - This is computed in `reload', in reload1.c. - - We allow frame pointers to be eliminated when not having one will - not interfere with debugging. */ -#define ACCUMULATE_OUTGOING_ARGS 1 -#define FRAME_POINTER_REQUIRED 0 -#define CAN_DEBUG_WITHOUT_FP - -/* Store in the variable DEPTH the initial difference between the - frame pointer reg contents and the stack pointer reg contents, - as of the start of the function body. This depends on the layout - of the fixed parts of the stack frame and on how registers are saved. */ - -#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = total_frame_size() - -/* Various type size information. - - The mn10200 has a limited number of small registers. Sizes of basic - data types are adjusted accordingly. */ -#define SHORT_TYPE_SIZE 16 -#define INT_TYPE_SIZE 16 -#define LONG_TYPE_SIZE 32 -#define LONG_LONG_TYPE_SIZE 32 -#define FLOAT_TYPE_SIZE 32 -#define DOUBLE_TYPE_SIZE 32 -#define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE - -/* Any size less than 64bits will work; but a smarter definition - can make G++ code smaller and faster. Most operations on the - mn10200 occur on 16bit hunks, so the best size for a boolean - is 16bits. */ -#define BOOL_TYPE_SIZE 16 - -/* The difference of two pointers must be at least 24bits since pointers - are 24bits; however, no basic data type is 24bits, so we have to round - up to a 32bits for the difference of pointers. */ -#undef SIZE_TYPE -#undef PTRDIFF_TYPE -#define SIZE_TYPE "long unsigned int" -#define PTRDIFF_TYPE "long int" - -/* Note sizeof (WCHAR_TYPE) must be equal to the value of WCHAR_TYPE_SIZE! */ -#undef WCHAR_TYPE -#define WCHAR_TYPE "int" - -#undef WCHAR_TYPE_SIZE -#define WCHAR_TYPE_SIZE BITS_PER_WORD - -#define MAX_FIXED_MODE_SIZE 32 - -/* A guess for the MN10200. */ -#define PROMOTE_PROTOTYPES 1 - -/* Value is the number of bytes of arguments automatically - popped when returning from a subroutine call. - FUNDECL is the declaration node of the function (as a tree), - FUNTYPE is the data type of the function (as a tree), - or for a library call it is an identifier node for the subroutine name. - SIZE is the number of bytes of arguments passed on the stack. */ - -#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 - -/* 1 if N is a possible register number for function argument passing. */ - -#define FUNCTION_ARG_REGNO_P(N) ((N) <= 1) - -/* Define a data type for recording info about an argument list - during the scan of that argument list. This data type should - hold all necessary information about the function itself - and about the args processed so far, enough to enable macros - such as FUNCTION_ARG to determine where the next arg should go. */ - -#define CUMULATIVE_ARGS struct cum_arg -struct cum_arg { int nbytes; }; - -/* Initialize a variable CUM of type CUMULATIVE_ARGS - for a call to a function whose data type is FNTYPE. - For a library call, FNTYPE is 0. - - On the MN10200, the offset starts at 0. */ - -#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ - ((CUM).nbytes = 0) - -/* Update the data in CUM to advance over an argument - of mode MODE and data type TYPE. - (TYPE is null for libcalls where that information may not be available.) */ - -#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ - ((CUM).nbytes += ((MODE) != BLKmode \ - ? (MODE) == PSImode ? 2 : \ - (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD \ - : (int_size_in_bytes (TYPE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD)) - -/* Define where to put the arguments to a function. - Value is zero to push the argument on the stack, - or a hard register in which to store the argument. - - MODE is the argument's machine mode. - TYPE is the data type of the argument (as a tree). - This is null for libcalls where that information may - not be available. - CUM is a variable of type CUMULATIVE_ARGS which gives info about - the preceding args and about the function being called. - NAMED is nonzero if this argument is a named parameter - (otherwise it is an extra parameter matching an ellipsis). */ - -#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ - function_arg (&CUM, MODE, TYPE, NAMED) - -/* Implement `va_arg'. */ -#define EXPAND_BUILTIN_VA_ARG(valist, type) \ - mn10200_va_arg (valist, type) - -/* For "large" items, we pass them by invisible reference, and the - callee is responsible for copying the data item if it might be - modified. */ -#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ - ((TYPE) && int_size_in_bytes (TYPE) > 8) - -#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ - ((TYPE) && int_size_in_bytes (TYPE) > 8) - -/* Define how to find the value returned by a function. - VALTYPE is the data type of the value (as a tree). - If the precise function being called is known, FUNC is its FUNCTION_DECL; - otherwise, FUNC is 0. */ - -#define FUNCTION_VALUE(VALTYPE, FUNC) \ - gen_rtx_REG (TYPE_MODE (VALTYPE), TYPE_MODE (VALTYPE) == PSImode ? 4 : 0) - -/* Define how to find the value returned by a library function - assuming the value has mode MODE. */ - -#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, (MODE) == PSImode ? 4 : 0) - -/* 1 if N is a possible register number for a function value. */ - -#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 4) - -/* Return values > 8 bytes in length in memory. */ -#define DEFAULT_PCC_STRUCT_RETURN 0 -#define RETURN_IN_MEMORY(TYPE) \ - (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode) - -/* Register in which address to store a structure value - is passed to a function. On the MN10200 it's passed as - the first parameter. */ - -#define STRUCT_VALUE 0 - -/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, - the stack pointer does not matter. The value is tested only in - functions that have frame pointers. - No definition is equivalent to always zero. */ - -#define EXIT_IGNORE_STACK 1 - -/* Output assembler code to FILE to increment profiler label # LABELNO - for profiling a function entry. - - ?!? Profiling is not currently supported. */ - -#define FUNCTION_PROFILER(FILE, LABELNO) ; - -/* Yes, we actually support trampolines on this machine, even though - nobody is likely to ever use them. */ -#define TRAMPOLINE_TEMPLATE(FILE) \ - do { \ - fprintf (FILE, "\t.byte 0xfd\n"); \ - fprintf (FILE, "\t.byte 0x00\n"); \ - fprintf (FILE, "\t.byte 0x00\n"); \ - fprintf (FILE, "\tmov (a3),a0\n"); \ - fprintf (FILE, "\tadd -4,a3\n"); \ - fprintf (FILE, "\tmov a0,(0,a3)\n"); \ - fprintf (FILE, "\tmov (21,a0),a0\n"); \ - fprintf (FILE, "\tmov a0,(4,a3)\n"); \ - fprintf (FILE, "\tmov (0,a3),a0\n"); \ - fprintf (FILE, "\tmov (17,a0),a0\n"); \ - fprintf (FILE, "\tadd 4,a3\n"); \ - fprintf (FILE, "\trts\n"); \ - fprintf (FILE, "\t.long 0\n"); \ - fprintf (FILE, "\t.long 0\n"); \ - } while (0) - -/* Length in units of the trampoline for entering a nested function. */ - -#define TRAMPOLINE_SIZE 0x1c - -/* Emit RTL insns to initialize the variable parts of a trampoline. - FNADDR is an RTX for the address of the function's pure code. - CXT is an RTX for the static chain value for the function. */ - -#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -{ \ - emit_move_insn (gen_rtx_MEM (PSImode, plus_constant ((TRAMP), 20)), \ - (CXT)); \ - emit_move_insn (gen_rtx_MEM (PSImode, plus_constant ((TRAMP), 24)), \ - (FNADDR)); \ -} - -/* A C expression whose value is RTL representing the value of the return - address for the frame COUNT steps up from the current frame. */ - -#define RETURN_ADDR_RTX(COUNT, FRAME) \ - ((COUNT == 0) \ - ? gen_rtx_MEM (Pmode, frame_pointer_rtx) \ - : (rtx) 0) - - -/* Addressing modes, and classification of registers for them. */ - - -/* 1 if X is an rtx for a constant that is a valid address. */ - -#define CONSTANT_ADDRESS_P(X) CONSTANT_P (X) - -/* Extra constraints. */ -#define OK_FOR_R(OP) \ - (GET_CODE (OP) == MEM \ - && GET_MODE (OP) == QImode \ - && REG_P (XEXP (OP, 0))) - -/* Q is used for sp + <something> in the {zero,sign}_extendpsisi2 patterns. */ -#define EXTRA_CONSTRAINT(OP, C) \ - ((C) == 'R' ? OK_FOR_R (OP) : \ - (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF : \ - (C) == 'Q' ? GET_CODE (OP) == PLUS : 0) - -/* Maximum number of registers that can appear in a valid memory address. */ - -#define MAX_REGS_PER_ADDRESS 2 - -/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx - and check its validity for a certain class. - We have two alternate definitions for each of them. - The usual definition accepts all pseudo regs; the other rejects - them unless they have been allocated suitable hard regs. - The symbol REG_OK_STRICT causes the latter definition to be used. - - Most source files want to accept pseudo regs in the hope that - they will get allocated to the class that the insn wants them to be in. - Source files for reload pass need to be strict. - After reload, it makes no difference, since pseudo regs have - been eliminated by then. */ - -#ifndef REG_OK_STRICT -/* Nonzero if X is a hard reg that can be used as an index - or if it is a pseudo reg. */ -#define REG_OK_FOR_INDEX_P(X) \ - (IN_RANGE (REGNO (X), 0, 3) || REGNO (X) >= FIRST_PSEUDO_REGISTER) -/* Nonzero if X is a hard reg that can be used as a base reg - or if it is a pseudo reg. */ -#define REG_OK_FOR_BASE_P(X) \ - (((REGNO (X) >= 4 && REGNO(X) <= 8) || REGNO (X) >= FIRST_PSEUDO_REGISTER)) -#else -/* Nonzero if X is a hard reg that can be used as an index. */ -#define REG_OK_FOR_INDEX_P(X) \ - REGNO_OK_FOR_INDEX_P (REGNO (X)) -/* Nonzero if X is a hard reg that can be used as a base reg. */ -#define REG_OK_FOR_BASE_P(X) \ - REGNO_OK_FOR_BASE_P (REGNO (X)) -#endif - - -/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression - that is a valid memory address for an instruction. - The MODE argument is the machine mode for the MEM expression - that wants to use this address. - - We used to allow reg+reg addresses for QImode and HImode; however, - they tended to cause the register allocator to run out of registers. - Basically, an indexed load/store always keeps 2 data and one address - register live, which is just too many for this machine. - - The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, - except for CONSTANT_ADDRESS_P which is actually machine-independent. */ - -/* Accept either REG or SUBREG where a register is valid. */ - -#define RTX_OK_FOR_BASE_P(X) \ - ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \ - || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \ - && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) - -#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -{ \ - if ((MODE != PSImode) && CONSTANT_ADDRESS_P (X)) \ - goto ADDR; \ - if (RTX_OK_FOR_BASE_P (X)) \ - goto ADDR; \ - if (GET_CODE (X) == PLUS) \ - { \ - rtx base = 0, index = 0; \ - if (RTX_OK_FOR_BASE_P (XEXP (X, 0))) \ - base = XEXP (X, 0), index = XEXP (X, 1); \ - if (RTX_OK_FOR_BASE_P (XEXP (X, 1))) \ - base = XEXP (X, 1), index = XEXP (X, 0); \ - if (base != 0 && index != 0) \ - { \ - if (GET_CODE (index) == CONST_INT) \ - goto ADDR; \ - } \ - } \ -} - - -/* Try machine-dependent ways of modifying an illegitimate address - to be legitimate. If we find one, return the new, valid address. - This macro is used in only one place: `memory_address' in explow.c. - - OLDX is the address as it was before break_out_memory_refs was called. - In some cases it is useful to look at this to decide what needs to be done. - - MODE and WIN are passed so that this macro can use - GO_IF_LEGITIMATE_ADDRESS. - - It is always safe for this macro to do nothing. It exists to recognize - opportunities to optimize the output. */ - -#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} - -/* Go to LABEL if ADDR (a legitimate address expression) - has an effect that depends on the machine mode it is used for. */ - -#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {} - -/* Nonzero if the constant value X is a legitimate general operand. - It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ - -#define LEGITIMATE_CONSTANT_P(X) 1 - - -/* Tell final.c how to eliminate redundant test instructions. */ - -/* Here we define machine-dependent flags and fields in cc_status - (see `conditions.h'). No extra ones are needed for the VAX. */ - -/* Store in cc_status the expressions - that the condition codes will describe - after execution of an instruction whose pattern is EXP. - Do not alter them if the instruction would not alter the cc's. */ - -#define CC_OVERFLOW_UNUSABLE 0x200 -#define CC_NO_CARRY CC_NO_OVERFLOW -#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN) - -/* The mn10200 has a limited number of registers, so CSE of function - addresses generally makes code worse due to register pressure. */ -#define NO_FUNCTION_CSE - -/* Make moves between different classes more expensive than moves - within the same class. */ -#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) (CLASS1 != CLASS2 ? 4 : 2) - -/* Nonzero if access to memory by bytes or half words is no faster - than accessing full words. */ -#define SLOW_BYTE_ACCESS 1 - -/* According expr.c, a value of around 6 should minimize code size, and - for the MN10200 series, code size our primary concern. */ -#define MOVE_RATIO 6 - -#define TEXT_SECTION_ASM_OP "\t.section .text" -#define DATA_SECTION_ASM_OP "\t.section .data" -#define BSS_SECTION_ASM_OP "\t.section .bss" - -/* Output at beginning/end of assembler file. */ -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) asm_file_start(FILE) - -#define ASM_COMMENT_START "#" - -/* Output to assembler file text saying following lines - may contain character constants, extra white space, comments, etc. */ - -#define ASM_APP_ON "#APP\n" - -/* Output to assembler file text saying following lines - no longer contain unusual constructs. */ - -#define ASM_APP_OFF "#NO_APP\n" - -/* This says how to output the assembler to define a global - uninitialized but not common symbol. - Try to use asm_output_bss to implement this macro. */ - -#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ - asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) - -/* Globalizing directive for a label. */ -#define GLOBAL_ASM_OP "\t.global " - -/* This is how to output a reference to a user-level label named NAME. - `assemble_name' uses this. */ - -#undef ASM_OUTPUT_LABELREF -#define ASM_OUTPUT_LABELREF(FILE, NAME) \ - fprintf (FILE, "_%s", (*targetm.strip_name_encoding) (NAME)) - -#define ASM_PN_FORMAT "%s___%lu" - -/* This is how we tell the assembler that two symbols have the same value. */ - -#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \ - do { assemble_name(FILE, NAME1); \ - fputs(" = ", FILE); \ - assemble_name(FILE, NAME2); \ - fputc('\n', FILE); } while (0) - - -/* How to refer to registers in assembler output. - This sequence is indexed by compiler's hard-register-number (see above). */ - -#define REGISTER_NAMES \ -{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3"} - -/* Print an instruction operand X on file FILE. - look in mn10200.c for details */ - -#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE,X,CODE) - -/* Print a memory operand whose address is X, on file FILE. - This uses a function in output-vax.c. */ - -#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) - -#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) -#define ASM_OUTPUT_REG_POP(FILE,REGNO) - -/* This is how to output an element of a case-vector that is absolute. */ - -#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ - fprintf (FILE, "\t%s .L%d\n", ".long", VALUE) - -/* This is how to output an element of a case-vector that is relative. */ - -#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ - fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) - -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ - if ((LOG) != 0) \ - fprintf (FILE, "\t.align %d\n", (LOG)) - -/* We don't have to worry about dbx compatibility for the mn10200. */ -#define DEFAULT_GDB_EXTENSIONS 1 - -/* Use stabs debugging info by default. */ -#undef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG - -/* GDB always assumes the current function's frame begins at the value - of the stack pointer upon entry to the current function. Accessing - local variables and parameters passed on the stack is done using the - base of the frame + an offset provided by GCC. - - For functions which have frame pointers this method works fine; - the (frame pointer) == (stack pointer at function entry) and GCC provides - an offset relative to the frame pointer. - - This loses for functions without a frame pointer; GCC provides an offset - which is relative to the stack pointer after adjusting for the function's - frame size. GDB would prefer the offset to be relative to the value of - the stack pointer at the function's entry. Yuk! */ -#define DEBUGGER_AUTO_OFFSET(X) \ - ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \ - + (frame_pointer_needed ? 0 : -total_frame_size ())) - -#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ - ((GET_CODE (X) == PLUS ? OFFSET : 0) \ - + (frame_pointer_needed ? 0 : -total_frame_size ())) - -/* Specify the machine mode that this machine uses - for the index in the tablejump instruction. */ -#define CASE_VECTOR_MODE Pmode - -/* Dispatch tables on the mn10200 are extremely expensive in terms of code - and readonly data size. So we crank up the case threshold value to - encourage a series of if/else comparisons to implement many small switch - statements. In theory, this value could be increased much more if we - were solely optimizing for space, but we keep it "reasonable" to avoid - serious code efficiency lossage. */ -#define CASE_VALUES_THRESHOLD 8 - -/* Define if operations between registers always perform the operation - on the full register even if a narrower mode is specified. */ -#define WORD_REGISTER_OPERATIONS - -/* We could define this either way. Using ZERO_EXTEND for QImode makes slightly - fast and more compact code. */ -#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND - -/* This flag, if defined, says the same insns that convert to a signed fixnum - also convert validly to an unsigned one. */ -#define FIXUNS_TRUNC_LIKE_FIX_TRUNC - -/* Max number of bytes we can move from memory to memory - in one reasonably fast instruction. */ -#define MOVE_MAX 2 - -/* Define if shifts truncate the shift count - which implies one can omit a sign-extension or zero-extension - of a shift count. */ -#define SHIFT_COUNT_TRUNCATED 1 - -/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits - is done just by pretending it is already truncated. */ -#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) (OUTPREC != 32) - -/* Specify the machine mode that pointers have. - After generation of rtl, the compiler makes no further distinction - between pointers and any other objects of this machine mode. */ -#define Pmode PSImode - -/* A function address in a call instruction - is a byte address (for indexing purposes) - so give the MEM rtx a byte's mode. */ -#define FUNCTION_MODE QImode - -/* Perform target dependent optabs initialization. */ -#define MODHI3_LIBCALL "__modhi3" -#define DIVHI3_LIBCALL "__divhi3" - -#define INIT_TARGET_OPTABS \ - do { \ - sdiv_optab->handlers[(int) HImode].libfunc \ - = init_one_libfunc (DIVHI3_LIBCALL); \ - smod_optab->handlers[(int) HImode].libfunc \ - = init_one_libfunc (MODHI3_LIBCALL); \ - } while (0) - -/* The assembler op to get a word. */ - -#define FILE_ASM_OP "\t.file\n" - -#define PREDICATE_CODES \ - {"call_address_operand", { SYMBOL_REF, REG }}, \ - {"constant_memory_operand", { MEM }}, \ - {"psimode_truncation_operand",{ PLUS, CONST_INT, CONST_DOUBLE, CONST, \ - SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM }},\ - {"extendpsi_operand", { PLUS, CONST_INT, CONST_DOUBLE, CONST, \ - SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM }}, \ - {"nshift_operator", { ASHIFTRT, LSHIFTRT, ASHIFT }}, - -extern GTY(()) rtx zero_dreg; -extern GTY(()) rtx zero_areg; diff --git a/gcc/config/mn10200/mn10200.md b/gcc/config/mn10200/mn10200.md deleted file mode 100644 index ea658fdb31c..00000000000 --- a/gcc/config/mn10200/mn10200.md +++ /dev/null @@ -1,2050 +0,0 @@ -;; GCC machine description for Matsushita MN10200 -;; Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation, Inc. -;; Contributed by Jeff Law (law@cygnus.com). - -;; This file is part of GNU CC. - -;; GNU CC is free software; you can redistribute it and/or modify -;; it under the terms of the GNU General Public License as published by -;; the Free Software Foundation; either version 2, or (at your option) -;; any later version. - -;; GNU CC is distributed in the hope that it will be useful, -;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;; GNU General Public License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GNU CC; see the file COPYING. If not, write to -;; the Free Software Foundation, 59 Temple Place - Suite 330, -;; Boston, MA 02111-1307, USA. - -;; The original PO technology requires these to be ordered by speed, -;; so that assigner will pick the fastest. - -;; See file "rtl.def" for documentation on define_insn, match_*, et. al. - -;; Condition code settings. -;; none - insn does not affect cc -;; none_0hit - insn does not affect cc but it does modify operand 0 -;; This attribute is used to keep track of when operand 0 changes. -;; See the description of NOTICE_UPDATE_CC for more info. -;; set_znv - sets z,n,v to usable values; c is unknown. -;; set_zn - sets z,n to usable values; v,c is unknown. -;; compare - compare instruction -;; clobber - value of cc is unknown -(define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber" - (const_string "clobber")) - -;; ---------------------------------------------------------------------- -;; MOVE INSTRUCTIONS -;; ---------------------------------------------------------------------- -;; -;; Some general notes on move instructions. -;; -;; The hardware can't encode nop moves involving data registers, so -;; we catch them and emit a nop instead. -;; -;; Loads/stores to/from address registers must be 16bit aligned, -;; thus we avoid them for QImode. -;; -;; Stores from address registers always store 24bits, so avoid -;; stores from address registers in HImode, SImode, and SFmode. -;; -;; As a result of the various problems using address registers in -;; QImode, HImode, SImode, and SFmode, we discourage their use via -;; '*' in their constraints. They're still allowed, but they're never -;; the preferred class for insns with those modes. - -;; movqi - -(define_expand "movqi" - [(set (match_operand:QI 0 "general_operand" "") - (match_operand:QI 1 "general_operand" ""))] - "" - " -{ - /* One of the ops has to be in a register */ - if (!register_operand (operand0, QImode) - && !register_operand (operand1, QImode)) - operands[1] = copy_to_mode_reg (QImode, operand1); -}") - -;; We avoid memory operations involving address registers because we -;; can't be sure they'll be suitably aligned. -;; -;; We also discourage holding QImode values in address registers. -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d,d,*a,d,d,m,d,*a,*a") - (match_operand:QI 1 "general_operand" "0,I,I,di,m,d,*a,d,i*a"))] - "register_operand (operands[0], QImode) - || register_operand (operands[1], QImode)" - "@ - nop - sub %0,%0 - sub %0,%0 - mov %S1,%0 - movbu %1,%0 - movb %1,%0 - mov %1,%0 - mov %1,%0 - mov %1,%0" - [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")]) - -;; movhi - -(define_expand "movhi" - [(set (match_operand:HI 0 "general_operand" "") - (match_operand:HI 1 "general_operand" ""))] - "" - " -{ - /* One of the ops has to be in a register */ - if (!register_operand (operand1, HImode) - && !register_operand (operand0, HImode)) - operands[1] = copy_to_mode_reg (HImode, operand1); -}") - -(define_insn "" - [(set (match_operand:HI 0 "general_operand" "=d,d,*a,d,d,m,d,*a,*a,*a") - (match_operand:HI 1 "general_operand" "0,I,I,di,m,d,*a,d,i*a,m"))] - "register_operand (operands[0], HImode) - || register_operand (operands[1], HImode)" - "@ - nop - sub %0,%0 - sub %0,%0 - mov %s1,%0 - mov %1,%0 - mov %1,%0 - mov %1,%0 - mov %1,%0 - mov %1,%0 - mov %A1,%0" - [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")]) - -;; movpsi and helpers - -(define_expand "movpsi" - [(set (match_operand:PSI 0 "general_operand" "") - (match_operand:PSI 1 "general_operand" ""))] - "" - " -{ - /* One of the ops has to be in a register */ - if (!register_operand (operand1, PSImode) - && !register_operand (operand0, PSImode)) - operands[1] = copy_to_mode_reg (PSImode, operand1); -}") - - -;; Constant and indexed addresses are not valid addresses for PSImode, -;; therefore they won't be matched by the general movpsi pattern below. -;; ??? We had patterns to handle indexed addresses, but they kept making -;; us run out of regs, so they were eliminated. - -(define_insn "" - [(set (match_operand:PSI 0 "register_operand" "=a") - (match_operand:PSI 1 "constant_memory_operand" ""))] - "" - "mov %A1,%0" - [(set_attr "cc" "none_0hit")]) - -(define_insn "" - [(set (match_operand:PSI 0 "constant_memory_operand" "=X") - (match_operand:PSI 1 "register_operand" "a"))] - "" - "mov %1,%A0" - [(set_attr "cc" "none_0hit")]) - -;; We want to prefer address registers here because 24bit moves to/from -;; memory are shorter and faster when done via address registers. -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,a?d,?da,a,m,?d,m") - (match_operand:PSI 1 "general_operand" "0,I,?dai,m,a,m,?d"))] - "register_operand (operands[0], PSImode) - || register_operand (operands[1], PSImode)" - "@ - nop - sub %0,%0 - mov %1,%0 - mov %A1,%0 - mov %1,%A0 - movx %A1,%0 - movx %1,%A0" - [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")]) - -(define_expand "movsi" - [(set (match_operand:SI 0 "general_operand" "") - (match_operand:SI 1 "general_operand" ""))] - "" - " -{ - /* One of the ops has to be in a register */ - if (!register_operand (operand1, SImode) - && !register_operand (operand0, SImode)) - operands[1] = copy_to_mode_reg (SImode, operand1); -}") - -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=d,d,*a,dm,d,d,*a,*a,*a") - (match_operand:SI 1 "general_operand" "0,I,I,d,dim,*a,d,*a,i"))] - "register_operand (operands[0], SImode) - || register_operand (operands[1], SImode)" - "* -{ - switch (which_alternative) - { - case 0: - return \"nop\"; - case 1: - case 2: - return \"sub %H0,%H0\;sub %L0,%L0\"; - case 3: - case 5: - case 6: - case 7: - return \"mov %H1,%H0\;mov %L1,%L0\"; - - /* The next two cases try to optimize cases where one half - of the constant is all zeros, or when the two halves are - the same. */ - case 4: - case 8: - if (REG_P (operands[0]) - && GET_CODE (operands[1]) == CONST_INT - && (INTVAL (operands[1]) & 0xffff0000) == 0) - output_asm_insn (\"sub %H0,%H0\", operands); - else - output_asm_insn (\"mov %h1,%H0\", operands); - - if (GET_CODE (operands[1]) == CONST_INT - && ((INTVAL (operands[1]) & 0xffff) - == ((INTVAL (operands[1]) >> 16) & 0xffff))) - output_asm_insn (\"mov %H0,%L0\", operands); - else if (GET_CODE (operands[1]) == CONST_INT - && (INTVAL (operands[1]) & 0xffff) == 0) - output_asm_insn (\"sub %L0,%L0\", operands); - else - output_asm_insn (\"mov %o1,%L0\", operands); - return \"\"; - default: - abort(); - } -}" - [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")]) - -(define_expand "movsf" - [(set (match_operand:SF 0 "general_operand" "") - (match_operand:SF 1 "general_operand" ""))] - "" - " -{ - /* One of the ops has to be in a register */ - if (!register_operand (operand1, SFmode) - && !register_operand (operand0, SFmode)) - operands[1] = copy_to_mode_reg (SFmode, operand1); -}") - -(define_insn "" - [(set (match_operand:SF 0 "general_operand" "=d,d,*a,dm,d,d,*a,*a,*a") - (match_operand:SF 1 "general_operand" "0,G,G,d,dim,*a,d,*a,i"))] - "register_operand (operands[0], SFmode) - || register_operand (operands[1], SFmode)" - "* -{ - switch (which_alternative) - { - case 0: - return \"nop\"; - - case 1: - case 2: - return \"sub %H0,%H0\;sub %L0,%L0\"; - - default: - { - long val = 0; - REAL_VALUE_TYPE rv; - - if (GET_CODE (operands[1]) == CONST_DOUBLE) - { - REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); - REAL_VALUE_TO_TARGET_SINGLE (rv, val); - } - - if (GET_CODE (operands[1]) == CONST_INT) - val = INTVAL (operands[1]); - - if ((GET_CODE (operands[1]) == CONST_INT - || GET_CODE (operands[1]) == CONST_DOUBLE) - && (val & 0xffff0000) == 0) - output_asm_insn (\"sub %H0,%H0\", operands); - else - output_asm_insn (\"mov %h1,%H0\", operands); - - if (GET_CODE (operands[1]) == CONST_INT - && ((INTVAL (operands[1]) & 0xffff) - == ((INTVAL (operands[1]) >> 16) & 0xffff))) - output_asm_insn (\"mov %H0,%L0\", operands); - else if ((GET_CODE (operands[1]) == CONST_INT - || GET_CODE (operands[1]) == CONST_DOUBLE) - && (val & 0x0000ffff) == 0) - output_asm_insn (\"sub %L0,%L0\", operands); - else - output_asm_insn (\"mov %o1,%L0\", operands); - return \"\"; - } - } -}" - [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")]) - - -;; ---------------------------------------------------------------------- -;; TEST INSTRUCTIONS -;; ---------------------------------------------------------------------- - -;; Go ahead and define tsthi and tstpsi so we can eliminate redundant tst insns -;; when we start trying to optimize this port. -(define_insn "tsthi" - [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "da"))] - "" - "* return output_tst (operands[0], insn);" - [(set_attr "cc" "set_znv")]) - -(define_insn "tstpsi" - [(set (cc0) (match_operand:PSI 0 "nonimmediate_operand" "da"))] - "" - "* return output_tst (operands[0], insn);" - [(set_attr "cc" "set_znv")]) - -(define_insn "" - [(set (cc0) (zero_extend:HI (match_operand:QI 0 "memory_operand" "d")))] - "" - "* return output_tst (operands[0], insn);" - [(set_attr "cc" "set_znv")]) - -(define_insn "" - [(set (cc0) (zero_extend:PSI (match_operand:QI 0 "memory_operand" "d")))] - "" - "* return output_tst (operands[0], insn);" - [(set_attr "cc" "set_znv")]) - -(define_insn "cmphi" - [(set (cc0) - (compare:HI (match_operand:HI 0 "nonimmediate_operand" "da") - (match_operand:HI 1 "general_operand" "dai")))] - "" - "cmp %1,%0" - [(set_attr "cc" "compare")]) - -(define_insn "cmppsi" - [(set (cc0) - (compare:PSI (match_operand:PSI 0 "nonimmediate_operand" "da") - (match_operand:PSI 1 "general_operand" "dai")))] - "" - "cmp %1,%0" - [(set_attr "cc" "compare")]) - -;; ---------------------------------------------------------------------- -;; ADD INSTRUCTIONS -;; ---------------------------------------------------------------------- - -(define_insn "addhi3" - [(set (match_operand:HI 0 "general_operand" "=d") - (plus:HI (match_operand:HI 1 "general_operand" "%0") - (match_operand:HI 2 "general_operand" "dai")))] - "" - "add %2,%0" - [(set_attr "cc" "set_zn")]) - -(define_insn "addpsi3" - [(set (match_operand:PSI 0 "general_operand" "=da") - (plus:PSI (match_operand:PSI 1 "general_operand" "%0") - (match_operand:PSI 2 "general_operand" "dai")))] - "" - "add %2,%0" - [(set_attr "cc" "set_zn")]) - -;; We want to avoid using explicit registers; reload won't tell us -;; if it has to spill them and may generate incorrect code in such -;; cases. -;; -;; So we call out to a library routine to perform 32bit add or -;; subtract operations. -;; -;; operand2 must be nonmemory_operand so that we will accept CONST_INTs -;; during initial code generation. -(define_expand "addsi3" - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" "")))] - "" - " -{ - /* If adding a CONST_INT, we are better off generating code ourselves. - - During RTL generation we call out to library routines. - - After RTL generation we can not call the library routines as - they need to push arguments via virtual_outgoing_args_rtx which - has already been instantiated. So, after RTL generation we just - FAIL and open code the operation. */ - if (GET_CODE (operands[2]) == CONST_INT) - { - if (!rtx_equal_p (operands[0], operands[1])) - emit_move_insn (operands[0], operands[1]); - emit_insn (gen_addsi3_const (operands[0], operands[0], operands[2])); - DONE; - } - else if (rtx_equal_function_value_matters) - { - rtx ret, insns; - - start_sequence (); - ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__addsi3\"), - NULL_RTX, 1, SImode, 2, operands[1], - SImode, operands[2], SImode); - insns = get_insns (); - end_sequence (); - emit_libcall_block (insns, operands[0], ret, - gen_rtx_PLUS (SImode, operands[1], operands[2])); - DONE; - } - else - FAIL; -}") - -(define_insn "addsi3_const" - [(set (match_operand:SI 0 "register_operand" "=d") - (plus:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "const_int_operand" "i"))) - (clobber (match_scratch:SI 3 "=&d"))] - "" - "* -{ - unsigned long value = INTVAL (operands[2]); - - /* If only the high bits are set in the constant, then we only - need a single add operation. It might be better to catch this - at RTL expansion time. */ - if ((value & 0xffff) == 0) - return \"add %h2,%H0\"; - - value >>= 16; - value &= 0xffff; - - if (value == 0) - return \"sub %3,%3\;add %o2,%L0\;addc %3,%H0\"; - else - return \"mov %h2,%3\;add %o2,%L0\;addc %3,%H0\"; -}" - [(set_attr "cc" "clobber")]) - -;; ---------------------------------------------------------------------- -;; SUBTRACT INSTRUCTIONS -;; ---------------------------------------------------------------------- - -(define_insn "subhi3" - [(set (match_operand:HI 0 "general_operand" "=d") - (minus:HI (match_operand:HI 1 "general_operand" "0") - (match_operand:HI 2 "general_operand" "dai")))] - "" - "sub %2,%0" - [(set_attr "cc" "set_zn")]) - -(define_insn "subpsi3" - [(set (match_operand:PSI 0 "general_operand" "=da") - (minus:PSI (match_operand:PSI 1 "general_operand" "0") - (match_operand:PSI 2 "general_operand" "dai")))] - "" - "sub %2,%0" - [(set_attr "cc" "set_zn")]) - -(define_expand "subsi3" - [(set (match_operand:SI 0 "register_operand" "") - (minus:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "register_operand" "")))] - "" - " -{ - /* During RTL generation we call out to library routines. - - After RTL generation we can not call the library routines as - they need to push arguments via virtual_outgoing_args_rtx which - has already been instantiated. So, after RTL generation we just - FAIL and open code the operation. */ - if (rtx_equal_function_value_matters) - { - rtx ret, insns; - - start_sequence (); - ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__subsi3\"), - NULL_RTX, 1, SImode, 2, operands[1], - SImode, operands[2], SImode); - insns = get_insns (); - end_sequence (); - emit_libcall_block (insns, operands[0], ret, - gen_rtx_MINUS (SImode, operands[1], operands[2])); - DONE; - } - else - FAIL; -}") - -;; There isn't a negate instruction, so we fake it. -;; -;; We used to expand this into patterns, but a single pattern -;; actually generates better overall code. -;; -;; We could do HImode negations with a "not;add" sequence, but -;; generally it's generated slightly worse code. -;; -;; The second alternative is not strictly necesasry, but helps -;; when the register allocators start running short of registers. -(define_insn "neghi2" - [(set (match_operand:HI 0 "general_operand" "=&d,d") - (neg:HI (match_operand:HI 1 "general_operand" "d,0")))] - "" - "@ - sub %0,%0\;sub %1,%0 - not %0\;add 1,%0" - [(set_attr "cc" "set_zn")]) - -;; The not/and sequence won't work here. It's not clear if we'll -;; ever need to provide an alternate sequence since this should -;; be used much less frequently than neghi2. -(define_insn "negpsi2" - [(set (match_operand:PSI 0 "general_operand" "=&d") - (neg:PSI (match_operand:PSI 1 "general_operand" "d")))] - "" - "sub %0,%0\;sub %1,%0" - [(set_attr "cc" "set_zn")]) - -;; Using a magic libcall that accepts its arguments in any -;; data register pair has proven to be the most efficient -;; and most compact way to represent negsi2. -(define_insn "negsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (neg:SI (match_operand:SI 1 "register_operand" "0")))] - "" - "jsr ___negsi2_%0" - [(set_attr "cc" "clobber")]) - -;; ---------------------------------------------------------------------- -;; MULTIPLY INSTRUCTIONS -;; ---------------------------------------------------------------------- -;; -;; The mn10200 has HIxHI->SI widening multiply, but we get _severe_ -;; code density regressions if we enable such a pattern. - -(define_insn "mulhi3" - [(set (match_operand:HI 0 "general_operand" "=d") - (mult:HI (match_operand:HI 1 "general_operand" "%0") - (match_operand:HI 2 "general_operand" "d")))] - "" - "mul %2,%0" - [(set_attr "cc" "set_zn")]) - -(define_insn "udivmodhi4" - [(set (match_operand:HI 0 "general_operand" "=d") - (udiv:HI (match_operand:HI 1 "general_operand" "0") - (match_operand:HI 2 "general_operand" "d"))) - (set (match_operand:HI 3 "general_operand" "=&d") - (umod:HI (match_dup 1) (match_dup 2)))] - "" - "* -{ - if (zero_dreg) - output_asm_insn (\"mov %0,mdr\", &zero_dreg); - else - output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands); - - if (find_reg_note (insn, REG_UNUSED, operands[3])) - return \"divu %2,%0\"; - else - return \"divu %2,%0\;mov mdr,%3\"; -}" - [(set_attr "cc" "set_zn")]) - - -;; ---------------------------------------------------------------------- -;; AND INSTRUCTIONS -;; ---------------------------------------------------------------------- - -(define_insn "andhi3" - [(set (match_operand:HI 0 "general_operand" "=d,d") - (and:HI (match_operand:HI 1 "general_operand" "%0,0") - (match_operand:HI 2 "general_operand" "M,di")))] - "" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff) - return \"extxbu %0\"; - if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fff) - return \"add %0,%0\;lsr %0\"; - if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffe) - return \"lsr %0\;add %0,%0\"; - return \"and %2,%0\"; -}" - [(set_attr "cc" "none_0hit,set_znv")]) - -;; This expander + pattern exist only to allow trampolines to be aligned -;; in the stack. -(define_expand "andpsi3" - [(set (match_operand:PSI 0 "general_operand" "") - (and:PSI (match_operand:PSI 1 "general_operand" "") - (match_operand:PSI 2 "const_int_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) != CONST_INT - || (INTVAL (operands[2]) & 0xff0000) != 0xff0000) - FAIL; -}") - -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d") - (and:PSI (match_operand:PSI 1 "general_operand" "%0") - (match_operand:PSI 2 "const_int_operand" "i")))] - "GET_CODE (operands[2]) == CONST_INT - && (INTVAL (operands[2]) & 0xff0000) == 0xff0000" - "and %2,%0" - [(set_attr "cc" "clobber")]) - -;; ---------------------------------------------------------------------- -;; OR INSTRUCTIONS -;; ---------------------------------------------------------------------- - -(define_insn "iorhi3" - [(set (match_operand:HI 0 "general_operand" "=d") - (ior:HI (match_operand:HI 1 "general_operand" "%0") - (match_operand:HI 2 "general_operand" "di")))] - "" - "or %2,%0" - [(set_attr "cc" "set_znv")]) - -;; ---------------------------------------------------------------------- -;; XOR INSTRUCTIONS -;; ---------------------------------------------------------------------- - -(define_insn "xorhi3" - [(set (match_operand:HI 0 "general_operand" "=d") - (xor:HI (match_operand:HI 1 "general_operand" "%0") - (match_operand:HI 2 "general_operand" "di")))] - "" - "xor %2,%0" - [(set_attr "cc" "set_znv")]) - -;; ---------------------------------------------------------------------- -;; NOT INSTRUCTIONS -;; ---------------------------------------------------------------------- - -(define_insn "one_cmplhi2" - [(set (match_operand:HI 0 "general_operand" "=d") - (not:HI (match_operand:HI 1 "general_operand" "0")))] - "" - "not %0" - [(set_attr "cc" "set_znv")]) - - -;; ----------------------------------------------------------------- -;; BIT INSTRUCTIONS -;; ----------------------------------------------------------------- - -;; These clears a constant set of bits in memory or in a register. -;; We must support register destinations to make reload happy. -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "+R,d") - (subreg:QI - (and:HI (subreg:HI (match_dup 0) 0) - (match_operand 1 "const_int_operand" "")) 0)) - (clobber (match_scratch:HI 2 "=&d,X"))] - "" - "@ - mov %N1,%2\;bclr %2,%0 - and %1,%0" - [(set_attr "cc" "clobber")]) - -;; This clears a variable set of bits in memory or in a register. -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "+R,d") - (subreg:QI - (and:HI (subreg:HI (match_dup 0) 0) - (not:HI (match_operand:HI 1 "general_operand" "d,d"))) 0)) - (clobber (match_scratch:HI 2 "=X,&d"))] - "" - "@ - bclr %1,%0 - mov %1,%2\;not %2\;and %2,%0" - [(set_attr "cc" "clobber")]) - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "+R,d") - (subreg:QI - (and:HI (not:HI (match_operand:HI 1 "general_operand" "d,d")) - (subreg:HI (match_dup 0) 0)) 0)) - (clobber (match_scratch:HI 2 "=X,&d"))] - "" - "@ - bclr %1,%0 - mov %1,%2\;not %2\;and %2,%0" - [(set_attr "cc" "clobber")]) - -;; These set bits in memory. -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "+R,d") - (subreg:QI - (ior:HI (subreg:HI (match_dup 0) 0) - (match_operand:HI 1 "general_operand" "d,d")) 0))] - "" - "@ - bset %1,%0 - or %1,%0" - [(set_attr "cc" "clobber")]) - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "+R,d") - (subreg:QI - (ior:HI (match_operand:HI 1 "general_operand" "d,d") - (subreg:HI (match_dup 0) 0)) 0))] - "" - "@ - bset %1,%0 - or %1,%0" - [(set_attr "cc" "clobber")]) - -;; Not any shorter/faster than using cmp, but it might save a -;; register if the result of the AND isn't ever used. - -(define_insn "" - [(set (cc0) - (zero_extract:HI (match_operand:HI 0 "general_operand" "d") - (match_operand 1 "const_int_operand" "") - (match_operand 2 "const_int_operand" "")))] - "" - "* -{ - int len = INTVAL (operands[1]); - int bit = INTVAL (operands[2]); - int mask = 0; - rtx xoperands[2]; - - while (len > 0) - { - mask |= (1 << bit); - bit++; - len--; - } - - xoperands[0] = operands[0]; - xoperands[1] = GEN_INT (mask); - output_asm_insn (\"btst %1,%0\", xoperands); - return \"\"; -}" - [(set_attr "cc" "clobber")]) - -(define_insn "" - [(set (cc0) (and:HI (match_operand:HI 0 "general_operand" "d") - (match_operand:HI 1 "const_int_operand" "i")))] - "" - "btst %1,%0" - [(set_attr "cc" "clobber")]) - - -;; ---------------------------------------------------------------------- -;; JUMP INSTRUCTIONS -;; ---------------------------------------------------------------------- - -;; Conditional jump instructions - -(define_expand "ble" - [(set (pc) - (if_then_else (le (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bleu" - [(set (pc) - (if_then_else (leu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bge" - [(set (pc) - (if_then_else (ge (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bgeu" - [(set (pc) - (if_then_else (geu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "blt" - [(set (pc) - (if_then_else (lt (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bltu" - [(set (pc) - (if_then_else (ltu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bgt" - [(set (pc) - (if_then_else (gt (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bgtu" - [(set (pc) - (if_then_else (gtu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "beq" - [(set (pc) - (if_then_else (eq (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bne" - [(set (pc) - (if_then_else (ne (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_insn "" - [(set (pc) - (if_then_else (match_operator 1 "comparison_operator" - [(cc0) (const_int 0)]) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* -{ - if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 - && (GET_CODE (operands[1]) == GT - || GET_CODE (operands[1]) == GE - || GET_CODE (operands[1]) == LE - || GET_CODE (operands[1]) == LT)) - return 0; - - if (GET_MODE (SET_SRC (PATTERN (PREV_INSN (insn)))) == PSImode) - return \"b%b1x %0\"; - else - return \"b%b1 %0\"; -}" - [(set_attr "cc" "none")]) - -(define_insn "" - [(set (pc) - (if_then_else (match_operator 1 "comparison_operator" - [(cc0) (const_int 0)]) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* -{ - if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 - && (GET_CODE (operands[1]) == GT - || GET_CODE (operands[1]) == GE - || GET_CODE (operands[1]) == LE - || GET_CODE (operands[1]) == LT)) - return 0; - - if (GET_MODE (SET_SRC (PATTERN (PREV_INSN (insn)))) == PSImode) - return \"b%B1x %0\"; - else - return \"b%B1 %0\"; -}" - [(set_attr "cc" "none")]) - -(define_insn "jump" - [(set (pc) - (label_ref (match_operand 0 "" "")))] - "" - "jmp %l0" - [(set_attr "cc" "none")]) - -(define_insn "indirect_jump" - [(set (pc) (match_operand:PSI 0 "register_operand" "a"))] - "" - "jmp (%0)" - [(set_attr "cc" "none")]) - -(define_insn "tablejump" - [(set (pc) (match_operand:PSI 0 "register_operand" "a")) - (use (label_ref (match_operand 1 "" "")))] - "" - "jmp (%0)" - [(set_attr "cc" "none")]) - -;; Call subroutine with no return value. - -(define_expand "call" - [(call (match_operand:QI 0 "general_operand" "") - (match_operand:HI 1 "general_operand" ""))] - "" - " -{ - if (! call_address_operand (XEXP (operands[0], 0), VOIDmode)) - XEXP (operands[0], 0) = force_reg (PSImode, XEXP (operands[0], 0)); - emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1])); - DONE; -}") - -(define_insn "call_internal" - [(call (mem:QI (match_operand:PSI 0 "call_address_operand" "aS")) - (match_operand:HI 1 "general_operand" "g"))] - "" - "jsr %C0" - [(set_attr "cc" "clobber")]) - -;; Call subroutine, returning value in operand 0 -;; (which must be a hard register). - -(define_expand "call_value" - [(set (match_operand 0 "" "") - (call (match_operand:QI 1 "general_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "" - " -{ - if (! call_address_operand (XEXP (operands[1], 0), VOIDmode)) - XEXP (operands[1], 0) = force_reg (PSImode, XEXP (operands[1], 0)); - emit_call_insn (gen_call_value_internal (operands[0], - XEXP (operands[1], 0), - operands[2])); - DONE; -}") - -(define_insn "call_value_internal" - [(set (match_operand 0 "" "=da") - (call (mem:QI (match_operand:PSI 1 "call_address_operand" "aS")) - (match_operand:HI 2 "general_operand" "g")))] - "" - "jsr %C1" - [(set_attr "cc" "clobber")]) - -(define_expand "untyped_call" - [(parallel [(call (match_operand 0 "" "") - (const_int 0)) - (match_operand 1 "" "") - (match_operand 2 "" "")])] - "" - " -{ - int i; - - emit_call_insn (gen_call (operands[0], const0_rtx)); - - for (i = 0; i < XVECLEN (operands[2], 0); i++) - { - rtx set = XVECEXP (operands[2], 0, i); - emit_move_insn (SET_DEST (set), SET_SRC (set)); - } - DONE; -}") - -(define_insn "nop" - [(const_int 0)] - "" - "nop" - [(set_attr "cc" "none")]) - -;; ---------------------------------------------------------------------- -;; EXTEND INSTRUCTIONS -;; ---------------------------------------------------------------------- - -(define_insn "zero_extendqihi2" - [(set (match_operand:HI 0 "general_operand" "=d,d,d") - (zero_extend:HI - (match_operand:QI 1 "general_operand" "0,di,m")))] - "" - "@ - extxbu %0 - mov %1,%0\;extxbu %0 - movbu %1,%0" - [(set_attr "cc" "none_0hit")]) - -(define_insn "zero_extendqipsi2" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (zero_extend:PSI - (match_operand:QI 1 "general_operand" "0,di,m")))] - "" - "@ - extxbu %0 - mov %1,%0\;extxbu %0 - movbu %1,%0" - [(set_attr "cc" "none_0hit")]) - -(define_insn "zero_extendqisi2" - [(set (match_operand:SI 0 "general_operand" "=d,d,d") - (zero_extend:SI - (match_operand:QI 1 "general_operand" "0,di,m")))] - "" - "@ - extxbu %L0\;sub %H0,%H0 - mov %1,%L0\;extxbu %L0\;sub %H0,%H0 - movbu %1,%L0\;sub %H0,%H0" - [(set_attr "cc" "clobber")]) - -(define_insn "zero_extendhipsi2" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (zero_extend:PSI - (match_operand:HI 1 "general_operand" "0,di,m")))] - "" - "@ - extxu %0 - mov %1,%0\;extxu %0 - mov %1,%0\;extxu %0" - [(set_attr "cc" "none_0hit")]) - -(define_insn "zero_extendhisi2" - [(set (match_operand:SI 0 "general_operand" "=d,d") - (zero_extend:SI - (match_operand:HI 1 "general_operand" "0,dim")))] - "" - "@ - sub %H0,%H0 - mov %1,%L0\;sub %H0,%H0" - [(set_attr "cc" "clobber,clobber")]) - -;; The last alternative is necessary because the second operand might -;; have been the frame pointer. The frame pointer would get replaced -;; by (plus (stack_pointer) (const_int)). -;; -;; Reload would think that it only needed a PSImode register in -;; push_reload and at the start of allocate_reload_regs. However, -;; at the end of allocate_reload_reg it would realize that the -;; reload register must also be valid for SImode, and if it was -;; not valid reload would abort. -(define_insn "zero_extendpsisi2" - [(set (match_operand:SI 0 "register_operand" "=d,?d,?*d,?*d") - (zero_extend:SI (match_operand:PSI 1 "extendpsi_operand" - "m,?0,?*dai,Q")))] - "" - "@ - mov %L1,%L0\;movbu %H1,%H0 - jsr ___zero_extendpsisi2_%0 - mov %1,%L0\;jsr ___zero_extendpsisi2_%0 - mov a3,%L0\;add %Z1,%L0\;jsr ___zero_extendpsisi2_%0" - [(set_attr "cc" "clobber")]) - -;;- sign extension instructions - -(define_insn "extendqihi2" - [(set (match_operand:HI 0 "general_operand" "=d,d,d") - (sign_extend:HI - (match_operand:QI 1 "general_operand" "0,di,m")))] - "" - "* -{ - if (which_alternative == 0) - return \"extxb %0\"; - else if (which_alternative == 1) - return \"mov %1,%0\;extxb %0\"; - else if (GET_CODE (XEXP (operands[1], 0)) == REG) - return \"movbu %1,%0\;extxb %0\"; - else - return \"movb %1,%0\"; -}" - [(set_attr "cc" "none_0hit")]) - -(define_insn "extendqipsi2" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (sign_extend:PSI - (match_operand:QI 1 "general_operand" "0,di,m")))] - "" - "* -{ - if (which_alternative == 0) - return \"extxb %0\"; - else if (which_alternative == 1) - return \"mov %1,%0\;extxb %0\"; - else if (GET_CODE (XEXP (operands[1], 0)) == REG) - return \"movbu %1,%0\;extxb %0\"; - else - return \"movb %1,%0\"; -}" - [(set_attr "cc" "none_0hit")]) - -(define_insn "extendqisi2" - [(set (match_operand:SI 0 "general_operand" "=d,d,d") - (sign_extend:SI - (match_operand:QI 1 "general_operand" "0,di,m")))] - "" - "* -{ - if (which_alternative == 0) - return \"extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\"; - else if (which_alternative == 1) - return \"mov %1,%L0\;extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\"; - else if (GET_CODE (XEXP (operands[1], 0)) == REG) - return \"movbu %1,%L0\;extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\"; - else - return \"movb %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\"; -}" - [(set_attr "cc" "clobber")]) - -(define_insn "extendhipsi2" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (sign_extend:PSI - (match_operand:HI 1 "general_operand" "0,di,m")))] - "" - "@ - extx %0 - mov %1,%0\;extx %0 - mov %1,%0" - [(set_attr "cc" "none_0hit")]) - -(define_insn "extendhisi2" - [(set (match_operand:SI 0 "general_operand" "=d,d,d") - (sign_extend:SI - (match_operand:HI 1 "general_operand" "0,di,m")))] - "" - "@ - mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0 - mov %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0 - mov %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0" - [(set_attr "cc" "clobber")]) - -;; The last alternative is necessary because the second operand might -;; have been the frame pointer. The frame pointer would get replaced -;; by (plus (stack_pointer) (const_int)). -;; -;; Reload would think that it only needed a PSImode register in -;; push_reload and at the start of allocate_reload_regs. However, -;; at the end of allocate_reload_reg it would realize that the -;; reload register must also be valid for SImode, and if it was -;; not valid reload would abort. -(define_insn "extendpsisi2" - [(set (match_operand:SI 0 "general_operand" "=d,?d,?*d,?*d") - (sign_extend:SI (match_operand:PSI 1 "extendpsi_operand" - "m,?0,?*dai,Q")))] - "" - "@ - mov %L1,%L0\;movb %H1,%H0 - jsr ___sign_extendpsisi2_%0 - mov %1,%L0\;jsr ___sign_extendpsisi2_%0 - mov a3,%L0\;add %Z1,%L0\;jsr ___sign_extendpsisi2_%0" - [(set_attr "cc" "clobber")]) - -(define_insn "truncsipsi2" - [(set (match_operand:PSI 0 "general_operand" "=a,?d,?*d,da") - (truncate:PSI (match_operand:SI 1 "psimode_truncation_operand" "m,?m,?*d,i")))] - "" - "@ - mov %1,%0 - movx %A1,%0 - jsr ___truncsipsi2_%1_%0 - mov %1,%0" - [(set_attr "cc" "clobber")]) - - -;; Combine should be simplifying this stuff, but isn't. -;; -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=d,d,d") - (sign_extend:SI - (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m"))))] - "" - "@ - extxbu %L0\;sub %H0,%H0 - mov %1,%L0\;extxbu %L0\;sub %H0,%H0 - movbu %1,%L0\;sub %H0,%H0" - [(set_attr "cc" "clobber")]) - -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (truncate:PSI - (sign_extend:SI (match_operand:QI 1 "general_operand" "0,di,m"))))] - "" - "* -{ - if (which_alternative == 0) - return \"extxb %0\"; - else if (which_alternative == 1) - return \"mov %1,%0\;extxb %0\"; - else if (GET_CODE (XEXP (operands[1], 0)) == REG) - return \"movbu %1,%0\;extxb %0\"; - else - return \"movb %1,%0\"; -}" - [(set_attr "cc" "none_0hit")]) - -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (truncate:PSI - (sign_extend:SI (match_operand:HI 1 "general_operand" "0,di,m"))))] - "" - "@ - extx %0 - mov %1,%0\;extx %0 - mov %1,%0" - [(set_attr "cc" "none_0hit")]) - -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (truncate:PSI - (sign_extend:SI - (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m")))))] - "" - "@ - extxbu %0 - mov %1,%0\;extxbu %0 - movbu %1,%0" - [(set_attr "cc" "none_0hit")]) - -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (truncate:PSI - (zero_extend:SI (match_operand:HI 1 "general_operand" "0,di,m"))))] - "" - "@ - extxu %0 - mov %1,%0\;extxu %0 - mov %1,%0\;extxu %0" - [(set_attr "cc" "none_0hit")]) - -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (truncate:PSI - (zero_extend:SI (match_operand:QI 1 "general_operand" "0,di,m"))))] - "" - "@ - extxbu %0 - mov %1,%0\;extxbu %0 - movbu %1,%0" - [(set_attr "cc" "none_0hit")]) - -;; ---------------------------------------------------------------------- -;; SHIFTS -;; ---------------------------------------------------------------------- - -;; If the shift count is small, we expand it into several single bit -;; shift insns. Otherwise we expand into a generic shift insn which -;; handles larger shift counts, shift by variable amounts, etc. -(define_expand "ashlhi3" - [(set (match_operand:HI 0 "general_operand" "") - (ashift:HI (match_operand:HI 1 "general_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "" - " -{ - /* This is an experiment to see if exposing more of the underlying - operations results in better code. */ - if (GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) <= 4) - { - int count = INTVAL (operands[2]); - emit_move_insn (operands[0], operands[1]); - while (count > 0) - { - emit_insn (gen_rtx_SET (HImode, operands[0], - gen_rtx_ASHIFT (HImode, - operands[0], GEN_INT (1)))); - count--; - } - DONE; - } - else - { - expand_a_shift (HImode, ASHIFT, operands); - DONE; - } -}") - -;; ASHIFT one bit. -(define_insn "" - [(set (match_operand:HI 0 "general_operand" "=d") - (ashift:HI (match_operand:HI 1 "general_operand" "0") - (const_int 1)))] - "" - "add %0,%0" - [(set_attr "cc" "set_zn")]) - -(define_expand "lshrhi3" - [(set (match_operand:HI 0 "general_operand" "") - (lshiftrt:HI (match_operand:HI 1 "general_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "" - " -{ - /* This is an experiment to see if exposing more of the underlying - operations results in better code. */ - if (GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) <= 4) - { - int count = INTVAL (operands[2]); - emit_move_insn (operands[0], operands[1]); - while (count > 0) - { - emit_insn (gen_rtx_SET (HImode, operands[0], - gen_rtx_LSHIFTRT (HImode, - operands[0], - GEN_INT (1)))); - count--; - } - DONE; - } - else - { - expand_a_shift (HImode, LSHIFTRT, operands); - DONE; - } -}") - -;; LSHIFTRT one bit. -(define_insn "" - [(set (match_operand:HI 0 "general_operand" "=d") - (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") - (const_int 1)))] - "" - "lsr %0" - [(set_attr "cc" "set_znv")]) - -(define_expand "ashrhi3" - [(set (match_operand:HI 0 "general_operand" "") - (ashiftrt:HI (match_operand:HI 1 "general_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "" - " -{ - /* This is an experiment to see if exposing more of the underlying - operations results in better code. */ - if (GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) <= 4) - { - int count = INTVAL (operands[2]); - emit_move_insn (operands[0], operands[1]); - while (count > 0) - { - emit_insn (gen_rtx_SET (HImode, operands[0], - gen_rtx_ASHIFTRT (HImode, operands[0], - GEN_INT (1)))); - count--; - } - DONE; - } - else - { - expand_a_shift (HImode, ASHIFTRT, operands); - DONE; - } -}") - -;; ASHIFTRT one bit. -(define_insn "" - [(set (match_operand:HI 0 "general_operand" "=d") - (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") - (const_int 1)))] - "" - "asr %0" - [(set_attr "cc" "set_znv")]) - -;; And the general HImode shift pattern. Handles both shift by constants -;; and shift by variable counts. -(define_insn "" - [(set (match_operand:HI 0 "general_operand" "=d,d") - (match_operator:HI 3 "nshift_operator" - [ (match_operand:HI 1 "general_operand" "0,0") - (match_operand:HI 2 "general_operand" "KL,dan")])) - (clobber (match_scratch:HI 4 "=X,&d"))] - "" - "* return emit_a_shift (insn, operands);" - [(set_attr "cc" "clobber")]) - -;; We expect only ASHIFT with constant shift counts to be common for -;; PSImode, so we optimize just that case. For all other cases we -;; extend the value to SImode and perform the shift in SImode. -(define_expand "ashlpsi3" - [(set (match_operand:PSI 0 "general_operand" "") - (ashift:PSI (match_operand:PSI 1 "general_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "" - " -{ - /* This is an experiment to see if exposing more of the underlying - operations results in better code. */ - if (GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) <= 7) - { - int count = INTVAL (operands[2]); - emit_move_insn (operands[0], operands[1]); - while (count > 0) - { - emit_insn (gen_rtx_SET (PSImode, operands[0], - gen_rtx_ASHIFT (PSImode, - operands[0], GEN_INT (1)))); - count--; - } - DONE; - } - else - { - expand_a_shift (PSImode, ASHIFT, operands); - DONE; - } -}") - -;; ASHIFT one bit. -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d") - (ashift:PSI (match_operand:PSI 1 "general_operand" "0") - (const_int 1)))] - "" - "add %0,%0" - [(set_attr "cc" "set_zn")]) - -(define_expand "lshrpsi3" - [(set (match_operand:PSI 0 "general_operand" "") - (lshiftrt:PSI (match_operand:PSI 1 "general_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "" - " -{ - rtx reg = gen_reg_rtx (SImode); - - emit_insn (gen_zero_extendpsisi2 (reg, operands[1])); - reg = expand_binop (SImode, lshr_optab, reg, - operands[2], reg, 1, OPTAB_WIDEN); - emit_insn (gen_truncsipsi2 (operands[0], reg)); - DONE; -}") - -(define_expand "ashrpsi3" - [(set (match_operand:PSI 0 "general_operand" "") - (ashiftrt:PSI (match_operand:PSI 1 "general_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "" - " -{ - rtx reg = gen_reg_rtx (SImode); - - emit_insn (gen_extendpsisi2 (reg, operands[1])); - reg = expand_binop (SImode, ashr_optab, reg, - operands[2], reg, 0, OPTAB_WIDEN); - emit_insn (gen_truncsipsi2 (operands[0], reg)); - DONE; -}") - -(define_expand "ashlsi3" - [(set (match_operand:SI 0 "register_operand" "") - (ashift:SI (match_operand:SI 1 "nonmemory_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "" - " -{ - /* For small shifts, just emit a series of single bit shifts inline. - - For other constant shift counts smaller than a word or non-constant - shift counts we call out to a library call during RTL generation time; - after RTL generation time we allow optabs.c to open code the operation. - See comments in addsi3/subsi3 expanders. - - Otherwise we allow optabs.c to open code the operation. */ - if (GET_CODE (operands[2]) == CONST_INT - && (INTVAL (operands[2]) <= 3)) - { - int count = INTVAL (operands[2]); - emit_move_insn (operands[0], operands[1]); - while (count > 0) - { - emit_insn (gen_rtx_SET (SImode, operands[0], - gen_rtx_ASHIFT (SImode, - operands[0], GEN_INT (1)))); - count--; - } - DONE; - } - else if (rtx_equal_function_value_matters - && (GET_CODE (operands[2]) != CONST_INT - || INTVAL (operands[2]) <= 15)) - { - rtx ret, insns; - - start_sequence (); - ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__ashlsi3\"), - NULL_RTX, 1, SImode, 2, operands[1], - SImode, operands[2], HImode); - insns = get_insns (); - end_sequence (); - emit_libcall_block (insns, operands[0], ret, - gen_rtx_ASHIFT (SImode, operands[1], operands[2])); - DONE; - } - else - FAIL; -}") - -;; ASHIFT one bit. -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=d") - (ashift:SI (match_operand:SI 1 "general_operand" "0") - (const_int 1)))] - "" - "add %L0,%L0\;addc %H0,%H0" - [(set_attr "cc" "clobber")]) - -(define_expand "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "") - (lshiftrt:SI (match_operand:SI 1 "general_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "" - " -{ - /* For small shifts, just emit a series of single bit shifts inline. - - For other constant shift counts smaller than a word or non-constant - shift counts we call out to a library call during RTL generation time; - after RTL generation time we allow optabs.c to open code the operation. - See comments in addsi3/subsi3 expanders. - - Otherwise we allow optabs.c to open code the operation. */ - if (GET_CODE (operands[2]) == CONST_INT - && (INTVAL (operands[2]) <= 2)) - { - int count = INTVAL (operands[2]); - emit_move_insn (operands[0], operands[1]); - while (count > 0) - { - emit_insn (gen_rtx_SET (SImode, operands[0], - gen_rtx_LSHIFTRT (SImode, operands[0], - GEN_INT (1)))); - count--; - } - DONE; - } - else if (rtx_equal_function_value_matters - && (GET_CODE (operands[2]) != CONST_INT - || INTVAL (operands[2]) <= 15)) - { - rtx ret, insns; - - start_sequence (); - ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__lshrsi3\"), - NULL_RTX, 1, SImode, 2, operands[1], - SImode, operands[2], HImode); - insns = get_insns (); - end_sequence (); - emit_libcall_block (insns, operands[0], ret, - gen_rtx_LSHIFTRT (SImode, operands[1], operands[2])); - DONE; - } - else - FAIL; -}") - -;; LSHIFTRT one bit. -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=d") - (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") - (const_int 1)))] - "" - "lsr %H0\;ror %L0" - [(set_attr "cc" "clobber")]) - -(define_expand "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "" - " -{ - /* For small shifts, just emit a series of single bit shifts inline. - - For other constant shift counts smaller than a word or non-constant - shift counts we call out to a library call during RTL generation time; - after RTL generation time we allow optabs.c to open code the operation. - See comments in addsi3/subsi3 expanders. - - Otherwise we allow optabs.c to open code the operation. */ - if (GET_CODE (operands[2]) == CONST_INT - && (INTVAL (operands[2]) <= 2)) - { - int count = INTVAL (operands[2]); - emit_move_insn (operands[0], operands[1]); - while (count > 0) - { - emit_insn (gen_rtx_SET (SImode, operands[0], - gen_rtx_ASHIFTRT (SImode, operands[0], - GEN_INT (1)))); - count--; - } - DONE; - } - else if (rtx_equal_function_value_matters - && (GET_CODE (operands[2]) != CONST_INT - || INTVAL (operands[2]) <= 15)) - { - rtx ret, insns; - - start_sequence (); - ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__ashrsi3\"), - NULL_RTX, 1, SImode, 2, operands[1], - SImode, operands[2], HImode); - insns = get_insns (); - end_sequence (); - emit_libcall_block (insns, operands[0], ret, - gen_rtx_ASHIFTRT (SImode, operands[1], operands[2])); - DONE; - } - else - FAIL; -}") - -;; ASHIFTRT one bit. -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=d") - (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") - (const_int 1)))] - "" - "asr %H0\;ror %L0" - [(set_attr "cc" "clobber")]) - -;; ---------------------------------------------------------------------- -;; FP INSTRUCTIONS -;; ---------------------------------------------------------------------- -;; -;; The mn102 series does not have floating point instructions, but since -;; FP values are held in integer regs, we can clear the high bit easily -;; which gives us an efficient inline floating point absolute value. -;; -;; Similarly for negation of a FP value. -;; - -(define_expand "abssf2" - [(set (match_operand:SF 0 "register_operand" "") - (abs:SF (match_operand:SF 1 "register_operand" "")))] - "" - " -{ - rtx target, result, insns; - - start_sequence (); - target = operand_subword (operands[0], 1, 1, SFmode); - result = expand_binop (HImode, and_optab, - operand_subword_force (operands[1], 1, SFmode), - GEN_INT(0x7fff), target, 0, OPTAB_WIDEN); - - if (result == 0) - abort (); - - if (result != target) - emit_move_insn (result, target); - - emit_move_insn (operand_subword (operands[0], 0, 1, SFmode), - operand_subword_force (operands[1], 0, SFmode)); - - insns = get_insns (); - end_sequence (); - - emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); - DONE; -}") - -(define_expand "negsf2" - [(set (match_operand:SF 0 "register_operand" "") - (neg:SF (match_operand:SF 1 "register_operand" "")))] - "" - " -{ - rtx target, result, insns; - - start_sequence (); - target = operand_subword (operands[0], 1, 1, SFmode); - result = expand_binop (HImode, xor_optab, - operand_subword_force (operands[1], 1, SFmode), - GEN_INT(-0x8000), target, 0, OPTAB_WIDEN); - - if (result == 0) - abort (); - - if (result != target) - emit_move_insn (result, target); - - emit_move_insn (operand_subword (operands[0], 0, 1, SFmode), - operand_subword_force (operands[1], 0, SFmode)); - - insns = get_insns (); - end_sequence (); - - emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); - DONE; -}") - -;; ---------------------------------------------------------------------- -;; PROLOGUE/EPILOGUE -;; ---------------------------------------------------------------------- -(define_expand "prologue" - [(const_int 0)] - "" - "expand_prologue (); DONE;") - -(define_insn "outline_prologue_call" - [(const_int 1)] - "" - "jsr ___prologue" - [(set_attr "cc" "clobber")]) - -(define_expand "epilogue" - [(return)] - "" - " -{ - expand_epilogue (); - DONE; -}") - -(define_insn "outline_epilogue_call_a0" - [(const_int 2)] - "" - "jsr ___epilogue_a0" - [(set_attr "cc" "clobber")]) - -(define_insn "outline_epilogue_call_d0" - [(const_int 3)] - "" - "jsr ___epilogue_d0" - [(set_attr "cc" "clobber")]) - -(define_insn "outline_epilogue_jump" - [(const_int 4) - (return)] - "" - "jmp ___epilogue_noreturn" - [(set_attr "cc" "clobber")]) - -(define_insn "return" - [(return)] - "reload_completed && total_frame_size () == 0 - && !current_function_needs_context" - "* -{ - rtx next = next_active_insn (insn); - - if (next - && GET_CODE (next) == JUMP_INSN - && GET_CODE (PATTERN (next)) == RETURN) - return \"\"; - return \"rts\"; -}" - [(set_attr "cc" "clobber")]) - -(define_insn "return_internal" - [(const_int 0) - (return)] - "" - "rts" - [(set_attr "cc" "clobber")]) - -;; These are special combiner patterns to improve array/pointer accesses. -;; -;; A typical sequence involves extending an integer/char, shifting it left -;; a few times, then truncating the value to PSImode. -;; -;; This first pattern combines the shifting & truncation operations, by -;; itself it is a win because the shifts end up occurring in PSImode instead -;; of SImode. However, it has the secondary effect of giving us the -;; opportunity to match patterns which allow us to remove the initial -;; extension completely, which is a big win. -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,d,a,da") - (truncate:PSI - (ashift:SI (match_operand:SI 1 "psimode_truncation_operand" "d,m,m,i") - (match_operand:HI 2 "const_int_operand" "i,i,i,i"))))] - "" - "* -{ - int count = INTVAL (operands[2]); - if (which_alternative == 0) - output_asm_insn (\"jsr ___truncsipsi2_%1_%0\", operands); - else if (which_alternative == 1) - output_asm_insn (\"movx %A1,%0\", operands); - else - output_asm_insn (\" mov %1,%0\", operands); - - while (count) - { - output_asm_insn (\"add %0,%0\", operands); - count--; - } - return \"\"; -}" - [(set_attr "cc" "clobber")]) - -;; Similarly, except that we also have zero/sign extension of the -;; original operand. */ -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,d") - (truncate:PSI - (ashift:SI - (zero_extend:SI (match_operand:HI 1 "general_operand" "0,dim")) - (match_operand:HI 2 "const_int_operand" "i,i"))))] - "" - "* -{ - int count = INTVAL (operands[2]); - - /* First extend operand 1 to PSImode. */ - if (which_alternative == 0) - output_asm_insn (\"extxu %0\", operands); - else - output_asm_insn (\"mov %1,%0\;extxu %0\", operands); - - /* Now do the shifting. */ - while (count) - { - output_asm_insn (\"add %0,%0\", operands); - count--; - } - return \"\"; -}" - [(set_attr "cc" "clobber")]) - -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (truncate:PSI - (ashift:SI - (sign_extend:SI (match_operand:HI 1 "general_operand" "0,di,m")) - (match_operand:HI 2 "const_int_operand" "i,i,i"))))] - "" - "* -{ - int count = INTVAL (operands[2]); - - /* First extend operand 1 to PSImode. */ - if (which_alternative == 0) - output_asm_insn (\"extx %0\", operands); - else if (which_alternative == 1) - output_asm_insn (\"mov %1,%0\;extx %0\", operands); - else - output_asm_insn (\"mov %1,%0\", operands); - - /* Now do the shifting. */ - while (count) - { - output_asm_insn (\"add %0,%0\", operands); - count--; - } - return \"\"; -}" - [(set_attr "cc" "clobber")]) - -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (truncate:PSI - (ashift:SI - (sign_extend:SI - (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m"))) - (match_operand:HI 2 "const_int_operand" "i,i,i"))))] - "" - "* -{ - int count = INTVAL (operands[2]); - - /* First extend operand 1 to PSImode. */ - if (which_alternative == 0) - output_asm_insn (\"extxbu %0\", operands); - else if (which_alternative == 1) - output_asm_insn (\"mov %1,%0\;extxbu %0\", operands); - else - output_asm_insn (\"movbu %1,%0\", operands); - - /* Now do the shifting. */ - while (count) - { - output_asm_insn (\"add %0,%0\", operands); - count--; - } - return \"\"; -}" - [(set_attr "cc" "clobber")]) - -(define_insn "" - [(set (match_operand:PSI 0 "general_operand" "=d,d,d") - (truncate:PSI - (ashift:SI - (sign_extend:SI - (match_operand:QI 1 "general_operand" "0,di,m")) - (match_operand:HI 2 "const_int_operand" "i,i,i"))))] - "" - "* -{ - int count = INTVAL (operands[2]); - - /* First extend operand 1 to PSImode. */ - if (which_alternative == 0) - output_asm_insn (\"extxb %0\", operands); - else if (which_alternative == 1) - output_asm_insn (\"mov %1,%0\;extxb %0\", operands); - else if (GET_CODE (XEXP (operands[1], 0)) == REG) - output_asm_insn (\"movbu %1,%0\;extxb %0\", operands); - else - output_asm_insn (\"movb %1,%0\", operands); - - /* Now do the shifting. */ - while (count) - { - output_asm_insn (\"add %0,%0\", operands); - count--; - } - return \"\"; -}" - [(set_attr "cc" "clobber")]) - -;; Try to combine consecutive updates of the stack pointer (or any -;; other register for that matter). -(define_peephole - [(set (match_operand:PSI 0 "register_operand" "=da") - (plus:PSI (match_dup 0) - (match_operand 1 "const_int_operand" ""))) - (set (match_dup 0) - (plus:PSI (match_dup 0) - (match_operand 2 "const_int_operand" "")))] - "" - "* -{ - operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1])); - return \"add %1,%0\"; -}" - [(set_attr "cc" "clobber")]) - -;; -;; We had patterns to check eq/ne, but the they don't work because -;; 0x80000000 + 0x80000000 = 0x0 with a carry out. -;; -;; The Z flag and C flag would be set, and we have no way to -;; check for the Z flag set and C flag clear. -;; -;; This will work on the mn10200 because we can check the ZX flag -;; if the comparison is in HImode. -(define_peephole - [(set (cc0) (match_operand:HI 0 "register_operand" "d")) - (set (pc) (if_then_else (ge (cc0) (const_int 0)) - (match_operand 1 "" "") - (pc)))] - "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])" - "add %0,%0\;bcc %1" - [(set_attr "cc" "clobber")]) - -(define_peephole - [(set (cc0) (match_operand:HI 0 "register_operand" "d")) - (set (pc) (if_then_else (lt (cc0) (const_int 0)) - (match_operand 1 "" "") - (pc)))] - "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])" - "add %0,%0\;bcs %1" - [(set_attr "cc" "clobber")]) - -(define_peephole - [(set (cc0) (match_operand:HI 0 "register_operand" "d")) - (set (pc) (if_then_else (ge (cc0) (const_int 0)) - (pc) - (match_operand 1 "" "")))] - "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])" - "add %0,%0\;bcs %1" - [(set_attr "cc" "clobber")]) - -(define_peephole - [(set (cc0) (match_operand:HI 0 "register_operand" "d")) - (set (pc) (if_then_else (lt (cc0) (const_int 0)) - (pc) - (match_operand 1 "" "")))] - "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])" - "add %0,%0\;bcc %1" - [(set_attr "cc" "clobber")]) - -(define_peephole - [(set (cc0) (match_operand:PSI 0 "register_operand" "d")) - (set (pc) (if_then_else (ge (cc0) (const_int 0)) - (match_operand 1 "" "") - (pc)))] - "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])" - "add %0,%0\;bccx %1" - [(set_attr "cc" "clobber")]) - -(define_peephole - [(set (cc0) (match_operand:PSI 0 "register_operand" "d")) - (set (pc) (if_then_else (lt (cc0) (const_int 0)) - (match_operand 1 "" "") - (pc)))] - "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])" - "add %0,%0\;bcsx %1" - [(set_attr "cc" "clobber")]) - -(define_peephole - [(set (cc0) (match_operand:PSI 0 "register_operand" "d")) - (set (pc) (if_then_else (ge (cc0) (const_int 0)) - (pc) - (match_operand 1 "" "")))] - "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])" - "add %0,%0\;bcsx %1" - [(set_attr "cc" "clobber")]) - -(define_peephole - [(set (cc0) (match_operand:PSI 0 "register_operand" "d")) - (set (pc) (if_then_else (lt (cc0) (const_int 0)) - (pc) - (match_operand 1 "" "")))] - "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])" - "add %0,%0\;bccx %1" - [(set_attr "cc" "clobber")]) - -;; We call out to library routines to perform 32bit addition and subtraction -;; operations (see addsi3/subsi3 expanders for why). These peepholes catch -;; the trivial case where the operation could be done with an add;addc or -;; sub;subc sequence. -(define_peephole - [(set (mem:SI (reg:PSI 7)) (reg:SI 2)) - (set (reg:SI 0) (call (match_operand:QI 1 "general_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF - && strcmp (XSTR (XEXP (operands[1], 0), 0), \"__addsi3\") == 0" - "add d2,d0\;addc d3,d1" - [(set_attr "cc" "clobber")]) - -(define_peephole - [(set (mem:SI (reg:PSI 7)) (reg:SI 2)) - (set (reg:SI 0) (call (match_operand:QI 1 "general_operand" "") - (match_operand:HI 2 "general_operand" "")))] - "GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF - && strcmp (XSTR (XEXP (operands[1], 0), 0), \"__subsi3\") == 0" - "sub d2,d0\;subc d3,d1" - [(set_attr "cc" "clobber")]) diff --git a/gcc/config/mn10200/t-mn10200 b/gcc/config/mn10200/t-mn10200 deleted file mode 100644 index 7bdc5abdd07..00000000000 --- a/gcc/config/mn10200/t-mn10200 +++ /dev/null @@ -1,52 +0,0 @@ -LIB1ASMSRC = mn10200/lib1funcs.asm -LIB1ASMFUNCS = _divhi3 \ - _modhi3 \ - _addsi3 \ - _subsi3 \ - _mulsi3 \ - _ashlsi3 \ - _lshrsi3 \ - _ashrsi3 \ - _negsi2_d0 \ - _negsi2_d2 \ - _zero_extendpsisi2_d0 \ - _zero_extendpsisi2_d2 \ - _sign_extendpsisi2_d0 \ - _sign_extendpsisi2_d2 \ - _truncsipsi2_d0_d0 \ - _truncsipsi2_d0_d1 \ - _truncsipsi2_d0_d2 \ - _truncsipsi2_d0_d3 \ - _truncsipsi2_d2_d0 \ - _truncsipsi2_d2_d1 \ - _truncsipsi2_d2_d2 \ - _truncsipsi2_d2_d3 \ - _cmpsi2 \ - _ucmpsi2 \ - _prologue \ - _epilogue_a0 \ - _epilogue_d0 \ - _epilogue_noreturn \ - _floatdisf \ - _fixsfdi - - -# We do not have DF or DI types, so fake out the libgcc2 compilation. -TARGET_LIBGCC2_CFLAGS=-DDF=SF -DDI=SI -LIB2FUNCS_EXTRA = $(srcdir)/config/udivmodsi4.c \ - $(srcdir)/config/divmod.c $(srcdir)/config/udivmod.c - -# We want fine grained libraries, so use the new code to build the -# floating point emulation libraries. The mn10200 only has single -# precision floating point. -FPBIT = fp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - echo '#define FLOAT_ONLY' >> fp-bit.c - echo '#define SMALL_MACHINE' >> fp-bit.c - echo '#define CMPtype HItype' >> fp-bit.c - echo '#ifdef __LITTLE_ENDIAN__' >> fp-bit.c - echo '#define FLOAT_BIT_ORDER_MISMATCH' >>fp-bit.c - echo '#endif' >> fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c diff --git a/gcc/config/pa/pa-hiux.h b/gcc/config/pa/pa-hiux.h deleted file mode 100644 index c1d945c6daa..00000000000 --- a/gcc/config/pa/pa-hiux.h +++ /dev/null @@ -1,76 +0,0 @@ -/* Definitions of target machine for GNU compiler, for HI-UX. - Copyright (C) 1993, 1995, 1996, 2002 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* HIUX is just a HPUX variant. We can simply use the HPUX configuration - for just about everything. */ - -/* OS cpp builtins are the one noteworthy difference between HPUX and HIUX. - The following defines are similar to those for hpux10 with the addition - of __H3050R and __H3050RX. */ -#undef TARGET_OS_CPP_BUILTINS -#define TARGET_OS_CPP_BUILTINS() \ - do \ - { \ - builtin_assert ("system=hiux"); \ - builtin_assert ("system=unix"); \ - builtin_define ("__hp9000s800"); \ - builtin_define ("__hp9000s800__"); \ - builtin_define ("__hiux"); \ - builtin_define ("__hiux__"); \ - builtin_define ("__unix"); \ - builtin_define ("__unix__"); \ - builtin_define ("__H3050R"); \ - builtin_define ("__H3050RX"); \ - if (c_language == clk_cplusplus) \ - { \ - builtin_define ("_HIUX_SOURCE"); \ - builtin_define ("_INCLUDE_LONGLONG"); \ - } \ - else if (!flag_iso) \ - { \ - builtin_define ("_HIUX_SOURCE"); \ - if (preprocessing_trad_p ()) \ - { \ - builtin_define ("hp9000s800"); \ - builtin_define ("hppa"); \ - builtin_define ("hiux"); \ - builtin_define ("unix"); \ - builtin_define ("__CLASSIC_C__"); \ - builtin_define ("_PWB"); \ - builtin_define ("PWB"); \ - } \ - else \ - builtin_define ("__STDC_EXT__"); \ - } \ - if (TARGET_SIO) \ - builtin_define ("_SIO"); \ - else \ - { \ - builtin_define ("__hp9000s700"); \ - builtin_define ("__hp9000s700__"); \ - builtin_define ("_WSIO"); \ - } \ - } \ - while (0) - -#undef SUBTARGET_SWITCHES -#define SUBTARGET_SWITCHES \ - { "sio", MASK_SIO, N_("Generate cpp defines for server IO") }, \ - { "wsio", -MASK_SIO, N_("Generate cpp defines for workstation IO") }, diff --git a/gcc/config/pa/pa-hpux7.h b/gcc/config/pa/pa-hpux7.h deleted file mode 100644 index 0239e038cf8..00000000000 --- a/gcc/config/pa/pa-hpux7.h +++ /dev/null @@ -1,86 +0,0 @@ -/* Definitions of target machine for GNU compiler, for HP-UX. - Copyright (C) 1991, 1995, 1996, 2002 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifndef TARGET_DEFAULT -#define TARGET_DEFAULT 0 -#endif - -/* Make GCC agree with types.h. */ -#undef SIZE_TYPE -#undef PTRDIFF_TYPE - -#define SIZE_TYPE "unsigned int" -#define PTRDIFF_TYPE "int" - -#undef TARGET_OS_CPP_BUILTINS -#define TARGET_OS_CPP_BUILTINS() \ - do \ - { \ - builtin_assert ("system=hpux"); \ - builtin_assert ("system=unix"); \ - builtin_define ("__hp9000s800"); \ - builtin_define ("__hp9000s800__"); \ - builtin_define ("__hp9k8"); \ - builtin_define ("__hp9k8__"); \ - builtin_define ("__hpux"); \ - builtin_define ("__hpux__"); \ - builtin_define ("__unix"); \ - builtin_define ("__unix__"); \ - if (c_language == clk_cplusplus) \ - { \ - builtin_define ("_HPUX_SOURCE"); \ - builtin_define ("_INCLUDE_LONGLONG"); \ - } \ - else if (!flag_iso) \ - { \ - builtin_define ("_HPUX_SOURCE"); \ - if (preprocessing_trad_p ()) \ - { \ - builtin_define ("hp9000s800"); \ - builtin_define ("hp9k8"); \ - builtin_define ("hppa"); \ - builtin_define ("hpux"); \ - builtin_define ("unix"); \ - builtin_define ("__CLASSIC_C__"); \ - builtin_define ("_PWB"); \ - builtin_define ("PWB"); \ - } \ - else \ - builtin_define ("__STDC_EXT__"); \ - } \ - if (TARGET_SIO) \ - builtin_define ("_SIO"); \ - else \ - { \ - builtin_define ("__hp9000s700"); \ - builtin_define ("__hp9000s700__"); \ - builtin_define ("_WSIO"); \ - } \ - } \ - while (0) - -#undef SUBTARGET_SWITCHES -#define SUBTARGET_SWITCHES \ - { "sio", MASK_SIO, N_("Generate cpp defines for server IO") }, \ - { "wsio", -MASK_SIO, N_("Generate cpp defines for workstation IO") }, - -/* Like the default, except no -lg. */ -#undef LIB_SPEC -#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p: -L/lib/libp/ -lc}%{pg: -L/lib/libp/ -lc}" diff --git a/gcc/config/pa/pa-hpux9.h b/gcc/config/pa/pa-hpux9.h deleted file mode 100644 index 89dbbc9ef46..00000000000 --- a/gcc/config/pa/pa-hpux9.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Definitions of target machine for GNU compiler, for HP PA-RISC 1.1 - Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc. - Contributed by Tim Moore (moore@defmacro.cs.utah.edu) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* We can debug dynamically linked executables on hpux9; we also want - dereferencing of a NULL pointer to cause a SEGV. */ -#undef LINK_SPEC -#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_PA_11) -#define LINK_SPEC \ - "%{!mpa-risc-1-0:%{!shared:-L/lib/pa1.1 -L/usr/lib/pa1.1 }} -z %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-b}" -#else -#define LINK_SPEC \ - "-z %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-b}" -#endif diff --git a/gcc/config/pa/pa-oldas.h b/gcc/config/pa/pa-oldas.h deleted file mode 100644 index 8ff741f1435..00000000000 --- a/gcc/config/pa/pa-oldas.h +++ /dev/null @@ -1,22 +0,0 @@ -/* Definitions of target machine for GNU compiler, for HP PA-RISC 1.1 - Copyright (C) 1991, 1996 Free Software Foundation, Inc. - Contributed by Tim Moore (moore@defmacro.cs.utah.edu) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#define HP_FP_ARG_DESCRIPTOR_REVERSED diff --git a/gcc/config/pa/t-mpeix b/gcc/config/pa/t-mpeix deleted file mode 100644 index 4e6cd7a2d8e..00000000000 --- a/gcc/config/pa/t-mpeix +++ /dev/null @@ -1,5 +0,0 @@ -LIB2FUNCS_EXTRA= quadlib.c - -quadlib.c: $(srcdir)/config/pa/quadlib.c - rm -f quadlib.c - cp $(srcdir)/config/pa/quadlib.c . diff --git a/gcc/config/psos.h b/gcc/config/psos.h deleted file mode 100644 index 72825d458df..00000000000 --- a/gcc/config/psos.h +++ /dev/null @@ -1,88 +0,0 @@ -/* Operating system specific defines to be used when targeting GCC for some - embedded system running pSOS. We assume GNU tools with ELF, but - try to maintain compatibility with the MRI tools. Based on svr4.h. - Copyright (C) 1996, 1999, 2000 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. - - To use this file, make up a file with a name like: - - ?????-psos.h - - where ????? is replaced by the name of the basic hardware that you - are targeting for. Then, in the file ?????-psos.h, put something - like: - - #include "?????.h" - #include "psos.h" - - followed by any really system-specific defines (or overrides of - defines) which you find that you need. -*/ - - -/* Define a symbol indicating that we are using psos.h. */ - -#define USING_PSOS_H - - -/* All pSOS targets currently use the ELF object file format. */ - -#define OBJECT_FORMAT_ELF - - -/* Provide a NULL STARTFILE_SPEC. The startfile cannot be specified - here because it depends on the architecture (e.g. 68K), the - board-support package (e.g. M162) and the run-time configuration - (e.g. application vs. ram-image vs. rom-image). Specify the - startfile in a linker-script created from the generic - architecture-specific linker-scripts. */ - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "" - - -/* Predefined macros (independent of processor type). */ - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dpsos" - - -/* Implicit library calls should use ANSI memcpy rather than BSD - bcopy, etc. */ - -#define TARGET_MEM_FUNCTIONS - -/* This is how we tell the assembler that a symbol is weak. */ - -#define ASM_WEAKEN_LABEL(FILE,NAME) \ - do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \ - fputc ('\n', FILE); } while (0) - -/* Switch into a generic section. */ -#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section - -/* Use DBX debugging info by default. */ - -#ifndef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG -#endif - -/* For pSOS we use DBX debugging info. */ - -#define DBX_DEBUGGING_INFO 1 diff --git a/gcc/config/romp/romp-protos.h b/gcc/config/romp/romp-protos.h deleted file mode 100644 index 8ec306f3802..00000000000 --- a/gcc/config/romp/romp-protos.h +++ /dev/null @@ -1,62 +0,0 @@ -/* Definitions of target machine for GNU compiler, for ROMP chip. - Copyright (C) 2000 Free Software Foundation, Inc. - Contributed by Richard Kenner (kenner@nyu.edu) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifdef RTX_CODE -extern int next_insn_tests_no_unsigned PARAMS ((rtx)); -extern void update_cc PARAMS ((rtx, rtx)); -extern int restore_compare_p PARAMS ((rtx)); -extern void print_operand PARAMS ((FILE *, rtx, int)); -extern rtx get_symref PARAMS ((const char *)); -extern int check_precision PARAMS ((enum machine_mode, rtx, rtx)); -extern const char *output_fpop PARAMS ((enum rtx_code, rtx, rtx, rtx, rtx)); -extern int constant_pool_address_operand PARAMS ((rtx, enum machine_mode)); -extern int romp_symbolic_operand PARAMS ((rtx, enum machine_mode)); -extern int zero_memory_operand PARAMS ((rtx, enum machine_mode)); -extern int short_memory_operand PARAMS ((rtx, enum machine_mode)); -extern int symbolic_memory_operand PARAMS ((rtx, enum machine_mode)); -extern int current_function_operand PARAMS ((rtx, enum machine_mode)); -extern int constant_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_cint_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_any_cint_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_D_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_add_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_and_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_mem_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_nonsymb_mem_operand PARAMS ((rtx, enum machine_mode)); -extern int romp_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_0_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_15_operand PARAMS ((rtx, enum machine_mode)); -extern int float_binary PARAMS ((rtx, enum machine_mode)); -extern int float_unary PARAMS ((rtx, enum machine_mode)); -extern int float_conversion PARAMS ((rtx, enum machine_mode)); -extern void romp_initialize_trampoline PARAMS ((rtx, rtx, rtx)); -#endif /* RTX_CODE */ - -extern int first_reg_to_save PARAMS ((void)); -extern int romp_pushes_stack PARAMS ((void)); -extern int romp_using_r14 PARAMS ((void)); -extern int null_epilogue PARAMS ((void)); -extern int romp_sa_size PARAMS ((void)); -extern int romp_makes_calls PARAMS ((void)); -extern void output_encoded_offset PARAMS ((FILE *, unsigned)); -extern int romp_debugger_auto_correction PARAMS ((int)); -extern int romp_debugger_arg_correction PARAMS ((int)); -extern const char *output_in_line_mul PARAMS ((void)); diff --git a/gcc/config/romp/romp.c b/gcc/config/romp/romp.c deleted file mode 100644 index ab4430279b3..00000000000 --- a/gcc/config/romp/romp.c +++ /dev/null @@ -1,2191 +0,0 @@ -/* Subroutines used for code generation on ROMP. - Copyright (C) 1990, 1991, 1992, 1993, 1997, 1998, 1999, 2000, 2002 - Free Software Foundation, Inc. - Contributed by Richard Kenner (kenner@nyu.edu) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - - -#include "config.h" -#include "system.h" -#include "coretypes.h" -#include "tm.h" -#include "rtl.h" -#include "regs.h" -#include "hard-reg-set.h" -#include "real.h" -#include "insn-config.h" -#include "conditions.h" -#include "output.h" -#include "insn-attr.h" -#include "flags.h" -#include "recog.h" -#include "obstack.h" -#include "tree.h" -#include "function.h" -#include "expr.h" -#include "ggc.h" -#include "toplev.h" -#include "tm_p.h" -#include "target.h" -#include "target-def.h" - -#define min(A,B) ((A) < (B) ? (A) : (B)) -#define max(A,B) ((A) > (B) ? (A) : (B)) - -static int unsigned_comparisons_p PARAMS ((rtx)); -static void output_loadsave_fpregs PARAMS ((FILE *, enum rtx_code, rtx)); -static void output_fpops PARAMS ((FILE *)); -static void init_fpops PARAMS ((void)); -static int memory_offset_in_range_p PARAMS ((rtx, enum machine_mode, int, int)); -static unsigned int hash_rtx PARAMS ((rtx)); -static void romp_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); -static void romp_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); -static void romp_select_rtx_section PARAMS ((enum machine_mode, rtx, - unsigned HOST_WIDE_INT)); -static void romp_encode_section_info PARAMS ((tree, rtx, int)); -static bool romp_rtx_costs PARAMS ((rtx, int, int, int *)); -static int romp_address_cost PARAMS ((rtx)); - -/* Initialize the GCC target structure. */ -#undef TARGET_ASM_FUNCTION_PROLOGUE -#define TARGET_ASM_FUNCTION_PROLOGUE romp_output_function_prologue -#undef TARGET_ASM_FUNCTION_EPILOGUE -#define TARGET_ASM_FUNCTION_EPILOGUE romp_output_function_epilogue -#undef TARGET_ASM_SELECT_RTX_SECTION -#define TARGET_ASM_SELECT_RTX_SECTION romp_select_rtx_section -#undef TARGET_ENCODE_SECTION_INFO -#define TARGET_ENCODE_SECTION_INFO romp_encode_section_info -#undef TARGET_RTX_COSTS -#define TARGET_RTX_COSTS romp_rtx_costs -#undef TARGET_ADDRESS_COST -#define TARGET_ADDRESS_COST romp_address_cost - -struct gcc_target targetm = TARGET_INITIALIZER; - -/* Return 1 if the insn using CC0 set by INSN does not contain - any unsigned tests applied to the condition codes. - - Based on `next_insn_tests_no_inequality' in recog.c. */ - -int -next_insn_tests_no_unsigned (insn) - rtx insn; -{ - register rtx next = next_cc0_user (insn); - - if (next == 0) - { - if (find_reg_note (insn, REG_UNUSED, cc0_rtx)) - return 1; - else - abort (); - } - - return ((GET_CODE (next) == JUMP_INSN - || GET_CODE (next) == INSN - || GET_CODE (next) == CALL_INSN) - && ! unsigned_comparisons_p (PATTERN (next))); -} - -static int -unsigned_comparisons_p (x) - rtx x; -{ - register const char *fmt; - register int len, i; - register enum rtx_code code = GET_CODE (x); - - switch (code) - { - case REG: - case PC: - case CC0: - case CONST_INT: - case CONST_DOUBLE: - case CONST: - case LABEL_REF: - case SYMBOL_REF: - return 0; - - case LTU: - case GTU: - case LEU: - case GEU: - return (XEXP (x, 0) == cc0_rtx || XEXP (x, 1) == cc0_rtx); - default: - break; - } - - len = GET_RTX_LENGTH (code); - fmt = GET_RTX_FORMAT (code); - - for (i = 0; i < len; i++) - { - if (fmt[i] == 'e') - { - if (unsigned_comparisons_p (XEXP (x, i))) - return 1; - } - else if (fmt[i] == 'E') - { - register int j; - for (j = XVECLEN (x, i) - 1; j >= 0; j--) - if (unsigned_comparisons_p (XVECEXP (x, i, j))) - return 1; - } - } - - return 0; -} - -/* Update the condition code from the insn. Look mostly at the first - byte of the machine-specific insn description information. - - cc_state.value[12] refer to two possible values that might correspond - to the CC. We only store register values. */ - -void -update_cc (body, insn) - rtx body ATTRIBUTE_UNUSED; - rtx insn; -{ - switch (get_attr_cc (insn)) - { - case CC_NONE: - /* Insn does not affect the CC at all. */ - break; - - case CC_CHANGE0: - /* Insn doesn't affect the CC but does modify operand[0], known to be - a register. */ - if (cc_status.value1 != 0 - && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) - cc_status.value1 = 0; - - if (cc_status.value2 != 0 - && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2)) - cc_status.value2 = 0; - - break; - - case CC_COPY1TO0: - /* Insn copies operand[1] to operand[0], both registers, but doesn't - affect the CC. */ - if (cc_status.value1 != 0 - && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) - cc_status.value1 = 0; - - if (cc_status.value2 != 0 - && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2)) - cc_status.value2 = 0; - - if (cc_status.value1 != 0 - && rtx_equal_p (cc_status.value1, recog_data.operand[1])) - cc_status.value2 = recog_data.operand[0]; - - if (cc_status.value2 != 0 - && rtx_equal_p (cc_status.value2, recog_data.operand[1])) - cc_status.value1 = recog_data.operand[0]; - - break; - - case CC_CLOBBER: - /* Insn clobbers CC. */ - CC_STATUS_INIT; - break; - - case CC_SETS: - /* Insn sets CC to recog_data.operand[0], but overflow is impossible. */ - CC_STATUS_INIT; - cc_status.flags |= CC_NO_OVERFLOW; - cc_status.value1 = recog_data.operand[0]; - break; - - case CC_COMPARE: - /* Insn is a compare which sets the CC fully. Update CC_STATUS for this - compare and mark whether the test will be signed or unsigned. */ - { - register rtx p = PATTERN (insn); - - CC_STATUS_INIT; - - if (GET_CODE (p) == PARALLEL) - p = XVECEXP (p, 0, 0); - cc_status.value1 = SET_SRC (p); - - if (GET_CODE (SET_SRC (p)) == REG) - cc_status.flags |= CC_NO_OVERFLOW; - if (! next_insn_tests_no_unsigned (insn)) - cc_status.flags |= CC_UNSIGNED; - } - break; - - case CC_TBIT: - /* Insn sets T bit if result is nonzero. Next insn must be branch. */ - CC_STATUS_INIT; - cc_status.flags = CC_IN_TB | CC_NOT_NEGATIVE; - break; - - default: - abort (); - } -} - -/* Return 1 if a previous compare needs to be re-issued. This will happen - if two compares tested the same objects, but one was signed and the - other unsigned. OP is the comparison operation being performed. */ - -int -restore_compare_p (op) - rtx op; -{ - enum rtx_code code = GET_CODE (op); - - return (((code == GEU || code == LEU || code == GTU || code == LTU) - && ! (cc_status.flags & CC_UNSIGNED)) - || ((code == GE || code == LE || code == GT || code == LT) - && (cc_status.flags & CC_UNSIGNED))); -} - -/* Generate the (long) string corresponding to an inline multiply insn. - Note that `r10' does not refer to the register r10, but rather to the - SCR used as the MQ. */ -const char * -output_in_line_mul () -{ - static char insns[200]; - int i; - - strcpy (insns, "s %0,%0\n"); - strcat (insns, "\tmts r10,%1\n"); - for (i = 0; i < 16; i++) - strcat (insns, "\tm %0,%2\n"); - strcat (insns, "\tmfs r10,%0"); - - return insns; -} - -/* Returns 1 if OP is a memory reference with an offset from a register within - the range specified. The offset must also be a multiple of the size of the - mode. */ - -static int -memory_offset_in_range_p (op, mode, low, high) - register rtx op; - enum machine_mode mode; - int low, high; -{ - int offset = 0; - - if (! memory_operand (op, mode)) - return 0; - - while (GET_CODE (op) == SUBREG) - { - offset += SUBREG_BYTE (op); - op = SUBREG_REG (op); - } - - /* We must now have either (mem (reg (x)), (mem (plus (reg (x)) (c))), - or a constant pool address. */ - if (GET_CODE (op) != MEM) - abort (); - - /* Now use the actual mode and get the address. */ - mode = GET_MODE (op); - op = XEXP (op, 0); - if (GET_CODE (op) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (op)) - offset = get_pool_offset (op) + 12; - else if (GET_CODE (op) == PLUS) - { - if (GET_CODE (XEXP (op, 1)) != CONST_INT - || ! register_operand (XEXP (op, 0), Pmode)) - return 0; - - offset += INTVAL (XEXP (op, 1)); - } - - else if (! register_operand (op, Pmode)) - return 0; - - return (offset >= low && offset <= high - && (offset % GET_MODE_SIZE (mode) == 0)); -} - -/* Return 1 if OP is a valid operand for a memory reference insn that can - only reference indirect through a register. */ - -int -zero_memory_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return memory_offset_in_range_p (op, mode, 0, 0); -} - -/* Return 1 if OP is a valid operand for a `short' memory reference insn. */ - -int -short_memory_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - if (mode == VOIDmode) - mode = GET_MODE (op); - - return memory_offset_in_range_p (op, mode, 0, - 15 * min (UNITS_PER_WORD, - GET_MODE_SIZE (mode))); -} - -/* Returns 1 if OP is a memory reference involving a symbolic constant - that is not in the constant pool. */ - -int -symbolic_memory_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - if (! memory_operand (op, mode)) - return 0; - - while (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - - if (GET_CODE (op) != MEM) - abort (); - - op = XEXP (op, 0); - if (constant_pool_address_operand (op, VOIDmode)) - return 0; - else - return romp_symbolic_operand (op, Pmode) - || (GET_CODE (op) == PLUS && register_operand (XEXP (op, 0), Pmode) - && romp_symbolic_operand (XEXP (op, 1), Pmode)); -} - - -/* Returns 1 if OP is a constant pool reference to the current function. */ - -int -current_function_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - if (GET_CODE (op) != MEM || GET_CODE (XEXP (op, 0)) != SYMBOL_REF - || ! CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) - return 0; - - op = get_pool_constant (XEXP (op, 0)); - return (GET_CODE (op) == SYMBOL_REF - && ! strcmp (current_function_name, XSTR (op, 0))); -} - -/* Return nonzero if this function is known to have a null epilogue. */ - -int -null_epilogue () -{ - return (reload_completed - && first_reg_to_save () == 16 - && ! romp_pushes_stack ()); -} - -/* Returns 1 if OP is the address of a location in the constant pool. */ - -int -constant_pool_address_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return ((GET_CODE (op) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (op)) - || (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == PLUS - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT - && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF - && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (op, 0), 0)))); -} - -/* Returns 1 if OP is either a symbol reference or a sum of a symbol - reference and a constant. */ - -int -romp_symbolic_operand (op, mode) - register rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - switch (GET_CODE (op)) - { - case SYMBOL_REF: - case LABEL_REF: - return ! op->integrated; - - case CONST: - op = XEXP (op, 0); - return (GET_CODE (XEXP (op, 0)) == SYMBOL_REF - || GET_CODE (XEXP (op, 0)) == LABEL_REF) - && GET_CODE (XEXP (op, 1)) == CONST_INT; - - default: - return 0; - } -} - -/* Returns 1 if OP is a valid constant for the ROMP. */ - -int -constant_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - switch (GET_CODE (op)) - { - case LABEL_REF: - case SYMBOL_REF: - case PLUS: - case CONST: - return romp_symbolic_operand (op,mode); - - case CONST_INT: - return (unsigned int) (INTVAL (op) + 0x8000) < 0x10000 - || (INTVAL (op) & 0xffff) == 0 || (INTVAL (op) & 0xffff0000) == 0; - - default: - return 0; - } -} - -/* Returns 1 if OP is either a constant integer valid for the ROMP or a - register. If a register, it must be in the proper mode unless MODE is - VOIDmode. */ - -int -reg_or_cint_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - if (GET_CODE (op) == CONST_INT) - return constant_operand (op, mode); - - return register_operand (op, mode); -} - -/* Return 1 is the operand is either a register or ANY constant integer. */ - -int -reg_or_any_cint_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - return GET_CODE (op) == CONST_INT || register_operand (op, mode); -} - -/* Return 1 if the operand is either a register or a valid D-type operand. */ - -int -reg_or_D_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - if (GET_CODE (op) == CONST_INT) - return (unsigned) (INTVAL (op) + 0x8000) < 0x10000; - - return register_operand (op, mode); -} - -/* Return 1 if the operand is either a register or an item that can be - used as the operand of an SI add insn. */ - -int -reg_or_add_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - return reg_or_D_operand (op, mode) || romp_symbolic_operand (op, mode) - || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0); -} - -/* Return 1 if the operand is either a register or an item that can be - used as the operand of a ROMP logical AND insn. */ - -int -reg_or_and_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - if (reg_or_cint_operand (op, mode)) - return 1; - - if (GET_CODE (op) != CONST_INT) - return 0; - - return (INTVAL (op) & 0xffff) == 0xffff - || (INTVAL (op) & 0xffff0000) == 0xffff0000; -} - -/* Return 1 if the operand is a register or memory operand. */ - -int -reg_or_mem_operand (op, mode) - register rtx op; - register enum machine_mode mode; -{ - return register_operand (op, mode) || memory_operand (op, mode); -} - -/* Return 1 if the operand is either a register or a memory operand that is - not symbolic. */ - -int -reg_or_nonsymb_mem_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - if (register_operand (op, mode)) - return 1; - - if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) - return 1; - - return 0; -} - -/* Return 1 if this operand is valid for the ROMP. This is any operand except - certain constant integers. */ - -int -romp_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - if (GET_CODE (op) == CONST_INT) - return constant_operand (op, mode); - - return general_operand (op, mode); -} - -/* Return 1 if the operand is (reg:mode 0). */ - -int -reg_0_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return ((mode == VOIDmode || mode == GET_MODE (op)) - && GET_CODE (op) == REG && REGNO (op) == 0); -} - -/* Return 1 if the operand is (reg:mode 15). */ - -int -reg_15_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return ((mode == VOIDmode || mode == GET_MODE (op)) - && GET_CODE (op) == REG && REGNO (op) == 15); -} - -/* Return 1 if this is a binary floating-point operation. */ - -int -float_binary (op, mode) - register rtx op; - enum machine_mode mode; -{ - if (mode != VOIDmode && mode != GET_MODE (op)) - return 0; - - if (GET_MODE (op) != SFmode && GET_MODE (op) != DFmode) - return 0; - - switch (GET_CODE (op)) - { - case PLUS: - case MINUS: - case MULT: - case DIV: - return GET_MODE (XEXP (op, 0)) == GET_MODE (op) - && GET_MODE (XEXP (op, 1)) == GET_MODE (op); - - default: - return 0; - } -} - -/* Return 1 if this is a unary floating-point operation. */ - -int -float_unary (op, mode) - register rtx op; - enum machine_mode mode; -{ - if (mode != VOIDmode && mode != GET_MODE (op)) - return 0; - - if (GET_MODE (op) != SFmode && GET_MODE (op) != DFmode) - return 0; - - return (GET_CODE (op) == NEG || GET_CODE (op) == ABS) - && GET_MODE (XEXP (op, 0)) == GET_MODE (op); -} - -/* Return 1 if this is a valid floating-point conversion that can be done - as part of an operation by the RT floating-point routines. */ - -int -float_conversion (op, mode) - register rtx op; - enum machine_mode mode; -{ - if (mode != VOIDmode && mode != GET_MODE (op)) - return 0; - - switch (GET_CODE (op)) - { - case FLOAT_TRUNCATE: - return GET_MODE (op) == SFmode && GET_MODE (XEXP (op, 0)) == DFmode; - - case FLOAT_EXTEND: - return GET_MODE (op) == DFmode && GET_MODE (XEXP (op, 0)) == SFmode; - - case FLOAT: - return ((GET_MODE (XEXP (op, 0)) == SImode - || GET_CODE (XEXP (op, 0)) == CONST_INT) - && (GET_MODE (op) == SFmode || GET_MODE (op) == DFmode)); - - case FIX: - return ((GET_MODE (op) == SImode - || GET_CODE (XEXP (op, 0)) == CONST_INT) - && (GET_MODE (XEXP (op, 0)) == SFmode - || GET_MODE (XEXP (op, 0)) == DFmode)); - - default: - return 0; - } -} - -/* Print an operand. Recognize special options, documented below. */ - -void -print_operand (file, x, code) - FILE *file; - rtx x; - int code; -{ - int i; - - switch (code) - { - case 'B': - /* Byte number (const/8) */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%B value"); - - fprintf (file, "%d", INTVAL (x) / 8); - break; - - case 'L': - /* Low order 16 bits of constant. */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%L value"); - - fprintf (file, "%d", INTVAL (x) & 0xffff); - break; - - case 's': - /* Null or "16" depending on whether the constant is greater than 16. */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%s value"); - - if (INTVAL (x) >= 16) - fprintf (file, "16"); - - break; - - case 'S': - /* For shifts: 's' will have given the half. Just give the amount - within 16. */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%S value"); - - fprintf (file, "%d", INTVAL (x) & 15); - break; - - case 'b': - /* The number of a single bit set or cleared, mod 16. Note that the ROMP - numbers bits with the high-order bit 31. */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%b value"); - - if ((i = exact_log2 (INTVAL (x))) >= 0) - fprintf (file, "%d", (31 - i) % 16); - else if ((i = exact_log2 (~ INTVAL (x))) >= 0) - fprintf (file, "%d", (31 - i) % 16); - else - output_operand_lossage ("invalid %%b value"); - - break; - - case 'h': - /* "l" or "u" depending on which half of the constant is zero. */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%h value"); - - if ((INTVAL (x) & 0xffff0000) == 0) - fprintf (file, "l"); - else if ((INTVAL (x) & 0xffff) == 0) - fprintf (file, "u"); - else - output_operand_lossage ("invalid %%h value"); - - break; - - case 'H': - /* Upper or lower half, depending on which half is zero. */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%H value"); - - if ((INTVAL (x) & 0xffff0000) == 0) - fprintf (file, "%d", INTVAL (x) & 0xffff); - else if ((INTVAL (x) & 0xffff) == 0) - fprintf (file, "%d", (INTVAL (x) >> 16) & 0xffff); - else - output_operand_lossage ("invalid %%H value"); - - break; - - case 'z': - /* Write two characters: - 'lo' if the high order part is all ones - 'lz' if the high order part is all zeros - 'uo' if the low order part is all ones - 'uz' if the low order part is all zeros - */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%z value"); - - if ((INTVAL (x) & 0xffff0000) == 0) - fprintf (file, "lz"); - else if ((INTVAL (x) & 0xffff0000) == 0xffff0000) - fprintf (file, "lo"); - else if ((INTVAL (x) & 0xffff) == 0) - fprintf (file, "uz"); - else if ((INTVAL (x) & 0xffff) == 0xffff) - fprintf (file, "uo"); - else - output_operand_lossage ("invalid %%z value"); - - break; - - case 'Z': - /* Upper or lower half, depending on which is nonzero or not - all ones. Must be consistent with 'z' above. */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%Z value"); - - if ((INTVAL (x) & 0xffff0000) == 0 - || (INTVAL (x) & 0xffff0000) == 0xffff0000) - fprintf (file, "%d", INTVAL (x) & 0xffff); - else if ((INTVAL (x) & 0xffff) == 0 || (INTVAL (x) & 0xffff) == 0xffff) - fprintf (file, "%d", (INTVAL (x) >> 16) & 0xffff); - else - output_operand_lossage ("invalid %%Z value"); - - break; - - case 'k': - /* Same as 'z', except the trailing 'o' or 'z' is not written. */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%k value"); - - if ((INTVAL (x) & 0xffff0000) == 0 - || (INTVAL (x) & 0xffff0000) == 0xffff0000) - fprintf (file, "l"); - else if ((INTVAL (x) & 0xffff) == 0 - || (INTVAL (x) & 0xffff) == 0xffff) - fprintf (file, "u"); - else - output_operand_lossage ("invalid %%k value"); - - break; - - case 't': - /* Similar to 's', except that we write 'h' or 'u'. */ - if (GET_CODE (x) != CONST_INT) - output_operand_lossage ("invalid %%k value"); - - if (INTVAL (x) < 16) - fprintf (file, "u"); - else - fprintf (file, "l"); - break; - - case 'M': - /* For memory operations, write 's' if the operand is a short - memory operand. */ - if (short_memory_operand (x, VOIDmode)) - fprintf (file, "s"); - break; - - case 'N': - /* Like 'M', but check for zero memory offset. */ - if (zero_memory_operand (x, VOIDmode)) - fprintf (file, "s"); - break; - - case 'O': - /* Write low-order part of DImode or DFmode. Supported for MEM - and REG only. */ - if (GET_CODE (x) == REG) - fprintf (file, "%s", reg_names[REGNO (x) + 1]); - else if (GET_CODE (x) == MEM) - print_operand (file, gen_rtx_MEM (GET_MODE (x), - plus_constant (XEXP (x, 0), 4)), 0); - else - abort (); - break; - - case 'C': - /* Offset in constant pool for constant pool address. */ - if (! constant_pool_address_operand (x, VOIDmode)) - abort (); - if (GET_CODE (x) == SYMBOL_REF) - fprintf (file, "%d", get_pool_offset (x) + 12); - else - /* Must be (const (plus (symbol_ref) (const_int))) */ - fprintf (file, "%d", - (get_pool_offset (XEXP (XEXP (x, 0), 0)) + 12 - + INTVAL (XEXP (XEXP (x, 0), 1)))); - break; - - case 'j': - /* Branch opcode. Check for condition in test bit for eq/ne. */ - switch (GET_CODE (x)) - { - case EQ: - if (cc_status.flags & CC_IN_TB) - fprintf (file, "ntb"); - else - fprintf (file, "eq"); - break; - - case NE: - if (cc_status.flags & CC_IN_TB) - fprintf (file, "tb"); - else - fprintf (file, "ne"); - break; - - case GT: - case GTU: - fprintf (file, "h"); - break; - - case LT: - case LTU: - fprintf (file, "l"); - break; - - case GE: - case GEU: - fprintf (file, "he"); - break; - - case LE: - case LEU: - fprintf (file, "le"); - break; - - default: - output_operand_lossage ("invalid %%j value"); - } - break; - - case 'J': - /* Reversed branch opcode. */ - switch (GET_CODE (x)) - { - case EQ: - if (cc_status.flags & CC_IN_TB) - fprintf (file, "tb"); - else - fprintf (file, "ne"); - break; - - case NE: - if (cc_status.flags & CC_IN_TB) - fprintf (file, "ntb"); - else - fprintf (file, "eq"); - break; - - case GT: - case GTU: - fprintf (file, "le"); - break; - - case LT: - case LTU: - fprintf (file, "he"); - break; - - case GE: - case GEU: - fprintf (file, "l"); - break; - - case LE: - case LEU: - fprintf (file, "h"); - break; - - default: - output_operand_lossage ("invalid %%j value"); - } - break; - - case '.': - /* Output nothing. Used as delimiter in, e.g., "mc%B1%.3 " */ - break; - - case '#': - /* Output 'x' if this insn has a delay slot, else nothing. */ - if (dbr_sequence_length ()) - fprintf (file, "x"); - break; - - case 0: - if (GET_CODE (x) == REG) - fprintf (file, "%s", reg_names[REGNO (x)]); - else if (GET_CODE (x) == MEM) - { - if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF - && current_function_operand (x, Pmode)) - fprintf (file, "r14"); - else - output_address (XEXP (x, 0)); - } - else - output_addr_const (file, x); - break; - - default: - output_operand_lossage ("invalid %%xn code"); - } -} - -/* This page contains routines that are used to determine what the function - prologue and epilogue code will do and write them out. */ - -/* Return the first register that is required to be saved. 16 if none. */ - -int -first_reg_to_save() -{ - int first_reg; - - /* Find lowest numbered live register. */ - for (first_reg = 6; first_reg <= 15; first_reg++) - if (regs_ever_live[first_reg]) - break; - - /* If we think that we do not have to save r14, see if it will be used - to be sure. */ - if (first_reg > 14 && romp_using_r14 ()) - first_reg = 14; - - return first_reg; -} - -/* Compute the size of the save area in the stack, including the space for - the first four incoming arguments. */ - -int -romp_sa_size () -{ - int size; - int i; - - /* We have the 4 words corresponding to the arguments passed in registers, - 4 reserved words, space for static chain, general register save area, - and floating-point save area. */ - size = 4 + 4 + 1 + (16 - first_reg_to_save ()); - - /* The documentation says we have to leave 18 words in the save area if - any floating-point registers at all are saved, not the three words - per register you might otherwise expect. */ - for (i = 2 + (TARGET_FP_REGS != 0); i <= 7; i++) - if (regs_ever_live[i + 17]) - { - size += 18; - break; - } - - return size * 4; -} - -/* Return nonzero if this function makes calls or has fp operations - (which are really calls). */ - -int -romp_makes_calls () -{ - rtx insn; - - for (insn = get_insns (); insn; insn = next_insn (insn)) - { - if (GET_CODE (insn) == CALL_INSN) - return 1; - else if (GET_CODE (insn) == INSN) - { - rtx body = PATTERN (insn); - - if (GET_CODE (body) != USE && GET_CODE (body) != CLOBBER - && GET_CODE (body) != ADDR_VEC - && GET_CODE (body) != ADDR_DIFF_VEC - && get_attr_type (insn) == TYPE_FP) - return 1; - } - } - - return 0; -} - -/* Return nonzero if this function will use r14 as a pointer to its - constant pool. */ - -int -romp_using_r14 () -{ - /* If we are debugging, profiling, have a non-empty constant pool, or - call a function, we need r14. */ - return (write_symbols != NO_DEBUG || current_function_profile - || get_pool_size () != 0 || romp_makes_calls ()); -} - -/* Return nonzero if this function needs to push space on the stack. */ - -int -romp_pushes_stack () -{ - /* We need to push the stack if a frame pointer is needed (because the - stack might be dynamically adjusted), if we are debugging, if the - total required size is more than 100 bytes, or if we make calls. */ - - return (frame_pointer_needed || write_symbols != NO_DEBUG - || (romp_sa_size () + get_frame_size ()) > 100 - || romp_makes_calls ()); -} - -/* Write function prologue. - - We compute the size of the fixed area required as follows: - - We always allocate 4 words for incoming arguments, 4 word reserved, 1 - word for static link, as many words as required for general register - save area, plus 2 words for each FP reg 2-7 that must be saved. */ - -static void -romp_output_function_prologue (file, size) - FILE *file; - HOST_WIDE_INT size; -{ - int first_reg; - int reg_save_offset; - HOST_WIDE_INT fp_save = size + current_function_outgoing_args_size; - - init_fpops (); - - /* Add in fixed size plus output argument area. */ - size += romp_sa_size () + current_function_outgoing_args_size; - - /* Compute first register to save and perform the save operation if anything - needs to be saved. */ - first_reg = first_reg_to_save(); - reg_save_offset = - (4 + 4 + 1 + (16 - first_reg)) * 4; - if (first_reg == 15) - fprintf (file, "\tst r15,%d(r1)\n", reg_save_offset); - else if (first_reg < 16) - fprintf (file, "\tstm r%d,%d(r1)\n", first_reg, reg_save_offset); - - /* Set up pointer to data area if it is needed. */ - if (romp_using_r14 ()) - fprintf (file, "\tcas r14,r0,r0\n"); - - /* Set up frame pointer if needed. */ - if (frame_pointer_needed) - fprintf (file, "\tcal r13,-%d(r1)\n", romp_sa_size () + 64); - - /* Push stack if neeeded. There are a couple of ways of doing this. */ - if (romp_pushes_stack ()) - { - if (size >= 32768) - { - if (size >= 65536) - { - fprintf (file, "\tcau r0,%d(r0)\n", size >> 16); - fprintf (file, "\toil r0,r0,%d\n", size & 0xffff); - } - else - fprintf (file, "\tcal16 r0,%d(r0)\n", size); - fprintf (file, "\ts r1,r0\n"); - } - else - fprintf (file, "\tcal r1,-%d(r1)\n", size); - } - - /* Save floating-point registers. */ - output_loadsave_fpregs (file, USE, - plus_constant (stack_pointer_rtx, fp_save)); -} - -/* Output the offset information used by debuggers. - This is the exactly the total_size value of output_function_epilogue() - which is added to the frame pointer. However the value in the debug - table is encoded in a space-saving way as follows: - - The first byte contains two fields: a 2-bit size field and the first - 6 bits of an offset value. The 2-bit size field is in the high-order - position and specifies how many subsequent bytes follow after - this one. An offset value is at most 4-bytes long. - - The last 6 bits of the first byte initialize the offset value. In many - cases where procedures have small local storage, this is enough and, in - this case, the high-order size field is zero so the byte can (almost) be - used as is (see below). Thus, the byte value of 0x0d is encodes an offset - size of 13 words, or 52 bytes. - - For procedures with a local space larger than 60 bytes, the 6 bits - are the high-order 6 bits. The remaining bytes follow as necessary, - in Big Endian order. Thus, the short value of 16907 (= 16384+523) - encodes an offset of 2092 bytes (523 words). - - The total offset value is in words (not bytes), so the final value has to - be multiplied by 4 before it can be used in address computations by a - debugger. */ - -void -output_encoded_offset (file, reg_offset) - FILE *file; - unsigned reg_offset; -{ - /* Convert the offset value to 4-byte words rather than bytes. */ - reg_offset = (reg_offset + 3) / 4; - - /* Now output 1-4 bytes in encoded form. */ - if (reg_offset < (1 << 6)) - /* Fits into one byte */ - fprintf (file, "\t.byte %d\n", reg_offset); - else if (reg_offset < (1 << (6 + 8))) - /* Fits into two bytes */ - fprintf (file, "\t.short %d\n", (1 << (6 + 8)) + reg_offset); - else if (reg_offset < (1 << (6 + 8 + 8))) - { - /* Fits in three bytes */ - fprintf (file, "\t.byte %d\n", (2 << 6) + (reg_offset >> ( 6+ 8))); - fprintf (file, "\t.short %d\n", reg_offset % (1 << (6 + 8))); - } - else - { - /* Use 4 bytes. */ - fprintf (file, "\t.short %d", (3 << (6 + 8)) + (reg_offset >> (6 + 8))); - fprintf (file, "\t.short %d\n", reg_offset % (1 << (6 + 8))); - } -} - -/* Write function epilogue. */ - -static void -romp_output_function_epilogue (file, size) - FILE *file; - HOST_WIDE_INT size; -{ - int first_reg = first_reg_to_save(); - int pushes_stack = romp_pushes_stack (); - int reg_save_offset = - ((16 - first_reg) + 1 + 4 + 4) * 4; - HOST_WIDE_INT total_size = (size + romp_sa_size () - + current_function_outgoing_args_size); - HOST_WIDE_INT fp_save = size + current_function_outgoing_args_size; - int long_frame = total_size >= 32768; - rtx insn = get_last_insn (); - int write_code = 1; - - int nargs = 0; /* words of arguments */ - tree argptr; - - /* Compute the number of words of arguments. Since this is just for - the traceback table, we ignore arguments that don't have a size or - don't have a fixed size. */ - - for (argptr = DECL_ARGUMENTS (current_function_decl); - argptr; argptr = TREE_CHAIN (argptr)) - { - int this_size = int_size_in_bytes (TREE_TYPE (argptr)); - - if (this_size > 0) - nargs += (this_size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; - } - - /* If the last insn was a BARRIER, we don't have to write anything except - the trace table. */ - if (GET_CODE (insn) == NOTE) - insn = prev_nonnote_insn (insn); - if (insn && GET_CODE (insn) == BARRIER) - write_code = 0; - - /* Restore floating-point registers. */ - if (write_code) - output_loadsave_fpregs (file, CLOBBER, - plus_constant (gen_rtx_REG (Pmode, 1), fp_save)); - - /* If we push the stack and do not have size > 32K, adjust the register - save location to the current position of sp. Otherwise, if long frame, - restore sp from fp. */ - if (pushes_stack && ! long_frame) - reg_save_offset += total_size; - else if (long_frame && write_code) - fprintf (file, "\tcal r1,%d(r13)\n", romp_sa_size () + 64); - - /* Restore registers. */ - if (first_reg == 15 && write_code) - fprintf (file, "\tl r15,%d(r1)\n", reg_save_offset); - else if (first_reg < 16 && write_code) - fprintf (file, "\tlm r%d,%d(r1)\n", first_reg, reg_save_offset); - if (first_reg == 16) first_reg = 0; - - /* Handle popping stack, if needed and write debug table entry. */ - if (pushes_stack) - { - if (write_code) - { - if (long_frame) - fprintf (file, "\tbr r15\n"); - else - fprintf (file, "\tbrx r15\n\tcal r1,%d(r1)\n", total_size); - } - - /* Table header (0xdf), usual-type stack frame (0x07), - table header (0xdf), and first register saved. - - The final 0x08 means that there is a byte following this one - describing the number of parameter words and the register used as - stack pointer. - - If GCC passed floating-point parameters in floating-point registers, - it would be necessary to change the final byte from 0x08 to 0x0c. - Also an additional entry byte would be need to be emitted to specify - the first floating-point register. - - (See also Section 11 (Trace Tables) in ``IBM/4.3 Linkage Convention,'' - pages IBM/4.3-PSD:5-7 of Volume III of the IBM Academic Operating - System Manual dated July 1987.) */ - - fprintf (file, "\t.long 0x%x\n", 0xdf07df08 + first_reg * 0x10); - - if (nargs > 15) nargs = 15; - - /* The number of parameter words and the register used as the stack - pointer (encoded here as r1). - - Note: The MetWare Hich C Compiler R2.1y actually gets this wrong; - it erroneously lists r13 but uses r1 as the stack too. But a bug in - dbx 1.5 nullifies this mistake---most of the time. - (Dbx retrieves the value of r13 saved on the stack which is often - the value of r1 before the call.) */ - - fprintf (file, "\t.byte 0x%x1\n", nargs); - output_encoded_offset (file, total_size); - } - else - { - if (write_code) - fprintf (file, "\tbr r15\n"); - - /* Table header (0xdf), no stack frame (0x02), - table header (0xdf) and no parameters saved (0x00). - - If GCC passed floating-point parameters in floating-point registers, - it might be necessary to change the final byte from 0x00 to 0x04. - Also a byte would be needed to specify the first floating-point - register. */ - fprintf (file, "\t.long 0xdf02df00\n"); - } - - /* Output any pending floating-point operations. */ - output_fpops (file); -} - -/* For the ROMP we need to make new SYMBOL_REFs for the actual name of a - called routine. To keep them unique we maintain a hash table of all - that have been created so far. */ - -struct symref_hashent { - rtx symref; /* Created SYMBOL_REF rtx. */ - struct symref_hashent *next; /* Next with same hash code. */ -}; - -#define SYMHASHSIZE 151 -#define HASHBITS 65535 - -/* Define the hash table itself. */ - -static struct symref_hashent *symref_hash_table[SYMHASHSIZE]; - -/* Given a name (allocable in temporary storage), return a SYMBOL_REF - for the name. The rtx is allocated from the current rtl_obstack, while - the name string is allocated from the permanent obstack. */ -rtx -get_symref (name) - register const char *name; -{ - register const char *sp = name; - unsigned int hash = 0; - struct symref_hashent *p, **last_p; - - /* Compute the hash code for the string. */ - while (*sp) - hash = (hash << 4) + *sp++; - - /* Search for a matching entry in the hash table, keeping track of the - insertion location as we do so. */ - hash = (hash & HASHBITS) % SYMHASHSIZE; - for (last_p = &symref_hash_table[hash], p = *last_p; - p; last_p = &p->next, p = *last_p) - if (strcmp (name, XSTR (p->symref, 0)) == 0) - break; - - /* If couldn't find matching SYMBOL_REF, make a new one. */ - if (p == 0) - { - /* Ensure SYMBOL_REF will stay around. */ - p = *last_p = (struct symref_hashent *) - xmalloc (sizeof (struct symref_hashent)); - p->symref = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); - p->next = 0; - } - - return p->symref; -} - -/* Validate the precision of a floating-point operation. - - We merge conversions from integers and between floating-point modes into - the insn. However, this must not effect the desired precision of the - insn. The RT floating-point system uses the widest of the operand modes. - If this should be a double-precision insn, ensure that one operand - passed to the floating-point processor has double mode. - - Note that since we don't check anything if the mode is single precision, - it, strictly speaking, isn't necessary to call this for those insns. - However, we do so in case something else needs to be checked in the - future. - - This routine returns 1 if the operation is OK. */ - -int -check_precision (opmode, op1, op2) - enum machine_mode opmode; - rtx op1, op2; -{ - if (opmode == SFmode) - return 1; - - /* If operand is not a conversion from an integer mode or an extension from - single-precision, it must be a double-precision value. */ - if (GET_CODE (op1) != FLOAT && GET_CODE (op1) != FLOAT_EXTEND) - return 1; - - if (op2 && GET_CODE (op2) != FLOAT && GET_CODE (op2) != FLOAT_EXTEND) - return 1; - - return 0; -} - -/* Floating-point on the RT is done by creating an operation block in the data - area that describes the operation. If two floating-point operations are the - same in a single function, they can use the same block. - - These routines are responsible for managing these blocks. */ - -/* Structure to describe a floating-point operation. */ - -struct fp_op { - struct fp_op *next_same_hash; /* Next op with same hash code. */ - struct fp_op *next_in_mem; /* Next op in memory. */ - int mem_offset; /* Offset from data area. */ - short size; /* Size of block in bytes. */ - short noperands; /* Number of operands in block. */ - rtx ops[3]; /* RTL for operands. */ - enum rtx_code opcode; /* Operation being performed. */ -}; - -/* Size of hash table. */ -#define FP_HASH_SIZE 101 - -/* Hash table of floating-point operation blocks. */ -static struct fp_op *fp_hash_table[FP_HASH_SIZE]; - -/* First floating-point block in data area. */ -static struct fp_op *first_fpop; - -/* Last block in data area so far. */ -static struct fp_op *last_fpop_in_mem; - -/* Subroutine number in file, to get unique "LF" labels. */ -static int subr_number = 0; - -/* Current word offset in data area (includes header and any constant pool). */ -int data_offset; - -/* Compute hash code for an RTX used in floating-point. */ - -static unsigned int -hash_rtx (x) - register rtx x; -{ - register unsigned int hash = (((int) GET_CODE (x) << 10) - + ((int) GET_MODE (x) << 20)); - register int i; - register const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); - - for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) - if (fmt[i] == 'e') - hash += hash_rtx (XEXP (x, i)); - else if (fmt[i] == 'u') - hash += (unsigned HOST_WIDE_INT) XEXP (x, i); - else if (fmt[i] == 'i') - hash += XINT (x, i); - else if (fmt[i] == 's') - hash += (unsigned HOST_WIDE_INT) XSTR (x, i); - - return hash; -} - -/* Given an operation code and up to three operands, return a character string - corresponding to the code to emit to branch to a floating-point operation - block. INSN is provided to see if the delay slot has been filled or not. - - A new floating-point operation block is created if this operation has not - been seen before. */ - -const char * -output_fpop (code, op0, op1, op2, insn) - enum rtx_code code; - rtx op0, op1, op2; - rtx insn ATTRIBUTE_UNUSED; -{ - static char outbuf[40]; - unsigned int hash, hash0, hash1, hash2; - int size, i; - register struct fp_op *fpop, *last_fpop; - int dyadic = (op2 != 0); - enum machine_mode opmode; - int noperands; - rtx tem; - unsigned int tem_hash; - int fr0_avail = 0; - - /* Compute hash code for each operand. If the operation is commutative, - put the one with the smaller hash code first. This will make us see - more operations as identical. */ - hash0 = op0 ? hash_rtx (op0) : 0; - hash1 = op1 ? hash_rtx (op1) : 0; - hash2 = op2 ? hash_rtx (op2) : 0; - - if (hash0 > hash1 && code == EQ) - { - tem = op0; op0 = op1; op1 = tem; - tem_hash = hash0; hash0 = hash1; hash1 = tem_hash; - } - else if (hash1 > hash2 && (code == PLUS || code == MULT)) - { - tem = op1; op1 = op2; op2 = tem; - tem_hash = hash1; hash1 = hash2; hash2 = tem_hash; - } - - /* If operation is commutative and the first and third operands are equal, - swap the second and third operands. Note that we must consider two - operands equal if they are the same register even if different modes. */ - if (op2 && (code == PLUS || code == MULT) - && (rtx_equal_p (op0, op2) - || (GET_CODE (op0) == REG && GET_CODE (op2) == REG - && REGNO (op0) == REGNO (op2)))) - { - tem = op1; op1 = op2; op2 = tem; - tem_hash = hash1; hash1 = hash2; hash2 = tem_hash; - } - - /* If the first and second operands are the same, merge them. Don't do this - for SFmode or SImode in general registers because this triggers a bug in - the RT fp code. */ - if (op1 && rtx_equal_p (op0, op1) - && code != EQ && code != GE && code != SET - && ((GET_MODE (op1) != SFmode && GET_MODE (op1) != SImode) - || GET_CODE (op0) != REG || FP_REGNO_P (REGNO (op0)))) - { - op1 = op2; - op2 = 0; - } - - noperands = 1 + (op1 != 0) + (op2 != 0); - - /* Compute hash code for entire expression and see if operation block - already exists. */ - hash = ((int) code << 13) + (hash0 << 2) + (hash1 << 1) + hash2; - - hash %= FP_HASH_SIZE; - for (fpop = fp_hash_table[hash], last_fpop = 0; - fpop; - last_fpop = fpop, fpop = fpop->next_same_hash) - if (fpop->opcode == code && noperands == fpop->noperands - && (op0 == 0 || rtx_equal_p (op0, fpop->ops[0])) - && (op1 == 0 || rtx_equal_p (op1, fpop->ops[1])) - && (op2 == 0 || rtx_equal_p (op2, fpop->ops[2]))) - goto win; - - /* We have never seen this operation before. */ - fpop = (struct fp_op *) xmalloc (sizeof (struct fp_op)); - fpop->mem_offset = data_offset; - fpop->opcode = code; - fpop->noperands = noperands; - fpop->ops[0] = op0; - fpop->ops[1] = op1; - fpop->ops[2] = op2; - - /* Compute the size using the rules in Appendix A of the RT Linkage - Convention (4.3/RT-PSD:5) manual. These rules are a bit ambiguous, - but if we guess wrong, it will effect only efficiency, not correctness. */ - - /* Size = 24 + 32 for each non-fp (or fr7) */ - size = 24; - if (op0 && (GET_CODE (op0) != REG - || ! FP_REGNO_P (REGNO (op0)) || REGNO (op0) == 23)) - size += 32; - - if (op1 && (GET_CODE (op1) != REG - || ! FP_REGNO_P (REGNO (op1)) || REGNO (op1) == 23)) - size += 32; - - if (op2 && (GET_CODE (op2) != REG - || ! FP_REGNO_P (REGNO (op2)) || REGNO (op2) == 23)) - size += 32; - - /* Size + 12 for each conversion. First get operation mode. */ - if ((op0 && GET_MODE (op0) == DFmode) - || (op1 && GET_MODE (op1) == DFmode) - || (op2 && GET_MODE (op2) == DFmode)) - opmode = DFmode; - else - opmode = SFmode; - - if (op0 && GET_MODE (op0) != opmode) - size += 12; - if (op1 && GET_MODE (op1) != opmode) - size += 12; - if (op2 && GET_MODE (op2) != opmode) - size += 12; - - /* 12 more if first and third operand types not the same. */ - if (op2 && GET_MODE (op0) != GET_MODE (op2)) - size += 12; - - /* CMP and CMPT need additional. Also, compute size of save/restore here. */ - if (code == EQ) - size += 32; - else if (code == GE) - size += 64; - else if (code == USE || code == CLOBBER) - { - /* 34 + 24 for each additional register plus 8 if fr7 saved. (We - call it 36 because we need to keep the block length a multiple - of four. */ - size = 36 - 24; - for (i = 0; i <= 7; i++) - if (INTVAL (op0) & (1 << (7-i))) - size += 24 + 8 * (i == 7); - } - - /* We provide no general-purpose scratch registers. */ - size +=16; - - /* No floating-point scratch registers are provided. Compute extra - length due to this. This logic is that shown in the referenced - appendix. */ - - i = 0; - if (op0 && GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0))) - i++; - if (op1 && GET_CODE (op1) == REG && FP_REGNO_P (REGNO (op1))) - i++; - if (op2 && GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2))) - i++; - - if ((op0 == 0 || GET_CODE (op0) != REG || REGNO(op0) != 17) - && (op1 == 0 || GET_CODE (op1) != REG || REGNO(op1) != 17) - && (op2 == 0 || GET_CODE (op2) != REG || REGNO(op2) != 17)) - fr0_avail = 1; - - if (dyadic) - { - if (i == 0) - size += fr0_avail ? 64 : 112; - else if (fpop->noperands == 2 && i == 1) - size += fr0_avail ? 0 : 64; - else if (fpop->noperands == 3) - { - if (GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0)) - && GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2))) - { - if (REGNO (op0) == REGNO (op2)) -#if 1 - /* This triggers a bug on the RT. */ - abort (); -#else - size += fr0_avail ? 0 : 64; -#endif - } - else - { - i = 0; - if (GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0))) - i++; - if (GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2))) - i++; - if (i == 0) - size += fr0_avail ? 64 : 112; - else if (i == 1) - size += fr0_avail ? 0 : 64; - } - } - } - else if (code != USE && code != CLOBBER - && (GET_CODE (op0) != REG || ! FP_REGNO_P (REGNO (op0)))) - size += 64; - - if (! TARGET_FULL_FP_BLOCKS) - { - /* If we are not to pad the blocks, just compute its actual length. */ - size = 12; /* Header + opcode */ - if (code == USE || code == CLOBBER) - size += 2; - else - { - if (op0) size += 2; - if (op1) size += 2; - if (op2) size += 2; - } - - /* If in the middle of a word, round. */ - if (size % UNITS_PER_WORD) - size += 2; - - /* Handle any immediates. */ - if (code != USE && code != CLOBBER && op0 && GET_CODE (op0) != REG) - size += 4; - if (op1 && GET_CODE (op1) != REG) - size += 4; - if (op2 && GET_CODE (op2) != REG) - size += 4; - - if (code != USE && code != CLOBBER && - op0 && GET_CODE (op0) == CONST_DOUBLE && GET_MODE (op0) == DFmode) - size += 4; - if (op1 && GET_CODE (op1) == CONST_DOUBLE && GET_MODE (op1) == DFmode) - size += 4; - if (op2 && GET_CODE (op2) == CONST_DOUBLE && GET_MODE (op2) == DFmode) - size += 4; - } - - /* Done with size computation! Chain this in. */ - fpop->size = size; - data_offset += size / UNITS_PER_WORD; - fpop->next_in_mem = 0; - fpop->next_same_hash = 0; - - if (last_fpop_in_mem) - last_fpop_in_mem->next_in_mem = fpop; - else - first_fpop = fpop; - last_fpop_in_mem = fpop; - - if (last_fpop) - last_fpop->next_same_hash = fpop; - else - fp_hash_table[hash] = fpop; - -win: - /* FPOP describes the operation to be performed. Return a string to branch - to it. */ - if (fpop->mem_offset < 32768 / UNITS_PER_WORD) - sprintf (outbuf, "cal r15,%d(r14)\n\tbalr%s r15,r15", - fpop->mem_offset * UNITS_PER_WORD, - dbr_sequence_length () ? "x" : ""); - else - sprintf (outbuf, "get r15,$L%dF%d\n\tbalr%s r15,r15", - subr_number, fpop->mem_offset * UNITS_PER_WORD, - dbr_sequence_length () ? "x" : ""); - return outbuf; -} - -/* If necessary, output a floating-point operation to save or restore all - floating-point registers. - - file is the file to write the operation to, CODE is USE for save, CLOBBER - for restore, and ADDR is the address of the same area, as RTL. */ - -static void -output_loadsave_fpregs (file, code, addr) - FILE *file; - enum rtx_code code; - rtx addr; -{ - register int i; - register int mask = 0; - - for (i = 2 + (TARGET_FP_REGS != 0); i <= 7; i++) - if (regs_ever_live[i + 17]) - mask |= 1 << (7 - i); - - if (mask) - fprintf (file, "\t%s\n", - output_fpop (code, GEN_INT (mask), gen_rtx_MEM (Pmode, addr), - 0, const0_rtx)); - -} - -/* Output any floating-point operations at the end of the routine. */ - -static void -output_fpops (file) - FILE *file; -{ - register struct fp_op *fpop; - register int size_so_far; - register int i; - rtx immed[3]; - - if (first_fpop == 0) - return; - - data_section (); - - ASM_OUTPUT_ALIGN (file, 2); - - for (fpop = first_fpop; fpop; fpop = fpop->next_in_mem) - { - if (fpop->mem_offset < 32768 / UNITS_PER_WORD) - fprintf (file, "# data area offset = %d\n", - fpop->mem_offset * UNITS_PER_WORD); - else - fprintf (file, "L%dF%d:\n", - subr_number, fpop->mem_offset * UNITS_PER_WORD); - - fprintf (file, "\tcas r0,r15,r0\n"); - fprintf (file, "\t.long FPGLUE\n"); - switch (fpop->opcode) - { - case USE: - fprintf (file, "\t.byte 0x1d\t# STOREM\n"); - break; - case CLOBBER: - fprintf (file, "\t.byte 0x0f\t# LOADM\n"); - break; - case ABS: - fprintf (file, "\t.byte 0x00\t# ABS\n"); - break; - case PLUS: - fprintf (file, "\t.byte 0x02\t# ADD\n"); - break; - case EQ: - fprintf (file, "\t.byte 0x07\t# CMP\n"); - break; - case GE: - fprintf (file, "\t.byte 0x08\t# CMPT\n"); - break; - case DIV: - fprintf (file, "\t.byte 0x0c\t# DIV\n"); - break; - case SET: - fprintf (file, "\t.byte 0x14\t# MOVE\n"); - break; - case MULT: - fprintf (file, "\t.byte 0x15\t# MUL\n"); - break; - case NEG: - fprintf (file, "\t.byte 0x16\t# NEG\n"); - break; - case SQRT: - fprintf (file, "\t.byte 0x1c\t# SQRT\n"); - break; - case MINUS: - fprintf (file, "\t.byte 0x1e\t# SUB\n"); - break; - default: - abort (); - } - - fprintf (file, "\t.byte %d\n", fpop->noperands); - fprintf (file, "\t.short 0x8001\n"); - - if ((fpop->ops[0] == 0 - || GET_CODE (fpop->ops[0]) != REG || REGNO(fpop->ops[0]) != 17) - && (fpop->ops[1] == 0 || GET_CODE (fpop->ops[1]) != REG - || REGNO(fpop->ops[1]) != 17) - && (fpop->ops[2] == 0 || GET_CODE (fpop->ops[2]) != REG - || REGNO(fpop->ops[2]) != 17)) - fprintf (file, "\t.byte %d, 0x80\n", fpop->size); - else - fprintf (file, "\t.byte %d, 0\n", fpop->size); - size_so_far = 12; - for (i = 0; i < fpop->noperands; i++) - { - register int type; - register int opbyte; - register const char *desc0; - char desc1[50]; - - immed[i] = 0; - switch (GET_MODE (fpop->ops[i])) - { - case SImode: - case VOIDmode: - desc0 = "int"; - type = 0; - break; - case SFmode: - desc0 = "float"; - type = 2; - break; - case DFmode: - desc0 = "double"; - type = 3; - break; - default: - abort (); - } - - switch (GET_CODE (fpop->ops[i])) - { - case REG: - strcpy(desc1, reg_names[REGNO (fpop->ops[i])]); - if (FP_REGNO_P (REGNO (fpop->ops[i]))) - { - type += 0x10; - opbyte = REGNO (fpop->ops[i]) - 17; - } - else - { - type += 0x00; - opbyte = REGNO (fpop->ops[i]); - if (type == 3) - opbyte = (opbyte << 4) + opbyte + 1; - } - break; - - case MEM: - type += 0x30; - if (GET_CODE (XEXP (fpop->ops[i], 0)) == PLUS) - { - immed[i] = XEXP (XEXP (fpop->ops[i], 0), 1); - opbyte = REGNO (XEXP (XEXP (fpop->ops[i], 0), 0)); - if (GET_CODE (immed[i]) == CONST_INT) - sprintf (desc1, "%d(%s)", INTVAL (immed[i]), - reg_names[opbyte]); - else - sprintf (desc1, "<memory> (%s)", reg_names[opbyte]); - } - else if (GET_CODE (XEXP (fpop->ops[i], 0)) == REG) - { - opbyte = REGNO (XEXP (fpop->ops[i], 0)); - immed[i] = const0_rtx; - sprintf (desc1, "(%s)", reg_names[opbyte]); - } - else - { - immed[i] = XEXP (fpop->ops[i], 0); - opbyte = 0; - sprintf(desc1, "<memory>"); - } - break; - - case CONST_INT: - case CONST_DOUBLE: - case CONST: - case SYMBOL_REF: - case LABEL_REF: - type += 0x20; - opbyte = 0; - immed[i] = fpop->ops[i]; - desc1[0] = '$'; - desc1[1] = '\0'; - break; - - default: - abort (); - } - - /* Save/restore is special. */ - if (i == 0 && (fpop->opcode == USE || fpop->opcode == CLOBBER)) - type = 0xff, opbyte = INTVAL (fpop->ops[0]), immed[i] = 0; - - fprintf (file, "\t.byte 0x%x,0x%x # (%s) %s\n", - type, opbyte, desc0, desc1); - - size_so_far += 2; - } - - /* If in the middle of a word, round. */ - if (size_so_far % UNITS_PER_WORD) - { - fprintf (file, "\t.space 2\n"); - size_so_far += 2; - } - - for (i = 0; i < fpop->noperands; i++) - if (immed[i]) - switch (GET_MODE (immed[i])) - { - case SImode: - case VOIDmode: - size_so_far += 4; - fprintf (file, "\t.long "); - output_addr_const (file, immed[i]); - fprintf (file, "\n"); - break; - - case DFmode: - size_so_far += 4; - case SFmode: - size_so_far += 4; - if (GET_CODE (immed[i]) == CONST_DOUBLE) - { - REAL_VALUE_TYPE r; - REAL_VALUE_FROM_CONST_DOUBLE (r, immed[i]); - assemble_real (r, GET_MODE (immed[i]), - GET_MODE_ALIGNMENT (GET_MODE (immed[i]))); - } - else - abort (); - break; - - default: - abort (); - } - - if (size_so_far != fpop->size) - { - if (TARGET_FULL_FP_BLOCKS) - fprintf (file, "\t.space %d\n", fpop->size - size_so_far); - else - abort (); - } - } - - /* Update for next subroutine. */ - subr_number++; - text_section (); -} - - /* Initialize floating-point operation table. */ - -static void -init_fpops() -{ - register int i; - - first_fpop = last_fpop_in_mem = 0; - for (i = 0; i < FP_HASH_SIZE; i++) - fp_hash_table[i] = 0; -} - -/* Return the offset value of an automatic variable (N_LSYM) having - the given offset. Basically, we correct by going from a frame pointer to - stack pointer value. -*/ - -int -romp_debugger_auto_correction(offset) - int offset; -{ - int fp_to_sp; - - /* We really want to go from STACK_POINTER_REGNUM to - FRAME_POINTER_REGNUM, but this isn't defined. So go the other - direction and negate. */ - INITIAL_ELIMINATION_OFFSET (FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM, - fp_to_sp); - - /* The offset value points somewhere between the frame pointer and - the stack pointer. What is up from the frame pointer is down from the - stack pointer. Therefore the negation in the offset value too. */ - - return -(offset+fp_to_sp+4); -} - -/* Return the offset value of an argument having - the given offset. Basically, we correct by going from an arg pointer to - stack pointer value. */ - -int -romp_debugger_arg_correction (offset) - int offset; -{ - int fp_to_argp; - - INITIAL_ELIMINATION_OFFSET (ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM, - fp_to_argp); - - /* Actually, something different happens if offset is from a floating-point - register argument, but we don't handle it here. */ - - return (offset - fp_to_argp); -} - -void -romp_initialize_trampoline (tramp, fnaddr, cxt) - rtx tramp, fnaddr, cxt; -{ - rtx addr, temp, val; - - temp = expand_simple_binop (SImode, PLUS, tramp, GEN_INT (4), - 0, 1, OPTAB_LIB_WIDEN); - emit_move_insn (gen_rtx_MEM (SImode, memory_address (SImode, tramp)), temp); - - val = force_reg (SImode, cxt); - addr = memory_address (HImode, plus_constant (tramp, 10)); - emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, val)); - temp = expand_shift (RSHIFT_EXPR, SImode, val, build_int_2 (16, 0), 0, 1); - addr = memory_address (HImode, plus_constant (tramp, 6)); - emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, temp)); - - val = force_reg (SImode, fnaddr); - addr = memory_address (HImode, plus_constant (tramp, 24)); - emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, val)); - temp = expand_shift (RSHIFT_EXPR, SImode, val, build_int_2 (16, 0), 0, 1); - addr = memory_address (HImode, plus_constant (tramp, 20)); - emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, temp)); -} - -/* On ROMP, all constants are in the data area. */ - -static void -romp_select_rtx_section (mode, x, align) - enum machine_mode mode ATTRIBUTE_UNUSED; - rtx x ATTRIBUTE_UNUSED; - unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED; -{ - data section (); -} - -/* For no good reason, we do the same as the other RT compilers and load - the addresses of data areas for a function from our data area. That means - that we need to mark such SYMBOL_REFs. We do so here. */ - -static void -romp_encode_section_info (decl, rtl, first) - tree decl; - rtx rtl; - int first ATTRIBUTE_UNUSED; -{ - if (TREE_CODE (TREE_TYPE (decl)) == FUNCTION_TYPE) - SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; -} - -static bool -romp_rtx_costs (x, code, outer_code, total) - rtx x; - int code, outer_code; - int *total; -{ - switch (x) - { - case CONST_INT: - if ((outer_code == IOR && exact_log2 (INTVAL (x)) >= 0) - || (outer_code == AND && exact_log2 (~INTVAL (x)) >= 0) - || ((outer_code == PLUS || outer_code == MINUS) - && (unsigned HOST_WIDE_INT) (INTVAL (x) + 15) < 31) - || (outer_code == SET && (unsigned HOST_WIDE_INT) INTVAL (x) < 16)) - *total = 0; - else if ((unsigned HOST_WIDE_INT) (INTVAL (x) + 0x8000) < 0x10000 - || (INTVAL (x) & 0xffff0000) == 0) - *total = 0; - else - *total = COSTS_N_INSNS (2); - return true; - - case CONST: - case LABEL_REF: - case SYMBOL_REF: - if (current_function_operand (x, Pmode)) - *total = 0; - else - *total = COSTS_N_INSNS (2); - return true; - - case CONST_DOUBLE: - if (x == CONST0_RTX (GET_MODE (x))) - *total = 2; - else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) - *total = COSTS_N_INSNS (5) - else - *total = COSTS_N_INSNS (4); - return true; - - case MEM: - *total = current_function_operand (x, Pmode) ? 0 : COSTS_N_INSNS (2); - return true; - - case MULT: - if (TARGET_IN_LINE_MUL && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) - *total = COSTS_N_INSNS (19); - else - *total = COSTS_N_INSNS (25); - return true; - - case DIV: - case UDIV: - case MOD: - case UMOD: - *total = COSTS_N_INSNS (45); - return true; - - default: - return false; - } -} - -/* For the ROMP, everything is cost 0 except for addresses involving - symbolic constants, which are cost 1. */ - -static int -romp_address_cost (x) - rtx x; -{ - return - ((GET_CODE (x) == SYMBOL_REF - && ! CONSTANT_POOL_ADDRESS_P (x)) - || GET_CODE (x) == LABEL_REF - || (GET_CODE (x) == CONST - && ! constant_pool_address_operand (x, Pmode)) - || (GET_CODE (x) == PLUS - && ((GET_CODE (XEXP (x, 1)) == SYMBOL_REF - && ! CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))) - || GET_CODE (XEXP (x, 1)) == LABEL_REF - || GET_CODE (XEXP (x, 1)) == CONST))); -} diff --git a/gcc/config/romp/romp.h b/gcc/config/romp/romp.h deleted file mode 100644 index cb7c9ad374b..00000000000 --- a/gcc/config/romp/romp.h +++ /dev/null @@ -1,1385 +0,0 @@ -/* Definitions of target machine for GNU compiler, for ROMP chip. - Copyright (C) 1989, 1991, 1993, 1995, 1996, 1998, 1999, 2000, 2001, 2002, - 2003 Free Software Foundation, Inc. - Contributed by Richard Kenner (kenner@nyu.edu) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - - -/* Names to predefine in the preprocessor for this target machine. */ - -#define CPP_PREDEFINES "-Dibm032 -Dunix -Asystem=unix -Asystem=bsd -Acpu=ibm032 -Amachine=ibm032" - -/* Print subsidiary information on the compiler version in use. */ -#define TARGET_VERSION ; - -/* Add -lfp_p when running with -p or -pg. */ -#define LIB_SPEC "%{pg:-lfp_p}%{p:-lfp_p} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" - -/* Run-time compilation parameters selecting different hardware subsets. */ - -/* Flag to generate all multiplies as an in-line sequence of multiply-step - insns instead of calling a library routine. */ -#define TARGET_IN_LINE_MUL (target_flags & 1) - -/* Flag to generate padded floating-point data blocks. Otherwise, we generate - them the minimum size. This trades off execution speed against size. */ -#define TARGET_FULL_FP_BLOCKS (target_flags & 2) - -/* Flag to pass and return floating point values in floating point registers. - Since this violates the linkage convention, we feel free to destroy fr2 - and fr3 on function calls. - fr1-fr3 are used to pass the arguments. */ -#define TARGET_FP_REGS (target_flags & 4) - -/* Flag to return structures of more than one word in memory. This is for - compatibility with the MetaWare HighC (hc) compiler. */ -#define TARGET_HC_STRUCT_RETURN (target_flags & 010) - -extern int target_flags; - -/* Macro to define tables used to set the flags. - This is a list in braces of pairs in braces, - each pair being { "NAME", VALUE } - where VALUE is the bits to set or minus the bits to clear. - An empty string NAME is used to identify the default VALUE. */ - -#define TARGET_SWITCHES \ - { {"in-line-mul", 1}, \ - {"call-lib-mul", -1}, \ - {"full-fp-blocks", 2}, \ - {"minimum-fp-blocks", -2}, \ - {"fp-arg-in-fpregs", 4}, \ - {"fp-arg-in-gregs", -4}, \ - {"hc-struct-return", 010}, \ - {"nohc-struct-return", - 010}, \ - { "", TARGET_DEFAULT}} - -#define TARGET_DEFAULT 3 - -/* target machine storage layout */ - -/* Define this if most significant bit is lowest numbered - in instructions that operate on numbered bit-fields. */ -/* That is true on ROMP. */ -#define BITS_BIG_ENDIAN 1 - -/* Define this if most significant byte of a word is the lowest numbered. */ -/* That is true on ROMP. */ -#define BYTES_BIG_ENDIAN 1 - -/* Define this if most significant word of a multiword number is lowest - numbered. - - For ROMP we can decide arbitrarily since there are no machine instructions - for them. Might as well be consistent with bits and bytes. */ -#define WORDS_BIG_ENDIAN 1 - -/* Width of a word, in units (bytes). */ -#define UNITS_PER_WORD 4 - -/* Allocation boundary (in *bits*) for storing arguments in argument list. */ -#define PARM_BOUNDARY 32 - -/* Boundary (in *bits*) on which stack pointer should be aligned. */ -#define STACK_BOUNDARY 32 - -/* Allocation boundary (in *bits*) for the code of a function. */ -#define FUNCTION_BOUNDARY 16 - -/* No data type wants to be aligned rounder than this. */ -#define BIGGEST_ALIGNMENT 32 - -/* Alignment of field after `int : 0' in a structure. */ -#define EMPTY_FIELD_BOUNDARY 32 - -/* Every structure's size must be a multiple of this. */ -#define STRUCTURE_SIZE_BOUNDARY 8 - -/* A bit-field declared as `int' forces `int' alignment for the struct. */ -#define PCC_BITFIELD_TYPE_MATTERS 1 - -/* Make strings word-aligned so strcpy from constants will be faster. */ -#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ - (TREE_CODE (EXP) == STRING_CST \ - && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) - -/* Make arrays of chars word-aligned for the same reasons. */ -#define DATA_ALIGNMENT(TYPE, ALIGN) \ - (TREE_CODE (TYPE) == ARRAY_TYPE \ - && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ - && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) - -/* Set this nonzero if move instructions will actually fail to work - when given unaligned data. */ -#define STRICT_ALIGNMENT 1 - -/* Standard register usage. */ - -/* Number of actual hardware registers. - The hardware registers are assigned numbers for the compiler - from 0 to just below FIRST_PSEUDO_REGISTER. - All registers that the compiler knows about must be given numbers, - even those that are not normally considered general registers. - - ROMP has 16 fullword registers and 8 floating point registers. - - In addition, the difference between the frame and argument pointers is - a function of the number of registers saved, so we need to have a register - to use for AP that will later be eliminated in favor of sp or fp. This is - a normal register, but it is fixed. */ - -#define FIRST_PSEUDO_REGISTER 25 - -/* 1 for registers that have pervasive standard uses - and are not available for the register allocator. - - On ROMP, r1 is used for the stack and r14 is used for a - data area pointer. - - HACK WARNING: On the RT, there is a bug in code generation for - the MC68881 when the first and third operands are the same floating-point - register. See the definition of the FINAL_PRESCAN_INSN macro for details. - Here we need to reserve fr0 for this purpose. */ -#define FIXED_REGISTERS \ - {0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, \ - 1, 0, 0, 0, 0, 0, 0, 0} - -/* 1 for registers not available across function calls. - These must include the FIXED_REGISTERS and also any - registers that can be used without being saved. - The latter must include the registers where values are returned - and the register where structure-value addresses are passed. - Aside from that, you can include as many other registers as you like. */ -#define CALL_USED_REGISTERS \ - {1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, \ - 1, 1, 0, 0, 0, 0, 0, 0} - -/* List the order in which to allocate registers. Each register must be - listed once, even those in FIXED_REGISTERS. - - We allocate in the following order: - fr0, fr1 (not saved) - fr2 ... fr6 - fr7 (more expensive for some FPA's) - r0 (not saved and won't conflict with parameter register) - r4, r3, r2 (not saved, highest used first to make less conflict) - r5 (not saved, but forces r6 to be saved if DI/DFmode) - r15, r14, r13, r12, r11, r10, r9, r8, r7, r6 (less to save) - r1, ap */ - -#define REG_ALLOC_ORDER \ - {17, 18, \ - 19, 20, 21, 22, 23, \ - 24, \ - 0, \ - 4, 3, 2, \ - 5, \ - 15, 14, 13, 12, 11, 10, \ - 9, 8, 7, 6, \ - 1, 16} - -/* True if register is floating-point. */ -#define FP_REGNO_P(N) ((N) >= 17) - -/* Return number of consecutive hard regs needed starting at reg REGNO - to hold something of mode MODE. - This is ordinarily the length in words of a value of mode MODE - but can be less for certain modes in special long registers. - - On ROMP, ordinary registers hold 32 bits worth; - a single floating point register is always enough for - anything that can be stored in them at all. */ -#define HARD_REGNO_NREGS(REGNO, MODE) \ - (FP_REGNO_P (REGNO) ? GET_MODE_NUNITS (MODE) \ - : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) - -/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. - On ROMP, the cpu registers can hold any mode but the float registers - can hold only floating point. */ -#define HARD_REGNO_MODE_OK(REGNO, MODE) \ - (! FP_REGNO_P (REGNO) || GET_MODE_CLASS (MODE) == MODE_FLOAT \ - || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) - -/* Value is 1 if it is a good idea to tie two pseudo registers - when one has mode MODE1 and one has mode MODE2. - If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, - for any hard reg, then this must be 0 for correct output. */ -#define MODES_TIEABLE_P(MODE1, MODE2) \ - ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ - || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ - == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ - || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) - -/* A C expression returning the cost of moving data from a register of class - CLASS1 to one of CLASS2. - - On the ROMP, access to floating-point registers is expensive (even between - two FP regs.) */ -#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ - (2 + 10 * ((CLASS1) == FP_REGS) + 10 * (CLASS2 == FP_REGS)) - -/* Specify the registers used for certain standard purposes. - The values of these macros are register numbers. */ - -/* ROMP pc isn't overloaded on a register that the compiler knows about. */ -/* #define PC_REGNUM */ - -/* Register to use for pushing function arguments. */ -#define STACK_POINTER_REGNUM 1 - -/* Base register for access to local variables of the function. */ -#define FRAME_POINTER_REGNUM 13 - -/* Value should be nonzero if functions must have frame pointers. - Zero means the frame pointer need not be set up (and parms - may be accessed via the stack pointer) in functions that seem suitable. - This is computed in `reload', in reload1.c. */ -#define FRAME_POINTER_REQUIRED 0 - -/* Base register for access to arguments of the function. */ -#define ARG_POINTER_REGNUM 16 - -/* Place to put static chain when calling a function that requires it. */ -#define STATIC_CHAIN \ - gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -36)) - -/* Place where static chain is found upon entry to routine. */ -#define STATIC_CHAIN_INCOMING \ - gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -20)) - -/* Place that structure value return address is placed. - - On the ROMP, it is passed as an extra parameter. */ -#define STRUCT_VALUE 0 - -/* Define the classes of registers for register constraints in the - machine description. Also define ranges of constants. - - One of the classes must always be named ALL_REGS and include all hard regs. - If there is more than one class, another class must be named NO_REGS - and contain no registers. - - The name GENERAL_REGS must be the name of a class (or an alias for - another name such as ALL_REGS). This is the class of registers - that is allowed by "g" or "r" in a register constraint. - Also, registers outside this class are allocated only when - instructions express preferences for them. - - The classes must be numbered in nondecreasing order; that is, - a larger-numbered class must never be contained completely - in a smaller-numbered class. - - For any two classes, it is very desirable that there be another - class that represents their union. */ - -/* The ROMP has two types of registers, general and floating-point. - - However, r0 is special in that it cannot be used as a base register. - So make a class for registers valid as base registers. - - For floating-point support, add classes that just consist of r0 and - r15, respectively. */ - -enum reg_class { NO_REGS, R0_REGS, R15_REGS, BASE_REGS, GENERAL_REGS, - FP_REGS, ALL_REGS, LIM_REG_CLASSES }; - -#define N_REG_CLASSES (int) LIM_REG_CLASSES - -/* Give names of register classes as strings for dump file. */ - -#define REG_CLASS_NAMES \ - {"NO_REGS", "R0_REGS", "R15_REGS", "BASE_REGS", "GENERAL_REGS", \ - "FP_REGS", "ALL_REGS" } - -/* Define which registers fit in which classes. - This is an initializer for a vector of HARD_REG_SET - of length N_REG_CLASSES. */ - -#define REG_CLASS_CONTENTS {{0}, {0x00001}, {0x08000}, {0x1fffe}, {0x1ffff}, \ - {0x1fe0000}, {0x1ffffff} } - -/* The same information, inverted: - Return the class number of the smallest class containing - reg number REGNO. This could be a conditional expression - or could index an array. */ - -#define REGNO_REG_CLASS(REGNO) \ - ((REGNO) == 0 ? GENERAL_REGS : FP_REGNO_P (REGNO) ? FP_REGS : BASE_REGS) - -/* The class value for index registers, and the one for base regs. */ -#define INDEX_REG_CLASS BASE_REGS -#define BASE_REG_CLASS BASE_REGS - -/* Get reg_class from a letter such as appears in the machine description. */ - -#define REG_CLASS_FROM_LETTER(C) \ - ((C) == 'f' ? FP_REGS \ - : (C) == 'b' ? BASE_REGS \ - : (C) == 'z' ? R0_REGS \ - : (C) == 't' ? R15_REGS \ - : NO_REGS) - -/* The letters I, J, K, L, M, N, and P in a register constraint string - can be used to stand for particular ranges of immediate operands. - This macro defines what the ranges are. - C is the letter, and VALUE is a constant value. - Return 1 if VALUE is in the range specified by C. - - `I' is constants less than 16 - `J' is negative constants greater than -16 - `K' is the range for a normal D insn. - `L' is a constant with only the low-order 16 bits set - `M' is a constant with only the high-order 16 bits set - `N' is a single-bit constant - `O' is a constant with either the high-order or low-order 16 bits all ones - `P' is the complement of a single-bit constant - */ - -#define CONST_OK_FOR_LETTER_P(VALUE, C) \ - ( (C) == 'I' ? (unsigned) (VALUE) < 0x10 \ - : (C) == 'J' ? (VALUE) < 0 && (VALUE) > -16 \ - : (C) == 'K' ? (unsigned) ((VALUE) + 0x8000) < 0x10000 \ - : (C) == 'L' ? ((VALUE) & 0xffff0000) == 0 \ - : (C) == 'M' ? ((VALUE) & 0xffff) == 0 \ - : (C) == 'N' ? exact_log2 (VALUE) >= 0 \ - : (C) == 'O' ? ((VALUE) & 0xffff) == 0xffff \ - || ((VALUE) & 0xffff0000) == 0xffff0000 \ - : (C) == 'P' ? exact_log2 (~ (VALUE)) >= 0 \ - : 0) - -/* Similar, but for floating constants, and defining letters G and H. - Here VALUE is the CONST_DOUBLE rtx itself. - No floating-point constants on ROMP. */ - -#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0 - -/* Optional extra constraints for this machine. - - For the ROMP, `Q' means that this is a memory operand but not a symbolic - memory operand. Note that an unassigned pseudo register is such a - memory operand. If register allocation has not been done, we reject - pseudos, since we assume (hope) that they will get hard registers. - - `R' means that this is a constant pool reference to the current function. - This is just r14 and so can be treated as a register. We bother with this - just in move insns as that is the only place it is likely to occur. - - `S' means that this is the address of a constant pool location. This is - equal to r14 plus a constant. We also only check for this in move insns. */ - -#define EXTRA_CONSTRAINT(OP, C) \ - ((C) == 'Q' ? \ - ((GET_CODE (OP) == REG \ - && REGNO (OP) >= FIRST_PSEUDO_REGISTER \ - && reg_renumber != 0 \ - && reg_renumber[REGNO (OP)] < 0) \ - || (GET_CODE (OP) == MEM \ - && ! symbolic_memory_operand (OP, VOIDmode))) \ - : (C) == 'R' ? current_function_operand (OP, VOIDmode) \ - : (C) == 'S' ? constant_pool_address_operand (OP, VOIDmode) \ - : 0) - -/* Given an rtx X being reloaded into a reg required to be - in class CLASS, return the class of reg to actually use. - In general this is just CLASS; but on some machines - in some cases it is preferable to use a more restrictive class. - - For the ROMP, if X is a memory reference that involves a symbol, - we must use a BASE_REGS register instead of GENERAL_REGS - to do the reload. The argument of MEM be either REG, PLUS, or SYMBOL_REF - to be valid, so we assume that this is the case. - - Also, if X is an integer class, ensure that floating-point registers - aren't used. */ - -#define PREFERRED_RELOAD_CLASS(X,CLASS) \ - ((CLASS) == FP_REGS && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ - ? GENERAL_REGS : \ - (CLASS) != GENERAL_REGS ? (CLASS) : \ - GET_CODE (X) != MEM ? GENERAL_REGS : \ - GET_CODE (XEXP (X, 0)) == SYMBOL_REF ? BASE_REGS : \ - GET_CODE (XEXP (X, 0)) == LABEL_REF ? BASE_REGS : \ - GET_CODE (XEXP (X, 0)) == CONST ? BASE_REGS : \ - GET_CODE (XEXP (X, 0)) == REG ? GENERAL_REGS : \ - GET_CODE (XEXP (X, 0)) != PLUS ? GENERAL_REGS : \ - GET_CODE (XEXP (XEXP (X, 0), 1)) == SYMBOL_REF ? BASE_REGS : \ - GET_CODE (XEXP (XEXP (X, 0), 1)) == LABEL_REF ? BASE_REGS : \ - GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST ? BASE_REGS : GENERAL_REGS) - -/* Return the register class of a scratch register needed to store into - OUT from a register of class CLASS in MODE. - - On the ROMP, we cannot store into a symbolic memory address from an - integer register; we need a BASE_REGS register as a scratch to do it. */ - -#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ - (GET_MODE_CLASS (MODE) == MODE_INT && symbolic_memory_operand (OUT, MODE) \ - ? BASE_REGS : NO_REGS) - -/* Return the maximum number of consecutive registers - needed to represent mode MODE in a register of class CLASS. - - On ROMP, this is the size of MODE in words, - except in the FP regs, where a single reg is always enough. */ -#define CLASS_MAX_NREGS(CLASS, MODE) \ - ((CLASS) == FP_REGS ? 1 \ - : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) - -/* Stack layout; function entry, exit and calling. */ - -/* Define this if pushing a word on the stack - makes the stack pointer a smaller address. */ -#define STACK_GROWS_DOWNWARD - -/* Define this if the nominal address of the stack frame - is at the high-address end of the local variables; - that is, each additional local variable allocated - goes at a more negative offset in the frame. */ -#define FRAME_GROWS_DOWNWARD - -/* Offset within stack frame to start allocating local variables at. - If FRAME_GROWS_DOWNWARD, this is the offset to the END of the - first local allocated. Otherwise, it is the offset to the BEGINNING - of the first local allocated. - On the ROMP, if we set the frame pointer to 15 words below the highest - address of the highest local variable, the first 16 words will be - addressable via D-short insns. */ -#define STARTING_FRAME_OFFSET 64 - -/* If we generate an insn to push BYTES bytes, - this says how many the stack pointer really advances by. - On ROMP, don't define this because there are no push insns. */ -/* #define PUSH_ROUNDING(BYTES) */ - -/* Offset of first parameter from the argument pointer register value. - On the ROMP, we define the argument pointer to the start of the argument - area. */ -#define FIRST_PARM_OFFSET(FNDECL) 0 - -/* Define this if stack space is still allocated for a parameter passed - in a register. The value is the number of bytes. */ -#define REG_PARM_STACK_SPACE(FNDECL) 16 - -/* This is the difference between the logical top of stack and the actual sp. - - For the ROMP, sp points past the words allocated for the first four outgoing - arguments (they are part of the callee's frame). */ -#define STACK_POINTER_OFFSET -16 - -/* Define this if the maximum size of all the outgoing args is to be - accumulated and pushed during the prologue. The amount can be - found in the variable current_function_outgoing_args_size. */ -#define ACCUMULATE_OUTGOING_ARGS 1 - -/* Value is the number of bytes of arguments automatically - popped when returning from a subroutine call. - FUNDECL is the declaration node of the function (as a tree), - FUNTYPE is the data type of the function (as a tree), - or for a library call it is an identifier node for the subroutine name. - SIZE is the number of bytes of arguments passed on the stack. */ - -#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 - -/* Define how to find the value returned by a function. - VALTYPE is the data type of the value (as a tree). - If the precise function being called is known, FUNC is its FUNCTION_DECL; - otherwise, FUNC is 0. - - On ROMP the value is found in r2, unless the machine specific option - fp-arg-in-fpregs is selected, in which case FP return values are in fr1 */ - -#define FUNCTION_VALUE(VALTYPE, FUNC) \ - gen_rtx_REG (TYPE_MODE (VALTYPE), \ - (TARGET_FP_REGS \ - && GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT) \ - ? 18 : 2) - -/* Define how to find the value returned by a library function - assuming the value has mode MODE. */ - -#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 2) - -/* The definition of this macro implies that there are cases where - a scalar value cannot be returned in registers. - - For the ROMP, if compatibility with HC is required, anything of - type DImode is returned in memory. */ - -#define RETURN_IN_MEMORY(type) \ - (TYPE_MODE (type) == BLKmode \ - || (TARGET_HC_STRUCT_RETURN && TYPE_MODE (type) == DImode)) - -/* 1 if N is a possible register number for a function value - as seen by the caller. - - On ROMP, r2 is the only register thus used unless fp values are to be - returned in fp regs, in which case fr1 is also used. */ - -#define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || ((N) == 18 && TARGET_FP_REGS)) - -/* 1 if N is a possible register number for function argument passing. - On ROMP, these are r2-r5 (and fr1-fr4 if fp regs are used). */ - -#define FUNCTION_ARG_REGNO_P(N) \ - (((N) <= 5 && (N) >= 2) || (TARGET_FP_REGS && (N) > 17 && (N) < 21)) - -/* Define a data type for recording info about an argument list - during the scan of that argument list. This data type should - hold all necessary information about the function itself - and about the args processed so far, enough to enable macros - such as FUNCTION_ARG to determine where the next arg should go. - - On the ROMP, this is a structure. The first word is the number of - words of (integer only if -mfp-arg-in-fpregs is specified) arguments - scanned so far (including the invisible argument, if any, which holds - the structure-value-address). The second word hold the corresponding - value for floating-point arguments, except that both single and double - count as one register. */ - -struct rt_cargs {int gregs, fregs; }; -#define CUMULATIVE_ARGS struct rt_cargs - -#define USE_FP_REG(MODE,CUM) \ - (TARGET_FP_REGS && GET_MODE_CLASS (MODE) == MODE_FLOAT \ - && (CUM).fregs < 3) - -/* Define intermediate macro to compute the size (in registers) of an argument - for the ROMP. */ - -#define ROMP_ARG_SIZE(MODE, TYPE, NAMED) \ -(! (NAMED) ? 0 \ - : (MODE) != BLKmode \ - ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ - : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) - -/* Initialize a variable CUM of type CUMULATIVE_ARGS - for a call to a function whose data type is FNTYPE. - For a library call, FNTYPE is 0. - - On ROMP, the offset normally starts at 0, but starts at 4 bytes - when the function gets a structure-value-address as an - invisible first argument. */ - -#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ - (CUM).gregs = 0, \ - (CUM).fregs = 0 - -/* Update the data in CUM to advance over an argument - of mode MODE and data type TYPE. - (TYPE is null for libcalls where that information may not be available.) */ - -#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ -{ if (NAMED) \ - { \ - if (USE_FP_REG(MODE, CUM)) \ - (CUM).fregs++; \ - else \ - (CUM).gregs += ROMP_ARG_SIZE (MODE, TYPE, NAMED); \ - } \ -} - -/* Determine where to put an argument to a function. - Value is zero to push the argument on the stack, - or a hard register in which to store the argument. - - MODE is the argument's machine mode. - TYPE is the data type of the argument (as a tree). - This is null for libcalls where that information may - not be available. - CUM is a variable of type CUMULATIVE_ARGS which gives info about - the preceding args and about the function being called. - NAMED is nonzero if this argument is a named parameter - (otherwise it is an extra parameter matching an ellipsis). - - On ROMP the first four words of args are normally in registers - and the rest are pushed. */ - -#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ - (! (NAMED) ? 0 \ - : ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST) ? 0 \ - : USE_FP_REG(MODE,CUM) ? gen_rtx_REG ((MODE), (CUM).fregs + 17) \ - : (CUM).gregs < 4 ? gen_rtx_REG ((MODE), 2 + (CUM).gregs) : 0) - -/* For an arg passed partly in registers and partly in memory, - this is the number of registers used. - For args passed entirely in registers or entirely in memory, zero. */ - -#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ - (! (NAMED) ? 0 \ - : USE_FP_REG(MODE,CUM) ? 0 \ - : (((CUM).gregs < 4 \ - && 4 < ((CUM).gregs + ROMP_ARG_SIZE (MODE, TYPE, NAMED))) \ - ? 4 - (CUM).gregs : 0)) - -/* Perform any needed actions needed for a function that is receiving a - variable number of arguments. - - CUM is as above. - - MODE and TYPE are the mode and type of the current parameter. - - PRETEND_SIZE is a variable that should be set to the amount of stack - that must be pushed by the prolog to pretend that our caller pushed - it. - - Normally, this macro will push all remaining incoming registers on the - stack and set PRETEND_SIZE to the length of the registers pushed. */ - -#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ -{ if (TARGET_FP_REGS) \ - error ("can't have varargs with -mfp-arg-in-fp-regs"); \ - else if ((CUM).gregs < 4) \ - { \ - int first_reg_offset = (CUM).gregs; \ - \ - if (MUST_PASS_IN_STACK (MODE, TYPE)) \ - first_reg_offset += ROMP_ARG_SIZE (TYPE_MODE (TYPE), TYPE, 1); \ - \ - if (first_reg_offset > 4) \ - first_reg_offset = 4; \ - \ - if (! NO_RTL && first_reg_offset != 4) \ - move_block_from_reg \ - (2 + first_reg_offset, \ - gen_rtx_MEM (BLKmode, \ - plus_constant (virtual_incoming_args_rtx, \ - first_reg_offset * 4)), \ - 4 - first_reg_offset); \ - PRETEND_SIZE = (4 - first_reg_offset) * UNITS_PER_WORD; \ - } \ -} - -/* This macro produces the initial definition of a function name. - On the ROMP, we need to place an extra '.' in the function name. */ - -#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ -{ if (TREE_PUBLIC(DECL)) \ - fprintf (FILE, "\t.globl _.%s\n", NAME); \ - fprintf (FILE, "_.%s:\n", NAME); \ -} - -/* This macro is used to output the start of the data area. - - On the ROMP, the _name is a pointer to the data area. At that - location is the address of _.name, which is really the name of - the function. We need to set all this up here. - - The global declaration of the data area, if needed, is done in - `assemble_function', where it thinks it is globalizing the function - itself. */ - -#define ASM_OUTPUT_POOL_PROLOGUE(FILE, NAME, DECL, SIZE) \ -{ extern int data_offset; \ - data_section (); \ - fprintf (FILE, "\t.align 2\n"); \ - ASM_OUTPUT_LABEL (FILE, NAME); \ - fprintf (FILE, "\t.long _.%s, 0, ", NAME); \ - if (current_function_calls_alloca) \ - fprintf (FILE, "0x%x\n", \ - 0xf6900000 + current_function_outgoing_args_size); \ - else \ - fprintf (FILE, "0\n"); \ - data_offset = ((SIZE) + 12 + 3) / 4; \ -} - -/* Output assembler code to FILE to increment profiler label # LABELNO - for profiling a function entry. */ - -#define FUNCTION_PROFILER(FILE, LABELNO) \ - fprintf(FILE, "\tcas r0,r15,r0\n\tbali r15,mcount\n"); - -/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, - the stack pointer does not matter. The value is tested only in - functions that have frame pointers. - No definition is equivalent to always zero. */ -/* #define EXIT_IGNORE_STACK 1 */ - -/* Output assembler code for a block containing the constant parts - of a trampoline, leaving space for the variable parts. - - The trampoline should set the static chain pointer to value placed - into the trampoline and should branch to the specified routine. - - On the ROMP, we have a problem. There are no free registers to use - to construct the static chain and function addresses. Hence we use - the following kludge: r15 (the return address) is first saved in mq. - Then we use r15 to form the function address. We then branch to the - function and restore r15 in the delay slot. This makes it appear that - the function was called directly from the caller. - - (Note that the function address built is actually that of the data block. - This is passed in r0 and the actual routine address is loaded into r15.) - - In addition, note that the address of the "called function", in this case - the trampoline, is actually the address of the data area. So we need to - make a fake data area that will contain the address of the trampoline. - Note that this must be defined as two half-words, since the trampoline - template (as opposed to the trampoline on the stack) is only half-word - aligned. */ - -#define TRAMPOLINE_TEMPLATE(FILE) \ -{ \ - fprintf (FILE, "\t.short 0,0\n"); \ - fprintf (FILE, "\tcau r0,0(r0)\n"); \ - fprintf (FILE, "\toil r0,r0,0\n"); \ - fprintf (FILE, "\tmts r10,r15\n"); \ - fprintf (FILE, "\tst r0,-36(r1)\n"); \ - fprintf (FILE, "\tcau r15,0(r0)\n"); \ - fprintf (FILE, "\toil r15,r15,0\n"); \ - fprintf (FILE, "\tcas r0,r15,r0\n"); \ - fprintf (FILE, "\tls r15,0(r15)\n"); \ - fprintf (FILE, "\tbrx r15\n"); \ - fprintf (FILE, "\tmfs r10,r15\n"); \ -} - -/* Length in units of the trampoline for entering a nested function. */ - -#define TRAMPOLINE_SIZE 36 - -/* Emit RTL insns to initialize the variable parts of a trampoline. - FNADDR is an RTX for the address of the function's pure code. - CXT is an RTX for the static chain value for the function. - - On the RT, the static chain and function addresses are written in - two 16-bit sections. - - We also need to write the address of the first instruction in - the trampoline into the first word of the trampoline to simulate a - data area. */ - -#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ - romp_initialize_trampoline (ADDR, FNADDR, CXT) - -/* Definitions for register eliminations. - - We have two registers that can be eliminated on the ROMP. First, the - frame pointer register can often be eliminated in favor of the stack - pointer register. Secondly, the argument pointer register can always be - eliminated; it is replaced with either the stack or frame pointer. - - In addition, we use the elimination mechanism to see if r14 is needed. - Initially we assume that it isn't. If it is, we spill it. This is done - by making it an eliminable register. It doesn't matter what we replace - it with, since it will never occur in the rtl at this point. */ - -/* This is an array of structures. Each structure initializes one pair - of eliminable registers. The "from" register number is given first, - followed by "to". Eliminations of the same "from" register are listed - in order of preference. */ -#define ELIMINABLE_REGS \ -{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ - { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ - { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ - { 14, 0}} - -/* Given FROM and TO register numbers, say whether this elimination is allowed. - Frame pointer elimination is automatically handled. - - For the ROMP, if frame pointer elimination is being done, we would like to - convert ap into fp, not sp. - - We need r14 if various conditions (tested in romp_using_r14) are true. - - All other eliminations are valid. */ -#define CAN_ELIMINATE(FROM, TO) \ - ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ - ? ! frame_pointer_needed \ - : (FROM) == 14 ? ! romp_using_r14 () \ - : 1) - -/* Define the offset between two registers, one to be eliminated, and the other - its replacement, at the start of a routine. */ -#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -{ if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ - { \ - if (romp_pushes_stack ()) \ - (OFFSET) = ((get_frame_size () - 64) \ - + current_function_outgoing_args_size); \ - else \ - (OFFSET) = - (romp_sa_size () + 64); \ - } \ - else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ - (OFFSET) = romp_sa_size () - 16 + 64; \ - else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ - { \ - if (romp_pushes_stack ()) \ - (OFFSET) = (get_frame_size () + (romp_sa_size () - 16) \ - + current_function_outgoing_args_size); \ - else \ - (OFFSET) = -16; \ - } \ - else if ((FROM) == 14) \ - (OFFSET) = 0; \ - else \ - abort (); \ -} - -/* Addressing modes, and classification of registers for them. */ - -/* Macros to check register numbers against specific register classes. */ - -/* These assume that REGNO is a hard or pseudo reg number. - They give nonzero only if REGNO is a hard reg of the suitable class - or a pseudo reg currently allocated to a suitable hard reg. - Since they use reg_renumber, they are safe only once reg_renumber - has been allocated, which happens in local-alloc.c. */ - -#define REGNO_OK_FOR_INDEX_P(REGNO) 0 -#define REGNO_OK_FOR_BASE_P(REGNO) \ -((REGNO) < FIRST_PSEUDO_REGISTER \ - ? (REGNO) < 16 && (REGNO) != 0 && (REGNO) != 16 \ - : (reg_renumber[REGNO] < 16 && reg_renumber[REGNO] >= 0 \ - && reg_renumber[REGNO] != 16)) - -/* Maximum number of registers that can appear in a valid memory address. */ - -#define MAX_REGS_PER_ADDRESS 1 - -/* Recognize any constant value that is a valid address. */ - -#define CONSTANT_ADDRESS_P(X) \ - (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ - || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ - || GET_CODE (X) == HIGH) - -/* Nonzero if the constant value X is a legitimate general operand. - It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. - - On the ROMP, there is a bit of a hack here. Basically, we wish to - only issue instructions that are not `as' macros. However, in the - case of `get', `load', and `store', if the operand is a relocatable - symbol (possibly +/- an integer), there is no way to express the - resulting split-relocation except with the macro. Therefore, allow - either a constant valid in a normal (sign-extended) D-format insn or - a relocatable expression. - - Also, for DFmode and DImode, we must ensure that both words are - addressable. - - We define two macros: The first is given an offset (0 or 4) and indicates - that the operand is a CONST_INT that is valid for that offset. The second - indicates a valid non-CONST_INT constant. */ - -#define LEGITIMATE_ADDRESS_INTEGER_P(X,OFFSET) \ - (GET_CODE (X) == CONST_INT \ - && (unsigned) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000) - -#define LEGITIMATE_ADDRESS_CONSTANT_P(X) \ - (GET_CODE (X) == SYMBOL_REF \ - || GET_CODE (X) == LABEL_REF \ - || (GET_CODE (X) == CONST \ - && (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \ - || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \ - && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT)) - -/* Include all constant integers and constant double, but exclude - SYMBOL_REFs that are to be obtained from the data area (see below). */ -#define LEGITIMATE_CONSTANT_P(X) \ - ((LEGITIMATE_ADDRESS_CONSTANT_P (X) \ - || GET_CODE (X) == CONST_INT \ - || GET_CODE (X) == CONST_DOUBLE) \ - && ! (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X))) - -/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx - and check its validity for a certain class. - We have two alternate definitions for each of them. - The usual definition accepts all pseudo regs; the other rejects - them unless they have been allocated suitable hard regs. - The symbol REG_OK_STRICT causes the latter definition to be used. - - Most source files want to accept pseudo regs in the hope that - they will get allocated to the class that the insn wants them to be in. - Source files for reload pass need to be strict. - After reload, it makes no difference, since pseudo regs have - been eliminated by then. */ - -#ifndef REG_OK_STRICT - -/* Nonzero if X is a hard reg that can be used as an index - or if it is a pseudo reg. */ -#define REG_OK_FOR_INDEX_P(X) 0 -/* Nonzero if X is a hard reg that can be used as a base reg - or if it is a pseudo reg. */ -#define REG_OK_FOR_BASE_P(X) \ - (REGNO (X) != 0 && (REGNO (X) < 17 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) - -#else - -/* Nonzero if X is a hard reg that can be used as an index. */ -#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) -/* Nonzero if X is a hard reg that can be used as a base reg. */ -#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) - -#endif - -/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression - that is a valid memory address for an instruction. - The MODE argument is the machine mode for the MEM expression - that wants to use this address. - - On the ROMP, a legitimate address is either a legitimate constant, - a register plus a legitimate constant, or a register. See the - discussion at the LEGITIMATE_ADDRESS_CONSTANT_P macro. */ -#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -{ if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ - goto ADDR; \ - if (GET_CODE (X) != CONST_INT && LEGITIMATE_ADDRESS_CONSTANT_P (X)) \ - goto ADDR; \ - if (GET_CODE (X) == PLUS \ - && GET_CODE (XEXP (X, 0)) == REG \ - && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ - && LEGITIMATE_ADDRESS_CONSTANT_P (XEXP (X, 1))) \ - goto ADDR; \ - if (GET_CODE (X) == PLUS \ - && GET_CODE (XEXP (X, 0)) == REG \ - && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ - && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \ - && (((MODE) != DFmode && (MODE) != DImode) \ - || (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4)))) \ - goto ADDR; \ -} - -/* Try machine-dependent ways of modifying an illegitimate address - to be legitimate. If we find one, return the new, valid address. - This macro is used in only one place: `memory_address' in explow.c. - - OLDX is the address as it was before break_out_memory_refs was called. - In some cases it is useful to look at this to decide what needs to be done. - - MODE and WIN are passed so that this macro can use - GO_IF_LEGITIMATE_ADDRESS. - - It is always safe for this macro to do nothing. It exists to recognize - opportunities to optimize the output. - - On ROMP, check for the sum of a register with a constant - integer that is out of range. If so, generate code to add the - constant with the low-order 16 bits masked to the register and force - this result into another register (this can be done with `cau'). - Then generate an address of REG+(CONST&0xffff), allowing for the - possibility of bit 16 being a one. - - If the register is not OK for a base register, abort. */ - -#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ -{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ - && GET_CODE (XEXP (X, 1)) == CONST_INT \ - && (unsigned) (INTVAL (XEXP (X, 1)) + 0x8000) >= 0x10000) \ - { int high_int, low_int; \ - if (! REG_OK_FOR_BASE_P (XEXP (X, 0))) \ - abort (); \ - high_int = INTVAL (XEXP (X, 1)) >> 16; \ - low_int = INTVAL (XEXP (X, 1)) & 0xffff; \ - if (low_int & 0x8000) \ - high_int += 1, low_int |= 0xffff0000; \ - (X) = gen_rtx_PLUS (SImode, \ - force_operand (plus_constant (XEXP (X, 0), \ - high_int << 16), 0), \ - GEN_INT (low_int)); \ - } \ -} - -/* Go to LABEL if ADDR (a legitimate address expression) - has an effect that depends on the machine mode it is used for. - - On the ROMP this is true only if the address is valid with a zero offset - but not with an offset of four (this means it cannot be used as an - address for DImode or DFmode). Since we know it is valid, we just check - for an address that is not valid with an offset of four. */ - -#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ -{ if (GET_CODE (ADDR) == PLUS \ - && ! LEGITIMATE_ADDRESS_CONSTANT_P (XEXP (ADDR, 1)) \ - && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 4)) \ - goto LABEL; \ -} - -/* Define this if some processing needs to be done immediately before - emitting code for an insn. - - This is used on the ROMP, to compensate for a bug in the floating-point - code. When a floating-point operation is done with the first and third - operands both the same floating-point register, it will generate bad code - for the MC68881. So we must detect this. If it occurs, we patch the - first operand to be fr0 and insert a move insn to move it to the desired - destination. */ -#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \ - { rtx op0, op1, op2, operation, tem; \ - if (NOPERANDS >= 3 && get_attr_type (INSN) == TYPE_FP) \ - { \ - op0 = OPERANDS[0]; \ - operation = OPERANDS[1]; \ - if (float_conversion (operation, VOIDmode)) \ - operation = XEXP (operation, 0); \ - if (float_binary (operation, VOIDmode)) \ - { \ - op1 = XEXP (operation, 0), op2 = XEXP (operation, 1); \ - if (float_conversion (op1, VOIDmode)) \ - op1 = XEXP (op1, 0); \ - if (float_conversion (op2, VOIDmode)) \ - op2 = XEXP (op2, 0); \ - if (rtx_equal_p (op0, op2) \ - && (GET_CODE (operation) == PLUS \ - || GET_CODE (operation) == MULT)) \ - tem = op1, op1 = op2, op2 = tem; \ - if (GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0)) \ - && GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2)) \ - && REGNO (op0) == REGNO (op2)) \ - { \ - tem = gen_rtx_REG (GET_MODE (op0), 17); \ - emit_insn_after (gen_move_insn (op0, tem), INSN); \ - SET_DEST (XVECEXP (PATTERN (INSN), 0, 0)) = tem; \ - OPERANDS[0] = tem; \ - } \ - } \ - } \ - } - -/* Specify the machine mode that this machine uses - for the index in the tablejump instruction. */ -#define CASE_VECTOR_MODE SImode - -/* Define as C expression which evaluates to nonzero if the tablejump - instruction expects the table to contain offsets from the address of the - table. - Do not define this if the table should contain absolute addresses. */ -/* #define CASE_VECTOR_PC_RELATIVE 1 */ - -/* Define this as 1 if `char' should by default be signed; else as 0. */ -#define DEFAULT_SIGNED_CHAR 0 - -/* This flag, if defined, says the same insns that convert to a signed fixnum - also convert validly to an unsigned one. - - We actually lie a bit here as overflow conditions are different. But - they aren't being checked anyway. */ - -#define FIXUNS_TRUNC_LIKE_FIX_TRUNC - -/* Max number of bytes we can move from memory to memory - in one reasonably fast instruction. */ -#define MOVE_MAX 4 - -/* Nonzero if access to memory by bytes is no faster than for words. - Also nonzero if doing byte operations (specifically shifts) in registers - is undesirable. */ -#define SLOW_BYTE_ACCESS 1 - -/* Define if operations between registers always perform the operation - on the full register even if a narrower mode is specified. */ -#define WORD_REGISTER_OPERATIONS - -/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD - will either zero-extend or sign-extend. The value of this macro should - be the code that says which one of the two operations is implicitly - done, NIL if none. */ -#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND - -/* This is BSD, so it wants DBX format. */ -#define DBX_DEBUGGING_INFO 1 - -/* Define the letter code used in a stabs entry for parameters passed - with the register attribute. - - GCC's default value, 'P', is used by dbx to refers to an external - procedure. The section 5 manual page for dbx implies that 'R' would be the - right letter, but dbx 1.5 has a bug in it that precludes its use. - Probably that is why neither hc or pcc use this. pcc puts in two - stabs entries: one for the parameter location and one for the register - location. The letter `r' (register) - would be okay, but it loses parameter attribute of the stabs entry. */ -#define DBX_REGPARM_STABS_LETTER 'R' - -/* A C expression for the integer offset value of an automatic variable - (N_LSYM) having address X (an RTX). This gets used in .stabs entries - for the local variables. Compare with the default definition. */ -#define DEBUGGER_AUTO_OFFSET(X) \ - (GET_CODE (X) == PLUS \ - ? romp_debugger_auto_correction (INTVAL (XEXP (X, 1)) ) \ - : 0 ) - -/* A C expression for the integer offset value of an argument (N_PSYM) - having address X (an RTX). The nominal offset is OFFSET. */ -#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ - romp_debugger_arg_correction (OFFSET); - -/* We don't have GAS for the RT yet, so don't write out special - .stabs in cc1plus. */ - -#define FASCIST_ASSEMBLER - -/* Do not break .stabs pseudos into continuations. */ -#define DBX_CONTIN_LENGTH 0 - -/* Don't try to use the `x' type-cross-reference character in DBX data. - Also has the consequence of putting each struct, union or enum - into a separate .stabs, containing only cross-refs to the others. */ -#define DBX_NO_XREFS - -/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits - is done just by pretending it is already truncated. */ -#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 - -/* Specify the machine mode that pointers have. - After generation of rtl, the compiler makes no further distinction - between pointers and any other objects of this machine mode. */ -#define Pmode SImode - -/* Mode of a function address in a call instruction (for indexing purposes). - - Doesn't matter on ROMP. */ -#define FUNCTION_MODE SImode - -/* Define this if addresses of constant functions - shouldn't be put through pseudo regs where they can be cse'd. - Desirable on machines where ordinary constants are expensive - but a CALL with constant address is cheap. */ -#define NO_FUNCTION_CSE - -/* Define this if shift instructions ignore all but the low-order - few bits. - - This is not true on the RT since it uses the low-order 6, not 5, bits. - At some point, this should be extended to see how to express that. */ - -/* #define SHIFT_COUNT_TRUNCATED */ - -/* Adjust the length of an INSN. LENGTH is the currently-computed length and - should be adjusted to reflect any required changes. This macro is used when - there is some systematic length adjustment required that would be difficult - to express in the length attribute. - - On the ROMP, there are two adjustments: First, a 2-byte insn in the delay - slot of a CALL (including floating-point operations) actually takes four - bytes. Second, we have to make the worst-case alignment assumption for - address vectors. */ - -#define ADJUST_INSN_LENGTH(X,LENGTH) \ - if (GET_CODE (X) == INSN && GET_CODE (PATTERN (X)) == SEQUENCE \ - && GET_CODE (XVECEXP (PATTERN (X), 0, 0)) != JUMP_INSN \ - && get_attr_length (XVECEXP (PATTERN (X), 0, 1)) == 2) \ - (LENGTH) += 2; \ - else if (GET_CODE (X) == JUMP_INSN && GET_CODE (PATTERN (X)) == ADDR_VEC) \ - (LENGTH) += 2; - -/* Tell final.c how to eliminate redundant test instructions. */ - -/* Here we define machine-dependent flags and fields in cc_status - (see `conditions.h'). */ - -/* Set if condition code (really not-Z) is stored in `test bit'. */ -#define CC_IN_TB 01000 - -/* Set if condition code is set by an unsigned compare. */ -#define CC_UNSIGNED 02000 - -/* Store in cc_status the expressions - that the condition codes will describe - after execution of an instruction whose pattern is EXP. - Do not alter them if the instruction would not alter the cc's. */ - -#define NOTICE_UPDATE_CC(BODY,INSN) \ - update_cc (BODY, INSN) - -/* Control the assembler format that we output. */ - -/* Output at beginning of assembler file. */ - -#define ASM_FILE_START(FILE) \ -{ const char *p; \ - \ - fprintf (FILE, "\t.globl .oVncs\n\t.set .oVncs,0\n") ; \ - fprintf (FILE, "\t.globl .oVgcc"); \ - for (p = version_string; *p != ' ' && *p != 0; p++) \ - fprintf (FILE, "%c", *p); \ - fprintf (FILE, "\n\t.set .oVgcc"); \ - for (p = version_string; *p != ' ' && *p != 0; p++) \ - fprintf (FILE, "%c", *p); \ - fprintf (FILE, ",0\n"); \ -} - -/* Output to assembler file text saying following lines - may contain character constants, extra white space, comments, etc. */ - -#define ASM_APP_ON "" - -/* Output to assembler file text saying following lines - no longer contain unusual constructs. */ - -#define ASM_APP_OFF "" - -/* Output before instructions and read-only data. */ - -#define TEXT_SECTION_ASM_OP "\t.text" - -/* Output before writable data. */ - -#define DATA_SECTION_ASM_OP "\t.data" - -/* How to refer to registers in assembler output. - This sequence is indexed by compiler's hard-register-number (see above). */ - -#define REGISTER_NAMES \ -{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ - "r10", "r11", "r12", "r13", "r14", "r15", "ap", \ - "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7" } - -/* Globalizing directive for a label. */ -#define GLOBAL_ASM_OP "\t.globl " - -/* The prefix to add to user-visible assembler symbols. */ - -#define USER_LABEL_PREFIX "_" - -/* This is how to output a label for a jump table. Arguments are the same as - for (*targetm.asm_out.internal_label), except the insn for the jump table is - passed. */ - -#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ -{ ASM_OUTPUT_ALIGN (FILE, 2); (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); } - -/* This is how to store into the string LABEL - the symbol_ref name of an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. - This is suitable for output with `assemble_name'. */ - -#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ - sprintf (LABEL, "*%s%d", PREFIX, NUM) - -/* This is how to output code to push a register on the stack. - It need not be very fast code. */ - -#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ - fprintf (FILE, "\tsis r1,4\n\tsts %s,0(r1)\n", reg_names[REGNO]) - -/* This is how to output an insn to pop a register from the stack. - It need not be very fast code. */ - -#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ - fprintf (FILE, "\tls r1,0(r1)\n\tais r1,4\n", reg_names[REGNO]) - -/* This is how to output an element of a case-vector that is absolute. */ - -#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ - fprintf (FILE, "\t.long L%d\n", VALUE) - -/* This is how to output an element of a case-vector that is relative. - Don't define this if it is not supported. */ - -/* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */ - -/* This is how to output an assembler line - that says to advance the location counter - to a multiple of 2**LOG bytes. */ - -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ - if ((LOG) != 0) \ - fprintf (FILE, "\t.align %d\n", (LOG)) - -#define ASM_OUTPUT_SKIP(FILE,SIZE) \ - fprintf (FILE, "\t.space %d\n", (int)(SIZE)) - -/* This says how to output an assembler line - to define a global common symbol. */ - -#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -( fputs (".comm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%d\n", (int)(SIZE))) - -/* This says how to output an assembler line - to define a local common symbol. */ - -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ -( fputs (".lcomm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%d\n", (int)(SIZE))) - -/* Print operand X (an rtx) in assembler syntax to file FILE. - CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. - For `%' followed by punctuation, CODE is the punctuation and X is null. */ - -#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) - -/* Define which CODE values are valid. */ - -#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ - ((CODE) == '.' || (CODE) == '#') - -/* Print a memory address as an operand to reference that memory location. */ - -#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -{ register rtx addr = ADDR; \ - register rtx base = 0, offset = addr; \ - if (GET_CODE (addr) == REG) \ - base = addr, offset = const0_rtx; \ - else if (GET_CODE (addr) == PLUS \ - && GET_CODE (XEXP (addr, 0)) == REG) \ - base = XEXP (addr, 0), offset = XEXP (addr, 1); \ - else if (GET_CODE (addr) == SYMBOL_REF \ - && CONSTANT_POOL_ADDRESS_P (addr)) \ - { \ - offset = GEN_INT (get_pool_offset (addr) + 12); \ - base = gen_rtx_REG (SImode, 14); \ - } \ - else if (GET_CODE (addr) == CONST \ - && GET_CODE (XEXP (addr, 0)) == PLUS \ - && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT \ - && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF \ - && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addr, 0), 0))) \ - { \ - offset = plus_constant (XEXP (XEXP (addr, 0), 1), \ - (get_pool_offset (XEXP (XEXP (addr, 0), 0)) \ - + 12)); \ - base = gen_rtx_REG (SImode, 14); \ - } \ - output_addr_const (FILE, offset); \ - if (base) \ - fprintf (FILE, "(%s)", reg_names [REGNO (base)]); \ -} - -/* Define the codes that are matched by predicates in aux-output.c. */ - -#define PREDICATE_CODES \ - {"zero_memory_operand", {SUBREG, MEM}}, \ - {"short_memory_operand", {SUBREG, MEM}}, \ - {"symbolic_memory_operand", {SUBREG, MEM}}, \ - {"current_function_operand", {MEM}}, \ - {"constant_pool_address_operand", {SUBREG, CONST}}, \ - {"romp_symbolic_operand", {LABEL_REF, SYMBOL_REF, CONST}}, \ - {"constant_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST, CONST_INT}}, \ - {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ - {"reg_or_any_cint_operand", {SUBREG, REG, CONST_INT}}, \ - {"short_cint_operand", {CONST_INT}}, \ - {"reg_or_D_operand", {SUBREG, REG, CONST_INT}}, \ - {"reg_or_add_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, \ - PLUS, CONST, CONST_INT}}, \ - {"reg_or_and_operand", {SUBREG, REG, CONST_INT}}, \ - {"reg_or_mem_operand", {SUBREG, REG, MEM}}, \ - {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \ - {"romp_operand", {SUBREG, MEM, REG, CONST_INT, CONST, LABEL_REF, \ - SYMBOL_REF, CONST_DOUBLE}}, \ - {"reg_0_operand", {REG}}, \ - {"reg_15_operand", {REG}}, \ - {"float_binary", {PLUS, MINUS, MULT, DIV}}, \ - {"float_unary", {NEG, ABS}}, \ - {"float_conversion", {FLOAT_TRUNCATE, FLOAT_EXTEND, FLOAT, FIX}}, - diff --git a/gcc/config/romp/romp.md b/gcc/config/romp/romp.md deleted file mode 100644 index 07da5f0748e..00000000000 --- a/gcc/config/romp/romp.md +++ /dev/null @@ -1,2766 +0,0 @@ -;;- Machine description for ROMP chip for GNU C compiler -;; Copyright (C) 1988, 1991, 1993, 1994, 1995, 1998, 1999, 2000 -;; Free Software Foundation, Inc. -;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) - -;; This file is part of GNU CC. - -;; GNU CC is free software; you can redistribute it and/or modify -;; it under the terms of the GNU General Public License as published by -;; the Free Software Foundation; either version 2, or (at your option) -;; any later version. - -;; GNU CC is distributed in the hope that it will be useful, -;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;; GNU General Public License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GNU CC; see the file COPYING. If not, write to -;; the Free Software Foundation, 59 Temple Place - Suite 330, -;; Boston, MA 02111-1307, USA. - - -;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. - -;; Define the attributes for the ROMP. - -;; Insn type. Used to default other attribute values. - -(define_attr "type" - "branch,ibranch,return,fp,load,loadz,store,call,address,arith,compare,multi,misc" - (const_string "arith")) - -;; Length in bytes. - -(define_attr "length" "" - (cond [(eq_attr "type" "branch") - (if_then_else (and (ge (minus (pc) (match_dup 0)) - (const_int -256)) - (le (minus (pc) (match_dup 0)) - (const_int 254))) - (const_int 2) - (const_int 4)) - (eq_attr "type" "return,ibranch") (const_int 2) - (eq_attr "type" "fp") (const_int 10) - (eq_attr "type" "call") (const_int 4) - (eq_attr "type" "load") - (cond [(match_operand 1 "short_memory_operand" "") (const_int 2) - (match_operand 1 "symbolic_memory_operand" "") (const_int 8)] - (const_int 4)) - (eq_attr "type" "loadz") - (cond [(match_operand 1 "zero_memory_operand" "") (const_int 2) - (match_operand 1 "symbolic_memory_operand" "") (const_int 8)] - (const_string "4")) - (eq_attr "type" "store") - (cond [(match_operand 0 "short_memory_operand" "") (const_int 2) - (match_operand 0 "symbolic_memory_operand" "") (const_int 8)] - (const_int 4))] - (const_int 4))) - -;; Whether insn can be placed in a delay slot. - -(define_attr "in_delay_slot" "yes,no" - (cond [(eq_attr "length" "8,10,38") (const_string "no") - (eq_attr "type" "branch,ibranch,return,call,multi") - (const_string "no")] - (const_string "yes"))) - -;; Whether insn needs a delay slot. We have to say that two-byte -;; branches do not need a delay slot. Otherwise, branch shortening will -;; try to do something with delay slot insns (we want it to on the PA). -;; This is a kludge, which should be cleaned up at some point. - -(define_attr "needs_delay_slot" "yes,no" - (if_then_else (ior (and (eq_attr "type" "branch") - (eq_attr "length" "4")) - (eq_attr "type" "ibranch,return,call")) - (const_string "yes") (const_string "no"))) - -;; What insn does to the condition code. - -(define_attr "cc" - "clobber,none,sets,change0,copy1to0,compare,tbit" - (cond [(eq_attr "type" "load,loadz") (const_string "change0") - (eq_attr "type" "store") (const_string "none") - (eq_attr "type" "fp,call") (const_string "clobber") - (eq_attr "type" "branch,ibranch,return") (const_string "none") - (eq_attr "type" "address") (const_string "change0") - (eq_attr "type" "compare") (const_string "compare") - (eq_attr "type" "arith") (const_string "sets")] - (const_string "clobber"))) - -;; Define attributes for `asm' insns. - -(define_asm_attributes [(set_attr "type" "misc") - (set_attr "length" "8") - (set_attr "in_delay_slot" "no") - (set_attr "cc" "clobber")]) - -;; Define the delay slot requirements for branches and calls. We don't have -;; any annulled insns. -;; -(define_delay (eq_attr "needs_delay_slot" "yes") - [(eq_attr "in_delay_slot" "yes") (nil) (nil)]) - -;; We cannot give a floating-point comparison a delay slot, even though it -;; could make use of it. This is because it would confuse next_cc0_user -;; to do so. Other fp insns can't get a delay slow because they set their -;; result and use their input after the delay slot insn is executed. This -;; isn't what reorg.c expects. - -;; Define load & store delays. These were obtained by measurements done by -;; jfc@athena.mit.edu. -;; -;; In general, the memory unit can support at most two simultaneous operations. -;; -;; Loads take 5 cycles to return the data and can be pipelined up to the -;; limit of two simultaneous operations. -(define_function_unit "memory" 1 2 (eq_attr "type" "load,loadz") 5 0) - -;; Stores do not return data, but tie up the memory unit for 2 cycles if the -;; next insn is also a store. -(define_function_unit "memory" 1 2 (eq_attr "type" "store") 1 2 - [(eq_attr "type" "store")]) - -;; Move word instructions. -;; -;; If destination is memory but source is not register, force source to -;; register. -;; -;; If source is a constant that is too large to load in a single insn, build -;; it in two pieces. -;; -;; If destination is memory and source is a register, a temporary register -;; will be needed. In that case, make a PARALLEL of the SET and a -;; CLOBBER of a SCRATCH to allocate the required temporary. -;; -;; This temporary is ACTUALLY only needed when the destination is a -;; relocatable expression. For generating RTL, however, we always -;; place the CLOBBER. In insns where it is not needed, the SCRATCH will -;; not be allocated to a register. -;; -;; Also, avoid creating pseudo-registers or SCRATCH rtx's during reload as -;; they will not be correctly handled. We never need pseudos for that -;; case anyway. -;; -;; We do not use DEFINE_SPLIT for loading constants because the number -;; of cases in the resulting unsplit insn would be too high to deal -;; with practically. -(define_expand "movsi" - [(set (match_operand:SI 0 "general_operand" "") - (match_operand:SI 1 "general_operand" ""))] - "" - " -{ rtx op0 = operands[0]; - rtx op1 = operands[1]; - - if (GET_CODE (op1) == REG && REGNO (op1) == 16) - DONE; - - if (GET_CODE (op0) == REG && REGNO (op0) == 16) - DONE; - - if (GET_CODE (op0) == MEM && ! reload_in_progress) - { - emit_insn (gen_storesi (operands[0], force_reg (SImode, operands[1]))); - DONE; - } - else if (GET_CODE (op1) == CONST_INT) - { - int const_val = INTVAL (op1); - - /* Try a number of cases to see how to best load the constant. */ - if ((const_val & 0xffff) == 0 - || (const_val & 0xffff0000) == 0 - || (unsigned) (const_val + 0x8000) < 0x10000) - /* Can do this in one insn, so generate it. */ - ; - else if (((- const_val) & 0xffff) == 0 - || ((- const_val) & 0xffff0000) == 0 - || (unsigned) ((- const_val) + 0x8000) < 0x10000) - { - /* Can do this by loading the negative constant and then negating. */ - emit_move_insn (operands[0], GEN_INT (- const_val)); - emit_insn (gen_negsi2 (operands[0], operands[0])); - DONE; - } - else - /* Do this the long way. */ - { - unsigned int high_part = const_val & 0xffff0000; - unsigned int low_part = const_val & 0xffff; - int i; - - if (low_part >= 0x10 && exact_log2 (low_part) >= 0) - i = high_part, high_part = low_part, low_part = i; - - emit_move_insn (operands[0], GEN_INT (low_part)); - emit_insn (gen_iorsi3 (operands[0], operands[0], - GEN_INT (high_part))); - DONE; - } - } -}") - -;; Move from a symbolic memory location to a register is special. In this -;; case, we know in advance that the register cannot be r0, so we can improve -;; register allocation by treating it separately. - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=b") - (match_operand:SI 1 "symbolic_memory_operand" "m"))] - "" - "load %0,%1" - [(set_attr "type" "load")]) - -;; Generic single-word move insn. We avoid the case where the destination is -;; a symbolic address, as that needs a temporary register. - -(define_insn "" - [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,r,r,r,b,Q") - (match_operand:SI 1 "romp_operand" "rR,I,K,L,M,S,s,Q,m,r"))] - "register_operand (operands[0], SImode) - || register_operand (operands[1], SImode)" - "@ - cas %0,%1,r0 - lis %0,%1 - cal %0,%1(r0) - cal16 %0,%1(r0) - cau %0,%H1(r0) - ail %0,r14,%C1 - get %0,$%1 - l%M1 %0,%1 - load %0,%1 - st%M0 %1,%0" - [(set_attr "type" "address,address,address,address,address,arith,misc,load,load,store") - (set_attr "length" "2,2,4,4,4,4,8,*,*,*")]) - -(define_insn "storesi" - [(set (match_operand:SI 0 "memory_operand" "=Q,m") - (match_operand:SI 1 "register_operand" "r,r")) - (clobber (match_scratch:SI 2 "=X,&b"))] - "" - "@ - st%M0 %1,%0 - store %1,%0,%2" - [(set_attr "type" "store")]) - -;; This pattern is used by reload when we store into a symbolic address. It -;; provides the temporary register required. This pattern is only used -;; when SECONDARY_OUTPUT_RELOAD_CLASS returns something other than -;; NO_REGS, so we need not have any predicates here. - -(define_expand "reload_outsi" - [(parallel [(set (match_operand:SI 0 "symbolic_memory_operand" "=m") - (match_operand:SI 1 "" "r")) - (clobber (match_operand:SI 2 "" "=&b"))])] - "" - "") - -;; Now do the same for the QI move instructions. -(define_expand "movqi" - [(set (match_operand:QI 0 "general_operand" "") - (match_operand:QI 1 "general_operand" ""))] - "" - " -{ rtx op0 = operands[0]; - - if (GET_CODE (op0) == MEM && ! reload_in_progress) - { - emit_insn (gen_storeqi (operands[0], force_reg (QImode, operands[1]))); - DONE; - } -}") - -(define_insn "" - [(set (match_operand:QI 0 "register_operand" "=b") - (match_operand:QI 1 "symbolic_memory_operand" "m"))] - "" - "loadc %0,%1" - [(set_attr "type" "load")]) - -(define_insn "" - [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,b,Q") - (match_operand:QI 1 "romp_operand" "r,I,n,s,Q,m,r"))] - "register_operand (operands[0], QImode) - || register_operand (operands[1], QImode)" - "@ - cas %0,%1,r0 - lis %0,%1 - cal %0,%L1(r0) - get %0,$%1 - lc%M1 %0,%1 - loadc %0,%1 - stc%M0 %1,%0" - [(set_attr "type" "address,address,address,misc,load,load,store") - (set_attr "length" "2,2,4,8,*,*,*")]) - -(define_insn "storeqi" - [(set (match_operand:QI 0 "memory_operand" "=Q,m") - (match_operand:QI 1 "register_operand" "r,r")) - (clobber (match_scratch:SI 2 "=X,&b"))] - "" - "@ - stc%M0 %1,%0 - storec %1,%0,%2" - [(set_attr "type" "store")]) - -(define_expand "reload_outqi" - [(parallel [(set (match_operand:QI 0 "symbolic_memory_operand" "=m") - (match_operand:QI 1 "" "r")) - (clobber (match_operand:SI 2 "" "=&b"))])] - "" - "") - -;; Finally, the HI instructions. -(define_expand "movhi" - [(set (match_operand:HI 0 "general_operand" "") - (match_operand:HI 1 "general_operand" ""))] - "" - " -{ rtx op0 = operands[0]; - - if (GET_CODE (op0) == MEM && ! reload_in_progress) - { - emit_insn (gen_storehi (operands[0], force_reg (HImode, operands[1]))); - DONE; - } -}") - -(define_insn "" - [(set (match_operand:HI 0 "register_operand" "=b") - (match_operand:HI 1 "symbolic_memory_operand" "m"))] - "" - "loadha %0,%1" - [(set_attr "type" "load")]) - - -;; use cal16 instead of cal for constant source because combine requires -;; the high bits of the register to be 0 after a HImode load of a constant - -(define_insn "" - [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,b,Q") - (match_operand:HI 1 "romp_operand" "r,I,n,s,Q,m,r"))] - "register_operand (operands[0], HImode) - || register_operand (operands[1], HImode)" - "@ - cas %0,%1,r0 - lis %0,%1 - cal16 %0,%L1(r0) - get %0,$%1 - lh%N1 %0,%1 - loadh %0,%1 - sth%M0 %1,%0" - [(set_attr "type" "address,address,address,misc,loadz,loadz,store") - (set_attr "length" "2,2,4,8,*,*,*")]) - -(define_insn "storehi" - [(set (match_operand:HI 0 "memory_operand" "=Q,m") - (match_operand:HI 1 "register_operand" "r,r")) - (clobber (match_scratch:SI 2 "=X,&b"))] - "" - "@ - sth%M0 %1,%0 - storeh %1,%0,%2" - [(set_attr "type" "store")]) - -(define_expand "reload_outhi" - [(parallel [(set (match_operand:HI 0 "symbolic_memory_operand" "=m") - (match_operand:HI 1 "" "r")) - (clobber (match_operand:SI 2 "" "=&b"))])] - "" - "") - -;; For DI move, if we have a constant, break the operation apart into -;; two SImode moves because the optimizer may be able to do a better job -;; with the resulting code. -;; -;; For memory stores, make the required pseudo for a temporary in case we -;; are storing into an absolute address. -;; -;; We need to be careful about the cases where the output is a register that is -;; the second register of the input. - -(define_expand "movdi" - [(set (match_operand:DI 0 "general_operand" "") - (match_operand:DI 1 "general_operand" ""))] - "" - " -{ rtx op0 = operands[0]; - rtx op1 = operands[1]; - - if (CONSTANT_P (op1)) - { - rtx insns; - - start_sequence (); - emit_move_insn (operand_subword (op0, 0, 1, DImode), - operand_subword (op1, 0, 1, DImode)); - emit_move_insn (operand_subword (op0, 1, 1, DImode), - operand_subword (op1, 1, 1, DImode)); - insns = get_insns (); - end_sequence (); - - emit_no_conflict_block (insns, op0, op1, 0, op1); - DONE; - } - - if (GET_CODE (op0) == MEM && ! reload_in_progress) - { - emit_insn (gen_storedi (operands[0], force_reg (DImode, operands[1]))); - DONE; - } -}") - -(define_insn "" - [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,Q") - (match_operand:DI 1 "reg_or_mem_operand" "r,Q,m,r"))] - "register_operand (operands[0], DImode) - || register_operand (operands[1], DImode)" - "* -{ - switch (which_alternative) - { - case 0: - if (REGNO (operands[0]) == REGNO (operands[1]) + 1) - return \"cas %O0,%O1,r0\;cas %0,%1,r0\"; - else - return \"cas %0,%1,r0\;cas %O0,%O1,r0\"; - case 1: - /* Here we must see which word to load first. We default to the - low-order word unless it occurs in the address. */ - if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, - operands[1], 0)) - return \"l%M1 %O0,%O1\;l%M1 %0,%1\"; - else - return \"l%M1 %0,%1\;l%M1 %O0,%O1\"; - case 2: - return \"get %O0,$%1\;ls %0,0(%O0)\;ls %O0,4(%O0)\"; - case 3: - return \"st%M0 %1,%0\;st%M0 %O1,%O0\"; - default: - abort(); - } -}" - [(set_attr "type" "multi") - (set_attr "cc" "change0,change0,change0,none") - (set_attr "length" "4,12,8,8")]) - -(define_insn "storedi" - [(set (match_operand:DI 0 "memory_operand" "=Q,m") - (match_operand:DI 1 "register_operand" "r,r")) - (clobber (match_scratch:SI 2 "=X,&b"))] - "" - "@ - st%M0 %1,%0\;st%M0 %O1,%O0 - get %2,$%0\;sts %1,0(%2)\;sts %O1,4(%2)" - [(set_attr "type" "multi,multi") - (set_attr "cc" "none,none") - (set_attr "length" "8,12")]) - -(define_expand "reload_outdi" - [(parallel [(set (match_operand:DI 0 "symbolic_memory_operand" "=m") - (match_operand:DI 1 "" "r")) - (clobber (match_operand:SI 2 "" "=&b"))])] - "" - "") - -;; Split symbolic memory operands differently. We first load the address -;; into a register and then do the two loads or stores. We can only do -;; this if operand_subword won't produce a SUBREG, which is only when -;; operands[0] is a hard register. Thus, these won't be used during the -;; first insn scheduling pass. -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "symbolic_memory_operand" ""))] - "GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (match_dup 5)) - (set (match_dup 6) (match_dup 7))] - " -{ operands[2] = operand_subword (operands[0], 1, 0, DImode); - operands[3] = XEXP (operands[1], 0); - operands[4] = operand_subword (operands[0], 0, 0, DImode); - operands[5] = gen_rtx_MEM (SImode, operands[2]); - operands[6] = operands[2]; - operands[7] = gen_rtx_MEM (SImode, plus_constant (operands[2], 4)); - - if (operands[2] == 0 || operands[4] == 0) - FAIL; -}") - -(define_split - [(set (match_operand:DI 0 "symbolic_memory_operand" "") - (match_operand:DI 1 "register_operand" "")) - (clobber (match_operand:SI 2 "register_operand" ""))] - "GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (match_dup 5)) - (set (match_dup 6) (match_dup 7))] - " -{ operands[3] = XEXP (operands[0], 0); - operands[4] = gen_rtx_MEM (SImode, operands[2]); - operands[5] = operand_subword (operands[1], 0, 0, DImode); - operands[6] = gen_rtx_MEM (SImode, plus_constant (operands[4], 4)); - operands[7] = operand_subword (operands[1], 1, 0, DImode); - - if (operands[5] == 0 || operands[7] == 0) - FAIL; -}") - -;; If the output is a register and the input is memory, we have to be careful -;; and see which word needs to be loaded first. -;; -;; Note that this case doesn't have a CLOBBER. Therefore, we must either -;; be after reload or operand[0] must not be a MEM. So we don't need a -;; CLOBBER on the new insns either. -;; -;; Due to a bug in sched.c, we do not want to split this insn if both -;; operands are registers and they overlap unless reload has completed. -(define_split - [(set (match_operand:DI 0 "general_operand" "") - (match_operand:DI 1 "general_operand" ""))] - "! symbolic_memory_operand (operands[0], DImode) - && ! symbolic_memory_operand (operands[1], DImode) - && ! (GET_CODE (operands[0]) == REG - && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) - && ! (GET_CODE (operands[1]) == REG - && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) - && ! (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG - && ! reload_completed - && reg_overlap_mentioned_p (operands[0], operands[1]))" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (match_dup 5))] - " -{ if (GET_CODE (operands[0]) != REG - || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, - operands[1], 0)) - { - operands[2] = operand_subword (operands[0], 0, 0, DImode); - operands[3] = operand_subword (operands[1], 0, 0, DImode); - operands[4] = operand_subword (operands[0], 1, 0, DImode); - operands[5] = operand_subword (operands[1], 1, 0, DImode); - } - else - { - operands[2] = operand_subword (operands[0], 1, 0, DImode); - operands[3] = operand_subword (operands[1], 1, 0, DImode); - operands[4] = operand_subword (operands[0], 0, 0, DImode); - operands[5] = operand_subword (operands[1], 0, 0, DImode); - } - - if (operands[2] == 0 || operands[3] == 0 - || operands[4] == 0 || operands[5] == 0) - FAIL; -}") - -(define_split - [(set (match_operand:DI 0 "general_operand" "") - (match_operand:DI 1 "general_operand" "")) - (clobber (match_operand:SI 6 "register_operand" ""))] - "! symbolic_memory_operand (operands[0], DImode) - && ! symbolic_memory_operand (operands[1], DImode) - && ! (GET_CODE (operands[0]) == REG - && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) - && ! (GET_CODE (operands[1]) == REG - && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) - && ! (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG - && ! reload_completed - && reg_overlap_mentioned_p (operands[0], operands[1]))" - [(parallel [(set (match_dup 2) (match_dup 3)) - (clobber (match_dup 7))]) - (parallel [(set (match_dup 4) (match_dup 5)) - (clobber (match_dup 8))])] - " -{ if (GET_CODE (operands[0]) != REG - || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, - operands[1], 0)) - { - operands[2] = operand_subword (operands[0], 0, 0, DImode); - operands[3] = operand_subword (operands[1], 0, 0, DImode); - operands[4] = operand_subword (operands[0], 1, 0, DImode); - operands[5] = operand_subword (operands[1], 1, 0, DImode); - } - else - { - operands[2] = operand_subword (operands[0], 1, 0, DImode); - operands[3] = operand_subword (operands[1], 1, 0, DImode); - operands[4] = operand_subword (operands[0], 0, 0, DImode); - operands[5] = operand_subword (operands[1], 0, 0, DImode); - } - - if (operands[2] == 0 || operands[3] == 0 - || operands[4] == 0 || operands[5] == 0) - FAIL; - - /* We must be sure to make two different SCRATCH operands, since they - are not allowed to be shared. After reload, however, we only have - a SCRATCH if we won't use the operand, so it is allowed to share it - then. */ - if (reload_completed || GET_CODE (operands[6]) != SCRATCH) - operands[7] = operands[8] = operands[6]; - else - { - operands[7] = gen_rtx_SCRATCH (SImode); - operands[8] = gen_rtx_SCRATCH (SImode); - } -}") - -;; Define move insns for SF, and DF. -;; -;; For register-register copies or a copy of something to itself, emit a -;; single SET insn since it will likely be optimized away. -;; -;; Otherwise, emit a floating-point move operation unless both input and -;; output are either constant, memory, or a non-floating-point hard register. -(define_expand "movdf" - [(parallel [(set (match_operand:DF 0 "general_operand" "") - (match_operand:DF 1 "general_operand" "")) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - " -{ rtx op0 = operands[0]; - rtx op1 = operands[1]; - - if (op0 == op1) - { - emit_insn (gen_rtx_SET (VOIDmode, op0, op1)); - DONE; - } - - if ((GET_CODE (op0) == MEM - || (GET_CODE (op0) == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER - && ! FP_REGNO_P (REGNO (op0)))) - && (GET_CODE (op1) == MEM - || GET_CODE (op1) == CONST_DOUBLE - || (GET_CODE (op1) == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER - && ! FP_REGNO_P (REGNO (op1)) && ! rtx_equal_p (op0, op1)))) - { - rtx insns; - - if (GET_CODE (op1) == CONST_DOUBLE) - op1 = force_const_mem (DFmode, op1); - - start_sequence (); - if (GET_CODE (operands[0]) != REG - || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, - operands[1], 0)) - { - emit_move_insn (operand_subword (op0, 0, 1, DFmode), - operand_subword_force (op1, 0, DFmode)); - emit_move_insn (operand_subword (op0, 1, 1, DFmode), - operand_subword_force (op1, 1, DFmode)); - } - else - { - emit_move_insn (operand_subword (op0, 1, 1, DFmode), - operand_subword_force (op1, 1, DFmode)); - emit_move_insn (operand_subword (op0, 0, 1, DFmode), - operand_subword_force (op1, 0, DFmode)); - } - - insns = get_insns (); - end_sequence (); - - emit_no_conflict_block (insns, op0, op1, 0, op1); - DONE; - } -}") - -(define_expand "movsf" - [(parallel [(set (match_operand:SF 0 "general_operand" "") - (match_operand:SF 1 "general_operand" "")) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - " -{ rtx op0 = operands[0]; - rtx op1 = operands[1]; - - if (op0 == op1) - { - emit_insn (gen_rtx_SET (VOIDmode, op0, op1)); - DONE; - } - - if ((GET_CODE (op0) == MEM - || (GET_CODE (op0) == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER - && ! FP_REGNO_P (REGNO (op0)))) - && (GET_CODE (op1) == MEM - || GET_CODE (op1) == CONST_DOUBLE - || (GET_CODE (op1) == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER - && ! FP_REGNO_P (REGNO (op1))))) - { - rtx last; - - if (GET_CODE (op1) == CONST_DOUBLE) - op1 = force_const_mem (SFmode, op1); - - last = emit_move_insn (operand_subword (op0, 0, 1, SFmode), - operand_subword_force (op1, 0, SFmode)); - - REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (last)); - DONE; - } -}") - -;; Define the move insns for SF and DF. Check for all general regs -;; in the FP insns and make them non-FP if so. Do the same if the input and -;; output are the same (the insn will be deleted in this case and we don't -;; want to think there are FP insns when there might not be). -(define_insn "" - [(set (match_operand:SF 0 "general_operand" "=*frg") - (match_dup 0))] - "" - "nopr r0" - [(set_attr "type" "address") - (set_attr "length" "2")]) - -(define_insn "" - [(set (match_operand:SF 0 "general_operand" "=r,*fr,r,r,Q,m,frg") - (match_operand:SF 1 "general_operand" "r,0,Q,m,r,r,frg")) - (clobber (match_operand:SI 2 "reg_0_operand" "=&z,z,z,z,z,z,z")) - (clobber (match_operand:SI 3 "reg_15_operand" "=&t,t,t,t,t,t,t"))] - "" - "* -{ switch (which_alternative) - { - case 0: - return \"cas %0,%1,r0\"; - case 1: - return \"nopr r0\"; - case 2: - return \"l%M1 %0,%1\"; - case 3: - return \"load %0,%1\"; - case 4: - return \"st%M0 %1,%0\"; - case 5: - return \"store %1,%0,%3\"; - default: - return output_fpop (SET, operands[0], operands[1], 0, insn); - } -}" - [(set_attr "type" "address,address,load,load,store,store,fp") - (set_attr "length" "2,2,*,*,*,*,*")]) - -(define_insn "" - [(set (match_operand:DF 0 "general_operand" "=*frg") - (match_dup 0))] - "" - "nopr r0" - [(set_attr "type" "address") - (set_attr "length" "2")]) - -(define_insn "" - [(set (match_operand:DF 0 "general_operand" "=r,*fr,r,r,Q,m,frg") - (match_operand:DF 1 "general_operand" "r,0,Q,m,r,r,*frg")) - (clobber (match_operand:SI 2 "reg_0_operand" "=&z,z,z,z,z,z,z")) - (clobber (match_operand:SI 3 "reg_15_operand" "=&t,t,t,t,t,t,t"))] - "" - "* -{ switch (which_alternative) - { - case 0: - if (REGNO (operands[0]) == REGNO (operands[1]) + 1) - return \"cas %O0,%O1,r0\;cas %0,%1,r0\"; - else - return \"cas %0,%1,r0\;cas %O0,%O1,r0\"; - case 1: - return \"nopr r0\"; - case 2: - /* Here we must see which word to load first. We default to the - low-order word unless it occurs in the address. */ - if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, - operands[1], 0)) - return \"l%M1 %O0,%O1\;l%M1 %0,%1\"; - else - return \"l%M1 %0,%1\;l%M1 %O0,%O1\"; - case 3: - return \"get %3,$%1\;ls %0,0(%3)\;ls %O0,4(%3)\"; - case 4: - return \"st%M0 %1,%0\;st%M0 %O1,%O0\"; - case 5: - return \"get %3,$%0\;sts %1,0(%3)\;sts %O1,4(%3)\"; - default: - return output_fpop (SET, operands[0], operands[1], 0, insn); - } -}" - [(set_attr "type" "address,multi,multi,multi,multi,multi,fp") - (set_attr "length" "2,4,*,*,*,*,*")]) - -;; Split all the above cases that involve multiple insns and no floating-point -;; data block. If before reload, we can make a SCRATCH. Otherwise, use -;; register 15. - -(define_split - [(set (match_operand:DF 0 "register_operand" "") - (match_operand:DF 1 "symbolic_memory_operand" "")) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))] - "GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 16" - [(set (reg:SI 15) (match_dup 2)) - (set (match_dup 3) (match_dup 4)) - (set (match_dup 5) (match_dup 6))] - " -{ operands[2] = XEXP (operands[1], 0); - operands[3] = operand_subword (operands[0], 0, 0, DFmode); - operands[4] = gen_rtx_MEM (SImode, gen_rtx (REG, SImode, 15)); - operands[5] = operand_subword (operands[0], 1, 0, DFmode); - operands[6] = gen_rtx_MEM (SImode, - plus_constant (gen_rtx (REG, SImode, 15), 4)); - - if (operands[3] == 0 || operands[5] == 0) - FAIL; -}") - -(define_split - [(set (match_operand:DF 0 "symbolic_memory_operand" "") - (match_operand:DF 1 "register_operand" "")) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))] - "GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 16" - [(set (reg:SI 15) (match_dup 2)) - (set (match_dup 3) (match_dup 4)) - (set (match_dup 5) (match_dup 6))] - " -{ operands[2] = XEXP (operands[0], 0); - operands[3] = gen_rtx_MEM (SImode, gen_rtx (REG, SImode, 15)); - operands[4] = operand_subword (operands[1], 0, 0, DFmode); - operands[5] = gen_rtx_MEM (SImode, - plus_constant (gen_rtx_REG (SImode, 15), 4)); - operands[6] = operand_subword (operands[1], 1, 0, DFmode); - - if (operands[4] == 0 || operands[6] == 0) - FAIL; -}") - -;; If the output is a register and the input is memory, we have to be careful -;; and see which word needs to be loaded first. We also cannot to the -;; split if the input is a constant because it would result in invalid -;; insns. When the output is a MEM, we must put a CLOBBER on each of the -;; resulting insn, when it is not a MEM, we must not. -(define_split - [(set (match_operand:DF 0 "memory_operand" "") - (match_operand:DF 1 "register_operand" "")) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))] - "GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 15" - [(parallel [(set (match_dup 2) (match_dup 3)) - (clobber (match_dup 6))]) - (parallel [(set (match_dup 4) (match_dup 5)) - (clobber (match_dup 7))])] - " -{ operands[2] = operand_subword (operands[0], 0, 0, DFmode); - operands[3] = operand_subword (operands[1], 0, 0, DFmode); - operands[4] = operand_subword (operands[0], 1, 0, DFmode); - operands[5] = operand_subword (operands[1], 1, 0, DFmode); - - if (operands[2] == 0 || operands[3] == 0 - || operands[4] == 0 || operands[5] == 0) - FAIL; - - if (reload_completed) - operands[6] = operands[7] = gen_rtx_REG (SImode, 15); - else - { - operands[6] = gen_rtx_SCRATCH (SImode); - operands[7] = gen_rtx_SCRATCH (SImode); - } -}") - -(define_split - [(set (match_operand:DF 0 "nonmemory_operand" "") - (match_operand:DF 1 "general_operand" "")) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))] - "! symbolic_memory_operand (operands[1], DFmode) - && GET_CODE (operands[1]) != CONST_DOUBLE - && (GET_CODE (operands[0]) != REG || REGNO (operands[0]) < 15) - && (GET_CODE (operands[1]) != REG || REGNO (operands[1]) < 15) - && (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG) - && ! (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG - && ! reload_completed - && reg_overlap_mentioned_p (operands[0], operands[1]))" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (match_dup 5))] - " -{ if (GET_CODE (operands[0]) != REG - || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, - operands[1], 0)) - { - operands[2] = operand_subword (operands[0], 0, 0, DFmode); - operands[3] = operand_subword (operands[1], 0, 0, DFmode); - operands[4] = operand_subword (operands[0], 1, 0, DFmode); - operands[5] = operand_subword (operands[1], 1, 0, DFmode); - } - else - { - operands[2] = operand_subword (operands[0], 1, 0, DFmode); - operands[3] = operand_subword (operands[1], 1, 0, DFmode); - operands[4] = operand_subword (operands[0], 0, 0, DFmode); - operands[5] = operand_subword (operands[1], 0, 0, DFmode); - } - - if (operands[2] == 0 || operands[3] == 0 - || operands[4] == 0 || operands[5] == 0) - FAIL; -}") - -;; Conversions from one integer mode to another. -;; It is possible sometimes to sign- or zero-extend while fetching from memory. -;; -;; First, sign-extensions: -(define_expand "extendhisi2" - [(set (match_operand:SI 0 "register_operand" "") - (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] - "" - "") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=b") - (sign_extend:SI (match_operand:HI 1 "symbolic_memory_operand" "m")))] - "" - "loadha %0,%1" - [(set_attr "type" "load")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,b") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Q,m")))] - "" - "@ - exts %0,%1 - lha%M1 %0,%1 - loadha %0,%1" - [(set_attr "type" "arith,load,load") - (set_attr "length" "2,*,*")]) - -(define_expand "extendqisi2" - [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "register_operand" "") - (const_int 24))) - (set (match_operand:SI 0 "register_operand" "") - (ashiftrt:SI (match_dup 2) - (const_int 24)))] - "" - " -{ operands[1] = gen_lowpart (SImode, operands[1]); - operands[2] = gen_reg_rtx (SImode); }") - -(define_expand "extendqihi2" - [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "register_operand" "") - (const_int 24))) - (set (match_operand:HI 0 "register_operand" "") - (ashiftrt:SI (match_dup 2) - (const_int 24)))] - "" - " -{ operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]); - operands[2] = gen_reg_rtx (SImode); }") - -;; Define peepholes to eliminate an instruction when we are doing a sign -;; extension but cannot clobber the input. -;; -;; In this case we will shift left 24 bits, but need a copy first. The shift -;; can be replaced by a "mc03" instruction, but this can only be done if -;; followed by the right shift of 24 or more bits. -(define_peephole - [(set (match_operand:SI 0 "register_operand" "") - (subreg:SI (match_operand:QI 1 "register_operand" "") 0)) - (set (match_dup 0) - (ashift:SI (match_dup 0) - (const_int 24))) - (set (match_dup 0) - (ashiftrt:SI (match_dup 0) - (match_operand:SI 2 "const_int_operand" "")))] - "INTVAL (operands[2]) >= 24" - "mc03 %0,%1\;sari16 %0,%S2" - [(set_attr "type" "multi") - (set_attr "length" "4") - (set_attr "cc" "sets")]) - -;; Now zero extensions: -(define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] - "" - "") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=b") - (zero_extend:SI (match_operand:HI 1 "symbolic_memory_operand" "m")))] - "" - "loadh %0,%1" - [(set_attr "type" "load")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,b") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Q,m")))] - "" - "@ - nilz %0,%1,65535 - lh%N1 %0,%1 - loadh %0,%1" - [(set_attr "type" "arith,loadz,load")]) - -(define_expand "zero_extendqisi2" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] - "" - "") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=b") - (zero_extend:SI (match_operand:QI 1 "symbolic_memory_operand" "m")))] - "" - "loadc %0,%1" - [(set_attr "type" "load")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,b") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Q,m")))] - "" - "@ - nilz %0,%1,255 - lc%M1 %0,%1 - loadc %0,%1" - [(set_attr "type" "arith,load,load")]) - -(define_expand "zero_extendqihi2" - [(set (match_operand:HI 0 "register_operand" "") - (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] - "" - "") - -(define_insn "" - [(set (match_operand:HI 0 "register_operand" "=b") - (zero_extend:HI (match_operand:QI 1 "symbolic_memory_operand" "m")))] - "" - "loadc %0,%1" - [(set_attr "type" "load")]) - -(define_insn "" - [(set (match_operand:HI 0 "register_operand" "=r,r,b") - (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,Q,m")))] - "" - "@ - nilz %0,%1,255 - lc%M1 %0,%1 - loadc %0,%1" - [(set_attr "type" "arith,load,load")]) - -;; Various extract and insertion operations. -(define_expand "extzv" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extract:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" "") - (match_operand:SI 3 "const_int_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8) - FAIL; - - if (GET_CODE (operands[3]) != CONST_INT) - FAIL; - - if (INTVAL (operands[3]) != 0 && INTVAL (operands[3]) != 8 - && INTVAL (operands[3]) != 16 && INTVAL (operands[3]) != 24) - FAIL; -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=&r") - (zero_extract:SI (match_operand:SI 1 "register_operand" "r") - (const_int 8) - (match_operand:SI 2 "const_int_operand" "n")))] - "(INTVAL (operands[2]) & 7) == 0" - "lis %0,0\;mc3%B2 %0,%1" - [(set_attr "type" "multi") - (set_attr "cc" "change0")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "=&r") - (zero_extract:SI (match_operand:SI 1 "register_operand" "r") - (const_int 8) - (match_operand:SI 2 "const_int_operand" "n")))] - "(INTVAL (operands[2]) & 7) == 0" - [(set (match_dup 0) (const_int 0)) - (set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 24)) - (zero_extract:SI (match_dup 1) (const_int 8) (match_dup 2)))] - "") - -(define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") - (const_int 8) - (const_int 24)) - (zero_extract:SI (match_operand:SI 1 "register_operand" "r") - (const_int 8) - (match_operand:SI 2 "const_int_operand" "n")))] - "(INTVAL (operands[2]) & 7) == 0" - "mc3%B2 %0,%1" - [(set_attr "type" "address") - (set_attr "length" "2")]) - -(define_expand "insv" - [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "const_int_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "register_operand" ""))] - "" - " -{ - if (GET_CODE (operands[2]) != CONST_INT) - FAIL; - - if (GET_CODE (operands[1]) != CONST_INT) - FAIL; - - if (INTVAL (operands[1]) == 1) - { - emit_insn (gen_bit_insv (operands[0], operands[1], operands[2], - operands[3])); - DONE; - } - else if (INTVAL (operands[1]) == 8 - && (INTVAL (operands[2]) % 8 == 0)) - ; /* Accept aligned byte-wide field. */ - else - FAIL; -}") - -;; For a single-bit insert, it is better to explicitly generate references -;; to the T bit. We will call the T bit "CC0" because it can be clobbered -;; by some CC0 sets (single-bit tests). - -(define_expand "bit_insv" - [(set (cc0) - (zero_extract:SI (match_operand:SI 3 "register_operand" "") - (const_int 1) - (const_int 31))) - (parallel [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "const_int_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (ne (cc0) (const_int 0))) - (clobber (match_scratch:SI 4 ""))])] - "" - "") - -(define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") - (const_int 8) - (match_operand:SI 1 "const_int_operand" "n")) - (match_operand:SI 2 "register_operand" "r"))] - "(INTVAL (operands[1]) & 7) == 0" - "mc%B1%.3 %0,%2" - [(set_attr "type" "address") - (set_attr "length" "2")]) - -;; This pattern cannot have any input reloads since if references CC0. -;; So we have to add code to support memory, which is the only other -;; thing that a "register_operand" can become. There is still a problem -;; if the address isn't valid and *it* needs a reload, but there is no -;; way to solve that problem, so let's hope it never happens. - -(define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,m") - (const_int 1) - (match_operand:SI 1 "const_int_operand" "n,m")) - (ne (cc0) (const_int 0))) - (clobber (match_scratch:SI 2 "=X,b"))] - "" - "@ - mftbi%t1 %0,%S1 - l%M0 %2,%0\;mftb%t1 %2,%S1\;st%M0 %2,%0" - [(set_attr "type" "*,multi") - (set_attr "cc" "none,none") - (set_attr "length" "2,10")]) - -;; Arithmetic instructions. First, add and subtract. -;; -;; It may be that the second input is either large or small enough that -;; the operation cannot be done in a single insn. In that case, emit two. -(define_expand "addsi3" - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned) (INTVAL (operands[2]) + 0x8000) >= 0x10000 - && (INTVAL (operands[2]) & 0xffff) != 0) - { - int low = INTVAL (operands[2]) & 0xffff; - int high = (unsigned) INTVAL (operands[2]) >> 16; - - if (low & 0x8000) - high++, low |= 0xffff0000; - - emit_insn (gen_addsi3 (operands[0], operands[1], GEN_INT (high << 16))); - operands[1] = operands[0]; - operands[2] = GEN_INT (low); - } -}") - -;; Put the insn to add a symbolic constant to a register separately to -;; improve register allocation since it has different register requirements. -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=b") - (plus:SI (match_operand:SI 1 "register_operand" "%b") - (match_operand:SI 2 "romp_symbolic_operand" "s")))] - "" - "get %0,$%2(%1)" - [(set_attr "type" "address") - (set_attr "length" "8")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,b") - (plus:SI (match_operand:SI 1 "reg_or_add_operand" "%0,0,r,b,0,r,b") - (match_operand:SI 2 "reg_or_add_operand" "I,J,K,M,r,b,s")))] - "register_operand (operands[1], SImode) - || register_operand (operands[2], SImode)" - "@ - ais %0,%2 - sis %0,%n2 - ail %0,%1,%2 - cau %0,%H2(%1) - a %0,%2 - cas %0,%1,%2 - get %0,$%2(%1)" - [(set_attr "type" "arith,arith,arith,address,arith,address,misc") - (set_attr "length" "2,2,4,4,2,2,8")]) - -;; Now subtract. -;; -;; 1. If third operand is constant integer, convert it to add of the negative -;; of that integer. -;; 2. If the second operand is not a valid constant integer, force it into a -;; register. -(define_expand "subsi3" - [(set (match_operand:SI 0 "register_operand" "") - (minus:SI (match_operand:SI 1 "reg_or_any_cint_operand" "") - (match_operand:SI 2 "reg_or_any_cint_operand" "")))] - "" - " -{ - if (GET_CODE (operands [2]) == CONST_INT) - { - emit_insn (gen_addsi3 (operands[0], operands[1], - GEN_INT (- INTVAL (operands[2])))); - DONE; - } - else - operands[2] = force_reg (SImode, operands[2]); - - if (GET_CODE (operands[1]) != CONST_INT - || (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000) - operands[1] = force_reg (SImode, operands[1]); -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (minus:SI (match_operand:SI 1 "reg_or_D_operand" "K,0,r") - (match_operand:SI 2 "register_operand" "r,r,0")))] - "" - "@ - sfi %0,%2,%1 - s %0,%2 - sf %0,%1" - [(set_attr "length" "4,2,2")]) - -;; Multiply either calls a special RT routine or is done in-line, depending -;; on the value of a -m flag. -;; -;; First define the way we call the subroutine. -(define_expand "mulsi3_subr" - [(set (reg:SI 2) (match_operand:SI 1 "register_operand" "")) - (set (reg:SI 3) (match_operand:SI 2 "register_operand" "")) - (parallel [(set (reg:SI 2) (mult:SI (reg:SI 2) (reg:SI 3))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))]) - (set (match_operand:SI 0 "register_operand" "") - (reg:SI 2))] - "" - "") - -(define_expand "mulsi3" - [(set (match_operand:SI 0 "register_operand" "") - (mult:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "register_operand" "")))] - "" - " -{ - if (! TARGET_IN_LINE_MUL) - { - emit_insn (gen_mulsi3_subr (operands[0], operands[1], operands[2])); - DONE; - } -}") - -;; Define the patterns to match. -;; We would like to provide a delay slot for the insns that call internal -;; routines, but doing so is risky since reorg will think that the use of -;; r2 and r3 is completed in the insn needing the delay slot. Also, it -;; won't know that the cc will be clobbered. So take the safe approach -;; and don't give them delay slots. -(define_insn "" - [(set (reg:SI 2) - (mult:SI (reg:SI 2) (reg:SI 3))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))] - "! TARGET_IN_LINE_MUL" - "bali%# r15,lmul$$" - [(set_attr "type" "misc") - (set_attr "in_delay_slot" "no")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=&r") - (mult:SI (match_operand:SI 1 "register_operand" "%r") - (match_operand:SI 2 "register_operand" "r")))] - "TARGET_IN_LINE_MUL" - "* -{ return output_in_line_mul (); }" - [(set_attr "length" "38") - (set_attr "type" "multi")]) - -;; Handle divide and modulus. The same function returns both values, -;; so use divmodsi4. This divides arg 1 by arg 2 with quotient to go -;; into arg 0 and remainder in arg 3. -;; -;; We want to put REG_EQUAL notes for the two outputs. So we need a -;; function to do everything else. -(define_expand "divmodsi4_doit" - [(set (reg:SI 2) - (match_operand:SI 0 "register_operand" "")) - (set (reg:SI 3) - (match_operand:SI 1 "register_operand" "")) - (parallel [(set (reg:SI 2) (div:SI (reg:SI 2) (reg:SI 3))) - (set (reg:SI 3) (mod:SI (reg:SI 2) (reg:SI 3))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "divmodsi4" - [(parallel [(set (match_operand:SI 0 "register_operand" "") - (div:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "register_operand" ""))) - (set (match_operand:SI 3 "register_operand" "") - (mod:SI (match_dup 1) (match_dup 2)))])] - "" - " -{ - rtx insn; - - emit_insn (gen_divmodsi4_doit (operands[1], operands[2])); - insn = emit_move_insn (operands[0], gen_rtx_REG (SImode, 2)); - REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, - gen_rtx_DIV (SImode, operands[1], - operands[2]), - REG_NOTES (insn)); - insn = emit_move_insn (operands[3], gen_rtx_REG (SImode, 3)); - REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, - gen_rtx_MOD (SImode, operands[1], - operands[2]), - REG_NOTES (insn)); - DONE; -}") - -(define_insn "" - [(set (reg:SI 2) - (div:SI (reg:SI 2) (reg:SI 3))) - (set (reg:SI 3) - (mod:SI (reg:SI 2) (reg:SI 3))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))] - "" - "bali%# r15,ldiv$$" - [(set_attr "type" "misc") - (set_attr "in_delay_slot" "no")]) - -;; Similarly for unsigned divide. -(define_expand "udivmodsi4_doit" - [(set (reg:SI 2) - (match_operand:SI 0 "register_operand" "")) - (set (reg:SI 3) - (match_operand:SI 1 "register_operand" "")) - (parallel [(set (reg:SI 2) (udiv:SI (reg:SI 2) (reg:SI 3))) - (set (reg:SI 3) (umod:SI (reg:SI 2) (reg:SI 3))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "udivmodsi4" - [(parallel [(set (match_operand:SI 0 "register_operand" "") - (udiv:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "register_operand" ""))) - (set (match_operand:SI 3 "register_operand" "") - (umod:SI (match_dup 1) (match_dup 2)))])] - "" - " -{ - rtx insn; - - emit_insn (gen_udivmodsi4_doit (operands[1], operands[2])); - insn = emit_move_insn (operands[0], gen_rtx_REG (SImode, 2)); - REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, - gen_rtx_UDIV (SImode, operands[1], - operands[2]), - REG_NOTES (insn)); - insn = emit_move_insn (operands[3], gen_rtx_REG (SImode, 3)); - REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, - gen_rtx_UMOD (SImode, operands[1], - operands[2]), - REG_NOTES (insn)); - DONE; -}") - -(define_insn "" - [(set (reg:SI 2) - (udiv:SI (reg:SI 2) (reg:SI 3))) - (set (reg:SI 3) - (umod:SI (reg:SI 2) (reg:SI 3))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))] - "" - "bali%# r15,uldiv$$" - [(set_attr "type" "misc") - (set_attr "in_delay_slot" "no")]) - -;; Define DImode arithmetic operations. -;; -;; It is possible to do certain adds and subtracts with constants in a single -;; insn, but it doesn't seem worth the trouble. -;; -;; Don't use DEFINE_SPLIT on these because the dependency on CC can't be -;; easily tracked in that case! -(define_insn "adddi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (match_operand:DI 1 "register_operand" "%0") - (match_operand:DI 2 "register_operand" "r")))] - "" - "a %O0,%O2\;ae %0,%2" - [(set_attr "type" "multi")]) - -(define_insn "subdi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:DI 2 "register_operand" "r")))] - "" - "s %O0,%O2\;se %0,%2" - [(set_attr "type" "multi")]) - -(define_insn "negdi2" - [(set (match_operand:DI 0 "register_operand" "=r,&r") - (neg:DI (match_operand:DI 1 "register_operand" "0,r")))] - "" - "twoc %O0,%O1\;onec %0,%1\;aei %0,%0,0" - [(set_attr "type" "multi") - (set_attr "length" "8")]) - -;; Unary arithmetic operations. -(define_insn "abssi2" - [(set (match_operand:SI 0 "register_operand" "=r") - (abs:SI (match_operand:SI 1 "register_operand" "r")))] - "" - "abs %0,%1" - [(set_attr "length" "2")]) - -(define_insn "negsi2" - [(set (match_operand:SI 0 "register_operand" "=r") - (neg:SI (match_operand:SI 1 "register_operand" "r")))] - "" - "twoc %0,%1" - [(set_attr "length" "2")]) - -(define_insn "one_cmplsi2" - [(set (match_operand:SI 0 "register_operand" "=r") - (not:SI (match_operand:SI 1 "register_operand" "r")))] - "" - "onec %0,%1" - [(set_attr "length" "2")]) - - -;; Logical insns: AND, IOR, and XOR -;; -;; If the operation is being performed on a 32-bit constant such that -;; it cannot be done in one insn, do it in two. We may lose a bit on -;; CSE in pathological cases, but it seems better doing it this way. -(define_expand "andsi3" - [(set (match_operand:SI 0 "register_operand" "") - (and:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "reg_or_any_cint_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - int top = (unsigned) INTVAL (operands[2]) >> 16; - int bottom = INTVAL (operands[2]) & 0xffff; - - if (top != 0 && top != 0xffff && bottom != 0 && bottom != 0xffff) - { - emit_insn (gen_andsi3 (operands[0], operands[1], - GEN_INT ((top << 16) | 0xffff))); - operands[1] = operands[0]; - operands[2] = GEN_INT (0xffff0000 | bottom); - } - } -}"); - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (and:SI (match_operand:SI 1 "reg_or_and_operand" "%0,r,0") - (match_operand:SI 2 "reg_or_and_operand" "P,LMO,r")))] - "register_operand (operands[1], SImode) - || register_operand (operands[2], SImode)" - "@ - clrb%k2 %0,%b2 - ni%z2 %0,%1,%Z2 - n %0,%2" - [(set_attr "length" "2,4,2")]) - -;; logical OR (IOR) -(define_expand "iorsi3" - [(set (match_operand:SI 0 "register_operand" "") - (ior:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "reg_or_any_cint_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - int top = (unsigned) INTVAL (operands[2]) >> 16; - int bottom = INTVAL (operands[2]) & 0xffff; - - if (top != 0 && bottom != 0) - { - emit_insn (gen_iorsi3 (operands[0], operands[1], - GEN_INT (top << 16))); - operands[1] = operands[0]; - operands[2] = GEN_INT (bottom); - } - } -}"); - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (ior:SI (match_operand:SI 1 "reg_or_cint_operand" "%0,r,0") - (match_operand:SI 2 "reg_or_cint_operand" "N,LM,r")))] - "register_operand (operands[1], SImode) - || register_operand (operands[2], SImode)" - "@ - setb%h2 %0,%b2 - oi%h2 %0,%1,%H2 - o %0,%2" - [(set_attr "length" "2,4,2")]) - -;; exclusive-or (XOR) -(define_expand "xorsi3" - [(set (match_operand:SI 0 "register_operand" "") - (xor:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "reg_or_any_cint_operand" "")))] - "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - int top = (unsigned) INTVAL (operands[2]) >> 16; - int bottom = INTVAL (operands[2]) & 0xffff; - - if (top == 0xffff && bottom == 0xffff) - { - emit_insn (gen_one_cmplsi2 (operands[0], operands[1])); - DONE; - } - else if (top != 0 && bottom != 0) - { - emit_insn (gen_xorsi3 (operands[0], operands[1], - GEN_INT (top << 16))); - operands[1] = operands[0]; - operands[2] = GEN_INT (bottom); - } - } -}"); - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (xor:SI (match_operand:SI 1 "reg_or_cint_operand" "%r,0") - (match_operand:SI 2 "reg_or_cint_operand" "LM,r")))] - "register_operand (operands[1], SImode) - || register_operand (operands[2], SImode)" - "@ - xi%h2 %0,%1,%H2 - x %0,%2" - [(set_attr "length" "4,2")]) - -;; Various shift insns -(define_insn "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "reg_or_cint_operand" "r,n")))] - "" - "@ - sar %0,%2 - sari%s2 %0,%S2" - [(set_attr "length" "2")]) - -(define_insn "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "reg_or_cint_operand" "r,n")))] - "" - "@ - sr %0,%2 - sri%s2 %0,%S2" - [(set_attr "length" "2")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (ashift:SI (match_operand:SI 1 "register_operand" "b") - (const_int 1)))] - "" - "cas %0,%1,%1" - [(set_attr "length" "2") - (set_attr "type" "address")]) - -(define_insn "ashlsi3" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (ashift:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "reg_or_cint_operand" "r,n")))] - "" - "@ - sl %0,%2 - sli%s2 %0,%S2" - [(set_attr "length" "2")]) - -;; Function call insns: -;; -;; On the ROMP, &fcn is actually a pointer to the data area, which is passed -;; to the function in r0. &.fcn is the actual starting address of the -;; function. Also, the word at &fcn contains &.fcn. -;; -;; For both functions that do and don't return values, there are two cases: -;; where the function's address is a constant, and where it isn't. -;; -;; Operand 1 (2 for `call_value') is the number of arguments and is not used. -(define_expand "call" - [(use (match_operand:SI 0 "address_operand" "")) - (use (match_operand 1 "" ""))] - "" - " -{ - rtx reg0 = gen_rtx_REG (SImode, 0); - rtx call_insn; - - if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) - abort(); - - operands[0] = XEXP (operands[0], 0); - if (GET_CODE (operands[0]) == SYMBOL_REF) - { - char *real_fcnname - = (char *) alloca (strlen (XSTR (operands[0], 0)) + 2); - - /* Copy the data area address to r0. */ - emit_move_insn (reg0, force_reg (SImode, operands[0])); - strcpy (real_fcnname, \".\"); - strcat (real_fcnname, XSTR (operands[0], 0)); - operands[0] = get_symref (real_fcnname); - } - else - { - rtx data_access; - - emit_move_insn (reg0, force_reg (SImode, operands[0])); - data_access = gen_rtx_MEM (SImode, operands[0]); - RTX_UNCHANGING_P (data_access) = 1; - operands[0] = copy_to_reg (data_access); - } - - call_insn = emit_call_insn (gen_call_internal (operands[0], operands[1])); - use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), reg0); - DONE; -}") - -(define_insn "call_internal" - [(call (mem:SI (match_operand:SI 0 "register_operand" "b")) - (match_operand 1 "" "g")) - (clobber (reg:SI 15))] - "" - "balr%# r15,%0" - [(set_attr "type" "call") - (set_attr "length" "2")]) - -(define_insn "" - [(call (mem:SI (match_operand:SI 0 "romp_symbolic_operand" "i")) - (match_operand 1 "" "g")) - (clobber (reg:SI 15))] - "GET_CODE (operands[0]) == SYMBOL_REF" - "bali%# r15,%0" - [(set_attr "type" "call")]) - -;; Call a function and return a value. -(define_expand "call_value" - [(use (match_operand 0 "" "")) - (use (match_operand:SI 1 "address_operand" "")) - (use (match_operand 2 "" ""))] - "" - " -{ - rtx reg0 = gen_rtx_REG (SImode, 0); - rtx call_insn; - - if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) - abort(); - - operands[1] = XEXP (operands[1], 0); - if (GET_CODE (operands[1]) == SYMBOL_REF) - { - char *real_fcnname = - (char *) alloca (strlen (XSTR (operands[1], 0)) + 2); - - /* Copy the data area address to r0. */ - emit_move_insn (reg0,force_reg (SImode, operands[1])); - strcpy (real_fcnname, \".\"); - strcat (real_fcnname, XSTR (operands[1], 0)); - operands[1] = get_symref (real_fcnname); - } - else - { - rtx data_access; - - emit_move_insn (reg0,force_reg (SImode, operands[1])); - data_access = gen_rtx_MEM (SImode, operands[1]); - RTX_UNCHANGING_P (data_access) = 1; - operands[1] = copy_to_reg (data_access); - } - - call_insn = emit_call_insn (gen_call_value_internal (operands[0], - operands[1], - operands[2])); - use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), reg0); - DONE; -}") - -(define_insn "call_value_internal" - [(set (match_operand 0 "" "=fg") - (call (mem:SI (match_operand:SI 1 "register_operand" "b")) - (match_operand 2 "" "g"))) - (clobber (reg:SI 15))] - "" - "balr%# r15,%1" - [(set_attr "length" "2") - (set_attr "type" "call")]) - -(define_insn "" - [(set (match_operand 0 "" "=fg") - (call (mem:SI (match_operand:SI 1 "romp_symbolic_operand" "i")) - (match_operand 2 "" "g"))) - (clobber (reg:SI 15))] - "GET_CODE (operands[1]) == SYMBOL_REF" - "bali%# r15,%1" - [(set_attr "type" "call")]) - -;; Call subroutine returning any type. - -(define_expand "untyped_call" - [(parallel [(call (match_operand 0 "" "") - (const_int 0)) - (match_operand 1 "" "") - (match_operand 2 "" "")])] - "" - " -{ - int i; - - emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); - - for (i = 0; i < XVECLEN (operands[2], 0); i++) - { - rtx set = XVECEXP (operands[2], 0, i); - emit_move_insn (SET_DEST (set), SET_SRC (set)); - } - - /* The optimizer does not know that the call sets the function value - registers we stored in the result block. We avoid problems by - claiming that all hard registers are used and clobbered at this - point. */ - emit_insn (gen_blockage ()); - - DONE; -}") - -;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and -;; all of memory. This blocks insns from being moved across this point. - -(define_insn "blockage" - [(unspec_volatile [(const_int 0)] 0)] - "" - "") - -;; No operation insn. -(define_insn "nop" - [(const_int 0)] - "" - "nopr r0" - [(set_attr "type" "address") - (set_attr "length" "2") - (set_attr "cc" "none")]) - -;; Here are the floating-point operations. -;; -;; Start by providing DEFINE_EXPAND for each operation. -;; The insns will be handled with MATCH_OPERATOR; the methodology will be -;; discussed below. - -;; First the conversion operations. - -(define_expand "truncdfsf2" - [(parallel [(set (match_operand:SF 0 "general_operand" "") - (float_truncate:SF (match_operand:DF 1 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "extendsfdf2" - [(parallel [(set (match_operand:DF 0 "general_operand" "") - (float_extend:DF (match_operand:SF 1 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "floatsisf2" - [(parallel [(set (match_operand:SF 0 "general_operand" "") - (float:SF (match_operand:SI 1 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "floatsidf2" - [(parallel [(set (match_operand:DF 0 "general_operand" "") - (float:DF (match_operand:SI 1 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "fix_truncsfsi2" - [(parallel [(set (match_operand:SI 0 "general_operand" "") - (fix:SI (match_operand:SF 1 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "fix_truncdfsi2" - [(parallel [(set (match_operand:SI 0 "general_operand" "") - (fix:SI (match_operand:DF 1 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -;; Now the binary operations. - -(define_expand "addsf3" - [(parallel [(set (match_operand:SF 0 "general_operand" "") - (plus:SF (match_operand:SF 1 "general_operand" "") - (match_operand:SF 2 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "adddf3" - [(parallel [(set (match_operand:DF 0 "general_operand" "") - (plus:DF (match_operand:DF 1 "general_operand" "") - (match_operand:DF 2 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "subsf3" - [(parallel [(set (match_operand:SF 0 "general_operand" "") - (minus:SF (match_operand:SF 1 "general_operand" "") - (match_operand:SF 2 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "subdf3" - [(parallel [(set (match_operand:DF 0 "general_operand" "") - (minus:DF (match_operand:DF 1 "general_operand" "") - (match_operand:DF 2 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "mulsf3" - [(parallel [(set (match_operand:SF 0 "general_operand" "") - (mult:SF (match_operand:SF 1 "general_operand" "") - (match_operand:SF 2 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "muldf3" - [(parallel [(set (match_operand:DF 0 "general_operand" "") - (mult:DF (match_operand:DF 1 "general_operand" "") - (match_operand:DF 2 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "divsf3" - [(parallel [(set (match_operand:SF 0 "general_operand" "") - (div:SF (match_operand:SF 1 "general_operand" "") - (match_operand:SF 2 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "divdf3" - [(parallel [(set (match_operand:DF 0 "general_operand" "") - (div:DF (match_operand:DF 1 "general_operand" "") - (match_operand:DF 2 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -;; Unary floating-point operations. -;; -;; Negations can be done without floating-point, since this is IEEE. -;; But we cannot do this if an operand is a hard FP register, since -;; the SUBREG we create would not be valid. -(define_expand "negsf2" - [(set (match_operand:SF 0 "register_operand" "") - (neg:SF (match_operand:SF 1 "register_operand" "")))] - "" - " -{ - if (! (GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER - && FP_REGNO_P (REGNO (operands[0]))) - && ! (GET_CODE (operands[1]) == REG - && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER - && FP_REGNO_P (REGNO (operands[1])))) - { - rtx result; - rtx target = operand_subword (operands[0], 0, 1, SFmode); - - result = expand_binop (SImode, xor_optab, - operand_subword_force (operands[1], 0, SFmode), - GEN_INT (0x80000000), target, 0, OPTAB_WIDEN); - if (result == 0) - abort (); - - if (result != target) - emit_move_insn (result, target); - - /* Make a place for REG_EQUAL. */ - emit_move_insn (operands[0], operands[0]); - DONE; - } -}") - -(define_expand "negdf2" - [(set (match_operand:DF 0 "register_operand" "") - (neg:DF (match_operand:DF 1 "register_operand" "")))] - "" - " -{ - if (! (GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER - && FP_REGNO_P (REGNO (operands[0]))) - && ! (GET_CODE (operands[1]) == REG - && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER - && FP_REGNO_P (REGNO (operands[1])))) - { - rtx result; - rtx target = operand_subword (operands[0], 0, 1, DFmode); - rtx insns; - - start_sequence (); - result = expand_binop (SImode, xor_optab, - operand_subword_force (operands[1], 0, DFmode), - GEN_INT (0x80000000), target, 0, OPTAB_WIDEN); - if (result == 0) - abort (); - - if (result != target) - emit_move_insn (result, target); - - emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), - operand_subword_force (operands[1], 1, DFmode)); - - insns = get_insns (); - end_sequence (); - - emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); - DONE; - } -}") - -(define_expand "abssf2" - [(parallel [(set (match_operand:SF 0 "general_operand" "") - (abs:SF (match_operand:SF 1 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "absdf2" - [(parallel [(set (match_operand:DF 0 "general_operand" "") - (abs:DF (match_operand:DF 1 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -;; Any floating-point operation can be either SFmode or DFmode, and each -;; operand (including the output) can be either a normal operand or a -;; conversion from a normal operand. -;; -;; We use MATCH_OPERATOR to match a floating-point binary or unary operator -;; and input and output conversions. So we need 2^N patterns for each type -;; of operation, where N is the number of operands, including the output. -;; There are thus a total of 14 patterns, 8 for binary operations, 4 for -;; unary operations and two for conversion/move operations (only one -;; operand can have a conversion for move operations). In addition, we have -;; to be careful that a floating-point reload register doesn't get allocated -;; for an integer. We take care of this for inputs with PREFERRED_RELOAD_CLASS -;; but need to have two different constraints for outputs. This means that -;; we have to duplicate each pattern where the output could be an integer. -;; This adds another 7 patterns, for a total of 21. - -;; Start with conversion operations (moves are done above). - -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=g") - (match_operator 1 "float_conversion" - [(match_operand 2 "general_operand" "frg")])) - (clobber (match_operand:SI 3 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))] - "" - "* -{ return output_fpop (SET, operands[0], operands[2], 0, insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_conversion" - [(match_operand 2 "general_operand" "frg")])) - (clobber (match_operand:SI 3 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))] - "" - "* -{ return output_fpop (SET, operands[0], operands[2], 0, insn); -}" - [(set_attr "type" "fp")]) - -;; Next, binary floating-point operations. - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_binary" - [(match_operand 2 "general_operand" "frg") - (match_operand 3 "general_operand" "frg")])) - (clobber (match_operand:SI 4 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[1]), operands[2], operands[3])" - "* -{ return output_fpop (GET_CODE (operands[1]), operands[0], - operands[2], operands[3], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_binary" - [(match_operand 2 "general_operand" "frg") - (match_operator 3 "float_conversion" - [(match_operand 4 "general_operand" "frg")])])) - (clobber (match_operand:SI 5 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[1]), operands[2], operands[4])" - "* -{ return output_fpop (GET_CODE (operands[1]), operands[0], - operands[2], operands[4], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_binary" - [(match_operator 2 "float_conversion" - [(match_operand 3 "general_operand" "frg")]) - (match_operand 4 "general_operand" "frg")])) - (clobber (match_operand:SI 5 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[1]), operands[3], operands[4])" - "* -{ return output_fpop (GET_CODE (operands[1]), operands[0], - operands[3], operands[4], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_binary" - [(match_operator 2 "float_conversion" - [(match_operand 3 "general_operand" "frg")]) - (match_operator 4 "float_conversion" - [(match_operand 5 "general_operand" "frg")])])) - (clobber (match_operand:SI 6 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[1]), operands[3], operands[5])" - "* -{ return output_fpop (GET_CODE (operands[1]), operands[0], - operands[3], operands[5], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=g") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_binary" - [(match_operand 3 "general_operand" "frg") - (match_operand 4 "general_operand" "frg")])])) - (clobber (match_operand:SI 5 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[3], operands[4])" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], - operands[3], operands[4], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_binary" - [(match_operand 3 "general_operand" "frg") - (match_operand 4 "general_operand" "frg")])])) - (clobber (match_operand:SI 5 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[3], operands[4])" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], - operands[3], operands[4], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=g") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_binary" - [(match_operand 3 "general_operand" "frg") - (match_operator 4 "float_conversion" - [(match_operand 5 "general_operand" "frg")])])])) - (clobber (match_operand:SI 6 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[3], operands[4])" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], - operands[3], operands[5], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_binary" - [(match_operand 3 "general_operand" "frg") - (match_operator 4 "float_conversion" - [(match_operand 5 "general_operand" "frg")])])])) - (clobber (match_operand:SI 6 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[3], operands[4])" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], - operands[3], operands[5], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=g") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_binary" - [(match_operator 3 "float_conversion" - [(match_operand 4 "general_operand" "frg")]) - (match_operand 5 "general_operand" "frg")])])) - (clobber (match_operand:SI 6 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[4], operands[5])" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], - operands[4], operands[5], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_binary" - [(match_operator 3 "float_conversion" - [(match_operand 4 "general_operand" "frg")]) - (match_operand 5 "general_operand" "frg")])])) - (clobber (match_operand:SI 6 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[4], operands[5])" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], - operands[4], operands[5], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=g") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_binary" - [(match_operator 3 "float_conversion" - [(match_operand 4 "general_operand" "frg")]) - (match_operator 5 "float_conversion" - [(match_operand 6 "general_operand" "frg")])])])) - (clobber (match_operand:SI 7 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 8 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[4], operands[6])" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], - operands[4], operands[6], insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_binary" - [(match_operator 3 "float_conversion" - [(match_operand 4 "general_operand" "frg")]) - (match_operator 5 "float_conversion" - [(match_operand 6 "general_operand" "frg")])])])) - (clobber (match_operand:SI 7 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 8 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[4], operands[6])" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], - operands[4], operands[6], insn); -}" - [(set_attr "type" "fp")]) - -;; Unary floating-point operations. - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_unary" - [(match_operand 2 "general_operand" "frg")])) - (clobber (match_operand:SI 3 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[1]), operands[2], 0)" - "* -{ return output_fpop (GET_CODE (operands[1]), operands[0], operands[2], - 0, insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_unary" - [(match_operator 2 "float_conversion" - [(match_operand 3 "general_operand" "frg")])])) - (clobber (match_operand:SI 4 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[1]), operands[3], 0)" - "* -{ return output_fpop (GET_CODE (operands[1]), operands[0], operands[3], - 0, insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=g") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_unary" - [(match_operand 3 "general_operand" "frg")])])) - (clobber (match_operand:SI 4 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[3], 0)" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[3], - 0, insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_unary" - [(match_operand 3 "general_operand" "frg")])])) - (clobber (match_operand:SI 4 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[3], 0)" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[3], - 0, insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand:SI 0 "general_operand" "=g") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_unary" - [(match_operator 3 "float_conversion" - [(match_operand 4 "general_operand" "frg")])])])) - (clobber (match_operand:SI 5 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[4], 0)" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[4], - 0, insn); -}" - [(set_attr "type" "fp")]) - -(define_insn "" - [(set (match_operand 0 "general_operand" "=frg") - (match_operator 1 "float_conversion" - [(match_operator 2 "float_unary" - [(match_operator 3 "float_conversion" - [(match_operand 4 "general_operand" "frg")])])])) - (clobber (match_operand:SI 5 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))] - "check_precision (GET_MODE (operands[2]), operands[4], 0)" - "* -{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[4], - 0, insn); -}" - [(set_attr "type" "fp")]) - -;; Compare insns are next. Note that the ROMP has two types of compares, -;; signed & unsigned, and one type of branch. Use the routine -;; `next_insn_tests_no_unsigned' to see which type to use. -(define_expand "tstsi" - [(set (cc0) - (match_operand:SI 0 "register_operand" "r"))] - "" - "") - -(define_expand "cmpsi" - [(set (cc0) - (compare (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "reg_or_cint_operand" "")))] - "" - "") - -;; Signed compare, `test' first. - -(define_insn "" - [(set (cc0) - (match_operand:SI 0 "register_operand" "r"))] - "next_insn_tests_no_unsigned (insn)" - "cis %0,0" - [(set_attr "length" "2") - (set_attr "type" "compare")]) - -(define_insn "" - [(set (cc0) (match_operand:SI 0 "register_operand" "r,r,r")) - (set (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "=0,r,Q") - (match_dup 0))] - "next_insn_tests_no_unsigned (insn)" - "@ - cis %1,0 - nilo %1,%0,65535 - st%M1 %0,%1\;cis %0,0" - [(set_attr "type" "compare,compare,store") - (set_attr "length" "2,4,6") - (set_attr "cc" "compare")]) - -(define_insn "" - [(set (cc0) - (compare (match_operand:SI 0 "register_operand" "r,r,r") - (match_operand:SI 1 "reg_or_cint_operand" "I,K,r")))] - "next_insn_tests_no_unsigned (insn)" - "@ - cis %0,%1 - cil %0,%1 - c %0,%1" - [(set_attr "length" "2,4,2") - (set_attr "type" "compare")]) - -;; Unsigned comparisons, `test' first, again. -(define_insn "" - [(set (cc0) - (match_operand:SI 0 "register_operand" "r"))] - "! next_insn_tests_no_unsigned (insn)" - "clil %0,0" - [(set_attr "type" "compare")]) - -(define_insn "" - [(set (cc0) - (compare (match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "reg_or_cint_operand" "K,r")))] - "! next_insn_tests_no_unsigned (insn)" - "@ - clil %0,%1 - cl %0,%1" - [(set_attr "length" "4,2") - (set_attr "type" "compare")]) - -;; Bit test insn. Many cases are converted into this by combine. This -;; uses the ROMP test bit. - -(define_insn "" - [(set (cc0) - (zero_extract (match_operand:SI 0 "register_operand" "r,r") - (const_int 1) - (match_operand:SI 1 "reg_or_any_cint_operand" "r,n")))] - "next_insn_tests_no_inequality (insn)" - "@ - mttb %0,%1 - mttbi%t1 %0,%S1" - [(set_attr "length" "2") - (set_attr "type" "compare") - (set_attr "cc" "tbit")]) - -;; Floating-point comparisons. There are two, equality and order. -;; The difference will be that a trap for NaN will be given on the orderr -;; comparisons only. - -(define_expand "cmpsf" - [(parallel [(set (cc0) (compare (match_operand:SF 0 "general_operand" "") - (match_operand:SF 1 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "cmpdf" - [(parallel [(set (cc0) (compare (match_operand:DF 0 "general_operand" "") - (match_operand:DF 1 "general_operand" ""))) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "tstsf" - [(parallel [(set (cc0) (match_operand:SF 0 "general_operand" "")) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -(define_expand "tstdf" - [(parallel [(set (cc0) (match_operand:DF 0 "general_operand" "")) - (clobber (reg:SI 0)) - (clobber (reg:SI 15))])] - "" - "") - -;; There are four cases for compare and two for test. These correspond -;; to each input having a floating-point conversion or not. - -(define_insn "" - [(set (cc0) (compare (match_operand 0 "general_operand" "frg") - (match_operand 1 "general_operand" "frg"))) - (clobber (match_operand:SI 2 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 3 "reg_15_operand" "=&t"))] - "GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode" - "* -{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE, - operands[0], operands[1], 0, insn); -}" - [(set_attr "type" "fp") - (set_attr "cc" "compare")]) - -(define_insn "" - [(set (cc0) (compare (match_operand 0 "general_operand" "frg") - (match_operator 1 "float_conversion" - [(match_operand 2 "general_operand" "frg")]))) - (clobber (match_operand:SI 3 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))] - "" - "* -{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE, - operands[0], operands[2], 0, insn); -}" - [(set_attr "type" "fp") - (set_attr "cc" "compare")]) - -(define_insn "" - [(set (cc0) (compare (match_operator 0 "float_conversion" - [(match_operand 1 "general_operand" "frg")]) - (match_operand 2 "general_operand" "frg"))) - (clobber (match_operand:SI 3 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))] - "" - "* -{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE, - operands[1], operands[2], 0, insn); -}" - [(set_attr "type" "fp") - (set_attr "cc" "compare")]) - -(define_insn "" - [(set (cc0) (compare (match_operator 0 "float_conversion" - [(match_operand 1 "general_operand" "frg")]) - (match_operator 2 "float_conversion" - [(match_operand 3 "general_operand" "frg")]))) - (clobber (match_operand:SI 4 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))] - "" - "* -{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE, - operands[1], operands[3], 0, insn); -}" - [(set_attr "type" "fp") - (set_attr "cc" "compare")]) - -(define_insn "" - [(set (cc0) (match_operand 0 "general_operand" "frg")) - (clobber (match_operand:SI 1 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 2 "reg_15_operand" "=&t"))] - "GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode" - "* -{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE, - operands[0], CONST0_RTX (GET_MODE (operands[0])), - 0, insn); -}" - [(set_attr "type" "fp") - (set_attr "cc" "compare")]) - -(define_insn "" - [(set (cc0) (match_operator 0 "float_conversion" - [(match_operand 1 "general_operand" "frg")])) - (clobber (match_operand:SI 2 "reg_0_operand" "=&z")) - (clobber (match_operand:SI 3 "reg_15_operand" "=&t"))] - "" - "* -{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE, - operands[1], CONST0_RTX (GET_MODE (operands[1])), - 0, insn); -}" - [(set_attr "type" "fp") - (set_attr "cc" "compare")]) - -;; Branch insns. Unsigned vs. signed have already -;; been taken care of. The only insns that need to be concerned about the -;; test bit are beq and bne because the rest are either always true, -;; always false, or converted to EQ or NE. - -;; For conditional branches, we use `define_expand' and just have two patterns -;; that match them. Operand printing does most of the work. - -(define_expand "beq" - [(set (pc) - (if_then_else (eq (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bne" - [(set (pc) - (if_then_else (ne (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bgt" - [(set (pc) - (if_then_else (gt (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bgtu" - [(set (pc) - (if_then_else (gtu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "blt" - [(set (pc) - (if_then_else (lt (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bltu" - [(set (pc) - (if_then_else (ltu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bge" - [(set (pc) - (if_then_else (ge (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bgeu" - [(set (pc) - (if_then_else (geu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "ble" - [(set (pc) - (if_then_else (le (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -(define_expand "bleu" - [(set (pc) - (if_then_else (leu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "") - -;; Define both directions of branch and return. - -(define_insn "" - [(set (pc) - (if_then_else (match_operator 1 "comparison_operator" - [(cc0) (const_int 0)]) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* -{ - if (restore_compare_p (operands[1])) - return 0; - else if (get_attr_length (insn) == 2) - return \"j%j1 %l0\"; - else - return \"b%j1%# %l0\"; -}" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else (match_operator 0 "comparison_operator" - [(cc0) (const_int 0)]) - (return) - (pc)))] - "null_epilogue ()" - "* -{ - if (restore_compare_p (operands[0])) - return 0; - else - return \"b%j0r%# r15\"; -}" - [(set_attr "type" "return")]) - -(define_insn "" - [(set (pc) - (if_then_else (match_operator 1 "comparison_operator" - [(cc0) (const_int 0)]) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* -{ - if (restore_compare_p (operands[1])) - return 0; - else if (get_attr_length (insn) == 2) - return \"j%J1 %l0\"; - else - return \"b%J1%# %l0\"; -}" - [(set_attr "type" "branch")]) - -(define_insn "" - [(set (pc) - (if_then_else (match_operator 0 "comparison_operator" - [(cc0) (const_int 0)]) - (pc) - (return)))] - "null_epilogue ()" - "* -{ - if (restore_compare_p (operands[0])) - return 0; - else - return \"b%J0r%# r15\"; -}" - [(set_attr "type" "return")]) - -;; Unconditional branch and return. - -(define_insn "jump" - [(set (pc) - (label_ref (match_operand 0 "" "")))] - "" - "* -{ - if (get_attr_length (insn) == 2) - return \"j %l0\"; - else - return \"b%# %l0\"; -}" - [(set_attr "type" "branch")]) - -(define_insn "return" - [(return)] - "null_epilogue ()" - "br%# r15" - [(set_attr "type" "return")]) - -(define_insn "indirect_jump" - [(set (pc) (match_operand:SI 0 "register_operand" "r"))] - "" - "br%# %0" - [(set_attr "type" "ibranch")]) - -;; Table jump for switch statements: -(define_insn "tablejump" - [(set (pc) - (match_operand:SI 0 "register_operand" "r")) - (use (label_ref (match_operand 1 "" "")))] - "" - "br%# %0" - [(set_attr "type" "ibranch")]) diff --git a/gcc/config/rs6000/aix31.h b/gcc/config/rs6000/aix31.h deleted file mode 100644 index 211fcd32124..00000000000 --- a/gcc/config/rs6000/aix31.h +++ /dev/null @@ -1,86 +0,0 @@ -/* Definitions of target machine for GNU compiler, - for IBM RS/6000 running AIX version 3.1. - Copyright (C) 1993,1997, 2000, 2001, 2003 Free Software Foundation, Inc. - Contributed by Richard Kenner (kenner@nyu.edu) - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 2, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, - MA 02111-1307, USA. */ - -/* Output something to declare an external symbol to the assembler. Most - assemblers don't need this. - - If we haven't already, add "[RW]" (or "[DS]" for a function) to the - name. Normally we write this out along with the name. In the few cases - where we can't, it gets stripped off. */ - -#undef ASM_OUTPUT_EXTERNAL -#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ -{ rtx _symref = XEXP (DECL_RTL (DECL), 0); \ - if ((TREE_CODE (DECL) == VAR_DECL \ - || TREE_CODE (DECL) == FUNCTION_DECL) \ - && (NAME)[strlen (NAME) - 1] != ']') \ - { \ - XSTR (_symref, 0) = concat (XSTR (_symref, 0), \ - (TREE_CODE (DECL) == FUNCTION_DECL \ - ? "[DS]" : "[RW]"), \ - NULL); \ - } \ - fputs ("\t.extern ", FILE); \ - assemble_name (FILE, XSTR (_symref, 0)); \ - if (TREE_CODE (DECL) == FUNCTION_DECL) \ - { \ - fputs ("\n\t.extern .", FILE); \ - RS6000_OUTPUT_BASENAME (FILE, XSTR (_symref, 0)); \ - } \ - putc ('\n', FILE); \ -} - -/* Similar, but for libcall. We only have to worry about the function name, - not that of the descriptor. */ - -#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \ -{ fputs ("\t.extern .", FILE); \ - assemble_name (FILE, XSTR (FUN, 0)); \ - putc ('\n', FILE); \ -} - -/* AIX 3.2 defined _AIX32, but older versions do not. */ -#undef TARGET_OS_CPP_BUILTINS -#define TARGET_OS_CPP_BUILTINS() \ - do \ - { \ - builtin_define ("_IBMR2"); \ - builtin_define ("_AIX"); \ - builtin_assert ("system=unix"); \ - builtin_assert ("system=aix"); \ - builtin_assert ("cpu=rs6000"); \ - builtin_assert ("machine=rs6000"); \ - } \ - while (0) - -/* AIX 3.1 uses bit 15 in CROR as the magic nop. */ -#undef RS6000_CALL_GLUE -#define RS6000_CALL_GLUE "cror 15,15,15" - -/* AIX 3.1 does not prepend underscores to itrunc, uitrunc, or mcount. */ -#undef RS6000_ITRUNC -#define RS6000_ITRUNC "itrunc" -#undef RS6000_UITRUNC -#define RS6000_UITRUNC "uitrunc" -#undef RS6000_MCOUNT -#define RS6000_MCOUNT ".mcount" - diff --git a/gcc/config/rs6000/aix3newas.h b/gcc/config/rs6000/aix3newas.h deleted file mode 100644 index 549e088fb8d..00000000000 --- a/gcc/config/rs6000/aix3newas.h +++ /dev/null @@ -1,59 +0,0 @@ -/* Definitions of target machine for GNU compiler, - for IBM RS/6000 POWER running AIX version 3.x with the fixed assembler. - Copyright (C) 1995, 1996, 2000, 2001, 2003 Free Software Foundation, Inc. - Contributed by Jason Merrill (jason@cygnus.com). - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 2, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, - MA 02111-1307, USA. */ - -/* Tell the assembler to assume that all undefined names are external. */ - -#undef ASM_SPEC -#define ASM_SPEC "-u %(asm_cpu)" - -#undef ASM_DEFAULT_SPEC -#define ASM_DEFAULT_SPEC "-mpwr" - -/* Define the options for the binder: Start text at 512, align all segments - to 512 bytes, and warn if there is text relocation. - - The -bhalt:4 option supposedly changes the level at which ld will abort, - but it also suppresses warnings about multiply defined symbols and is - used by the AIX cc command. So we use it here. - - -bnodelcsect undoes a poor choice of default relating to multiply-defined - csects. See AIX documentation for more information about this. - - -bM:SRE tells the linker that the output file is Shared REusable. Note - that to actually build a shared library you will also need to specify an - export list with the -Wl,-bE option. - - If -mcpu=common, export the architecture dependent multiply/divide routines - as per README.RS6000. */ - -#undef LINK_SPEC -#ifndef CROSS_COMPILE -#define LINK_SPEC "-T512 -H512 %{!r:-btextro} -bhalt:4 -bnodelcsect\ - %{static:-bnso -bI:/lib/syscalls.exp} \ - %{mcpu=common: milli.exp%s} \ - %{!shared:%{g*:-bexport:/usr/lib/libg.exp}} %{shared:-bM:SRE}" -#else -#define LINK_SPEC "-T512 -H512 %{!r:-btextro} -bhalt:4 -bnodelcsect\ - %{static:-bnso} \ - %{mcpu=common: milli.exp%s} \ - %{shared:-bM:SRE}" -#endif diff --git a/gcc/config/rs6000/mach.h b/gcc/config/rs6000/mach.h deleted file mode 100644 index 6cd03050144..00000000000 --- a/gcc/config/rs6000/mach.h +++ /dev/null @@ -1,54 +0,0 @@ -/* Definitions of target machine for GNU compiler, - for IBM RS/6000 running MACH. - Copyright (C) 1992, 1999, 2003 Free Software Foundation, Inc. - Contributed by Richard Kenner (kenner@nyu.edu) - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 2, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, - MA 02111-1307, USA. */ - -#define TARGET_AIX 0 - -/* Print subsidiary information on the compiler version in use. */ -#define TARGET_VERSION fprintf (stderr, " (Mach-RS/6000)"); - -/* We don't define AIX under MACH; instead we define `unix'. */ -#undef TARGET_OS_CPP_BUILTINS -#define TARGET_OS_CPP_BUILTINS() \ - do \ - { \ - builtin_define_std ("rios"); \ - builtin_define ("_IBMR2"); \ - builtin_define_std ("unix"); \ - builtin_assert ("system=unix"); \ - builtin_assert ("system=mach"); \ - builtin_assert ("cpu=rs6000"); \ - builtin_assert ("machine=rs6000"); \ - } \ - while (0) - -/* Define different binder options for MACH. */ -#undef LINK_SPEC -#define LINK_SPEC \ - "-T0x10000000 -D0x20000000 -K %{!nostdlib:%{!r*:%{!e*:-e __start}}} \ - -bnoso -berrmsg -btextro -bhalt:4 -bnodelcsect" - -/* MACH doesn't have atexit. */ -#define NEED_ATEXIT - -/* Don't default to pcc-struct-return, because gcc is the only compiler, and - we want to retain compatibility with older gcc versions. */ -#define DEFAULT_PCC_STRUCT_RETURN 0 diff --git a/gcc/config/sparc/bsd.h b/gcc/config/sparc/bsd.h deleted file mode 100644 index 41f83081399..00000000000 --- a/gcc/config/sparc/bsd.h +++ /dev/null @@ -1,5 +0,0 @@ -#undef LIB_SPEC -#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:gcrt0.o%s}%{!p:crt0.o%s}}" diff --git a/gcc/config/sparc/hal.h b/gcc/config/sparc/hal.h deleted file mode 100644 index 0222b819e0e..00000000000 --- a/gcc/config/sparc/hal.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Definitions of target machine for GNU compiler, for HAL - SPARC running Solaris 2 HALOS - Copyright 1998 Free Software Foundation, Inc. - Contributed by Carol LePage (carolo@hal.com) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* Need different command line for assembler */ - -#undef ASM_SPEC -#define ASM_SPEC \ - "%{V} %{v:%{!V:-V}} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -e1 \ - %{fpic:-K PIC} %{fPIC:-K PIC}" - -/* Need DWARF for debuggers. */ - -#undef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG diff --git a/gcc/config/sparc/linux-aout.h b/gcc/config/sparc/linux-aout.h deleted file mode 100644 index 70b2c794b7d..00000000000 --- a/gcc/config/sparc/linux-aout.h +++ /dev/null @@ -1,96 +0,0 @@ -/* Definitions for SPARC running Linux-based GNU systems with a.out. - Copyright (C) 1996, 1997, 1999, 2002 Free Software Foundation, Inc. - Contributed by Eddie C. Dost (ecd@skynet.be) - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* Don't assume anything about the header files. */ -#define NO_IMPLICIT_EXTERN_C - -/* GNU/Linux uses ctype from glibc.a. I am not sure how complete it is. - For now, we play safe. It may change later. */ - -#if 0 -#undef MULTIBYTE_CHARS -#define MULTIBYTE_CHARS 1 -#endif - -/* We need that too. */ -#define HANDLE_SYSV_PRAGMA 1 - -#undef MD_EXEC_PREFIX -#undef MD_STARTFILE_PREFIX - -/* Output at beginning of assembler file. */ -/* The .file command should always begin the output. */ -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) output_file_directive (FILE, main_input_filename) - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "%{pg:gcrt0.o%s} %{!pg:%{p:gcrt0.o%s} %{!p:crt0.o%s}} %{static:-static}" - -#undef TARGET_VERSION -#define TARGET_VERSION fprintf (stderr, " (sparc GNU/Linux with a.out)"); - -#undef SIZE_TYPE -#define SIZE_TYPE "unsigned int" - -#undef PTRDIFF_TYPE -#define PTRDIFF_TYPE "int" - -#undef WCHAR_TYPE -#define WCHAR_TYPE "int" - -#undef WCHAR_TYPE_SIZE -#define WCHAR_TYPE_SIZE 32 - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dunix -Dsparc -D__gnu_linux__ -Dlinux -Asystem=unix -Asystem=posix" - -#undef CPP_SUBTARGET_SPEC -#define CPP_SUBTARGET_SPEC \ -"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}" - -/* Don't default to pcc-struct-return, because gcc is the only compiler, - and we want to retain compatibility with older gcc versions. */ -#undef DEFAULT_PCC_STRUCT_RETURN -#define DEFAULT_PCC_STRUCT_RETURN 0 - -#undef LIB_SPEC - -#if 1 -/* We no longer link with libc_p.a or libg.a by default. If you - want to profile or debug the GNU/Linux C library, please add - -lc_p or -ggdb to LDFLAGS at the link time, respectively. */ -#define LIB_SPEC \ -"%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}" -#else -#define LIB_SPEC \ -"%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \ - %{!p:%{!pg:%{!g*:-lc} %{g*:-lg -static}}}" -#endif - -#undef LINK_SPEC -#define LINK_SPEC "-m sparclinux" - -/* The sun bundled assembler doesn't accept -Yd, (and neither does gas). - It's safe to pass -s always, even if -g is not used. */ -#undef ASM_SPEC -#define ASM_SPEC \ - "%{V} %{v:%{!V:-V}} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s %{fpic:-K PIC} %{fPIC:-K PIC}" - diff --git a/gcc/config/sparc/lynx-ng.h b/gcc/config/sparc/lynx-ng.h deleted file mode 100644 index b1a6ef5f8f3..00000000000 --- a/gcc/config/sparc/lynx-ng.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Definitions for SPARC running LynxOS, using Lynx's old as and ld. - Copyright (C) 1993, 1995 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* ??? Must redefine to get sparclite and v8 defines. Can this be done - differently? */ - -#undef CPP_SPEC -#define CPP_SPEC "%{mthreads:-D_MULTITHREADED} \ - %{mposix:-D_POSIX_SOURCE} \ - %{msystem-v:-I/usr/include_v} \ - %(cpp_cpu)" - -/* Names to predefine in the preprocessor for this target machine. */ - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dunix -Dsparc -DLynx -DIBITS32 -Asystem=unix -Asystem=lynx -Acpu=sparc -Amachine=sparc" - -/* Provide required defaults for linker switches. */ - -#undef LINK_SPEC -#define LINK_SPEC "-e __main -T 0 %{msystem-v:-V} %{mcoff:-k}" diff --git a/gcc/config/sparc/lynx.h b/gcc/config/sparc/lynx.h deleted file mode 100644 index 805f65f34e3..00000000000 --- a/gcc/config/sparc/lynx.h +++ /dev/null @@ -1,47 +0,0 @@ -/* Definitions for SPARC running LynxOS. - Copyright (C) 1993, 1995, 1996, 2000 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#undef ASM_OUTPUT_IDENT - -#define BSS_SECTION_ASM_OP "\t.section\t\".bss\"" - -/* ??? Must redefine to get sparclite and v8 defines. Can this be done - differently? */ - -#undef CPP_SPEC -#define CPP_SPEC "%{mthreads:-D_MULTITHREADED} \ - %{mposix:-D_POSIX_SOURCE} \ - %{msystem-v:-I/usr/include_v} \ - %(cpp_cpu)" - -/* Names to predefine in the preprocessor for this target machine. */ - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dunix -Dsparc -DSPARC -DLynx -DLYNX -DIBITS32 -Asystem=unix -Asystem=lynx -Acpu=sparc -Amachine=sparc" - -#undef LINK_SPEC - -/* SPARC version of libc.a has references to libm.a (printf calls pow for - instance), so we must always link both. */ - -#undef LIB_SPEC -#define LIB_SPEC "%{mthreads:-L/lib/thread/} \ - %{msystem-v:-lc_v -lm_v -lc_v} \ - %{!msystem-v:%{mposix:-lc_p} -lc -lm -lc}" diff --git a/gcc/config/sparc/netbsd.h b/gcc/config/sparc/netbsd.h deleted file mode 100644 index 284e288d5e4..00000000000 --- a/gcc/config/sparc/netbsd.h +++ /dev/null @@ -1,49 +0,0 @@ -#define TARGET_OS_CPP_BUILTINS() \ - do \ - { \ - NETBSD_OS_CPP_BUILTINS_AOUT(); \ - builtin_define_std ("sparc"); \ - builtin_assert ("cpu=sparc"); \ - builtin_assert ("machine=sparc"); \ - } \ - while (0) - -/* Make sure this is undefined. */ -#undef CPP_PREDEFINES - -/* What extra spec entries do we need? */ -#undef SUBTARGET_EXTRA_SPECS -#define SUBTARGET_EXTRA_SPECS \ - { "netbsd_cpp_spec", NETBSD_CPP_SPEC }, - -#undef CPP_SPEC -#define CPP_SPEC "%(cpp_cpu) %(netbsd_cpp_spec)" - -/* Make gcc agree with <machine/ansi.h> */ - -#undef SIZE_TYPE -#define SIZE_TYPE "unsigned int" - -#undef PTRDIFF_TYPE -#define PTRDIFF_TYPE "int" - -/* This is BSD, so it wants DBX format. */ - -#define DBX_DEBUGGING_INFO 1 - -/* This is the char to use for continuation (in case we need to turn - continuation back on). */ - -#define DBX_CONTIN_CHAR '?' - -/* Don't default to pcc-struct-return, because gcc is the only compiler, and - we want to retain compatibility with older gcc versions. */ -#undef DEFAULT_PCC_STRUCT_RETURN -#define DEFAULT_PCC_STRUCT_RETURN 0 - -/* Until they use ELF or something that handles dwarf2 unwinds - and initialization stuff better. */ -#define DWARF2_UNWIND_INFO 0 - -/* Attempt to enable execute permissions on the stack. */ -#define TRANSFER_FROM_TRAMPOLINE NETBSD_ENABLE_EXECUTE_STACK diff --git a/gcc/config/sparc/sp86x-aout.h b/gcc/config/sparc/sp86x-aout.h deleted file mode 100644 index 74607d35165..00000000000 --- a/gcc/config/sparc/sp86x-aout.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Definitions of target machine for GNU compiler, for sparclite 86x w/o FPU. - Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-D__sparc__ -D__sparclite86x__ -Acpu=sparc -Amachine=sparc" - -#undef TARGET_VERSION -#define TARGET_VERSION fprintf (stderr, " (sparclite 86x)"); - -/* Enable app-regs and epilogue options. Do not enable the fpu. */ - -#undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_APP_REGS - -#undef ASM_SPEC -#define ASM_SPEC "%{v:-v} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)" - -/* US Software GOFAST library support. */ -#undef INIT_SUBTARGET_OPTABS -#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS - -#undef LINK_SPEC -#define LINK_SPEC "%{v:-V}" - -#undef BYTES_BIG_ENDIAN -#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN_DATA) -#undef WORDS_BIG_ENDIAN -#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN_DATA) - -#define TARGET_LITTLE_ENDIAN_DATA (target_flags & MASK_LITTLE_ENDIAN) -#undef SUBTARGET_SWITCHES -#define SUBTARGET_SWITCHES \ - { "little-endian-data", MASK_LITTLE_ENDIAN, N_("Use little-endian byte order for data")}, diff --git a/gcc/config/sparc/splet.h b/gcc/config/sparc/splet.h deleted file mode 100644 index 0d3f0546abe..00000000000 --- a/gcc/config/sparc/splet.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Definitions of target machine for GNU compiler, for SPARClet. - Copyright (C) 1996, 1997, 2000 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_APP_REGS - -#define CPP_PREDEFINES "-Dsparc -Acpu=sparc -Amachine=sparc" - -#undef SUBTARGET_SWITCHES -#define SUBTARGET_SWITCHES \ -{"big-endian", -MASK_LITTLE_ENDIAN, N_("Generate code for big endian") }, \ -{"little-endian", MASK_LITTLE_ENDIAN, N_("Generate code for little endian") }, - -#undef ASM_SPEC -#define ASM_SPEC "%{mlittle-endian:-EL} %(asm_cpu)" - -/* Require the user to supply crt0.o. */ -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "" - -#undef LINK_SPEC -#define LINK_SPEC "%{mlittle-endian:-EL}" - -/* sparclet chips are bi-endian. */ -#undef BYTES_BIG_ENDIAN -#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) -#undef WORDS_BIG_ENDIAN -#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) diff --git a/gcc/config/sparc/sun4gas.h b/gcc/config/sparc/sun4gas.h deleted file mode 100644 index 7f4f7dbbc80..00000000000 --- a/gcc/config/sparc/sun4gas.h +++ /dev/null @@ -1,22 +0,0 @@ -/* Definitions of target machine for GNU compiler, for SunOS 4.x with gas - Copyright (C) 1997, 2000 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* defaults.h will define DWARF2_UNWIND_INFO for us. */ -#undef DWARF2_UNWIND_INFO diff --git a/gcc/config/sparc/sun4o3.h b/gcc/config/sparc/sun4o3.h deleted file mode 100644 index e79a4c8d329..00000000000 --- a/gcc/config/sparc/sun4o3.h +++ /dev/null @@ -1,11 +0,0 @@ -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -Asystem=unix -Asystem=bsd" - -/* Override the name of the mcount profiling function. */ - -#undef MCOUNT_FUNCTION -#define MCOUNT_FUNCTION "*.mcount" - -/* LINK_SPEC is needed only for SunOS 4. */ - -#undef LINK_SPEC diff --git a/gcc/config/sparc/sunos4.h b/gcc/config/sparc/sunos4.h deleted file mode 100644 index 513251ce836..00000000000 --- a/gcc/config/sparc/sunos4.h +++ /dev/null @@ -1,48 +0,0 @@ -/* Definitions of target machine for GNU compiler, for SunOS 4.x - Copyright (C) 1994, 1999 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#undef SUNOS4_SHARED_LIBRARIES -#define SUNOS4_SHARED_LIBRARIES 1 - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -Asystem=unix -Asystem=bsd" - -#define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}" - -/* Provide required defaults for linker -e and -d switches. */ - -#define LINK_SPEC \ - "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \ - %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}" - -/* Use N_BINCL stabs. */ - -#define DBX_USE_BINCL - -/* The Sun as doesn't like unaligned data. */ -#define DWARF2_UNWIND_INFO 0 - -/* SunOS has on_exit instead of atexit. */ -/* The man page says it returns int. */ -#ifdef IN_LIBGCC2 -extern int on_exit PARAMS ((void *, void *)); -#endif -#define ON_EXIT(FUNC) on_exit ((FUNC), 0) -#define NEED_ATEXIT diff --git a/gcc/config/sparc/t-chorus-elf b/gcc/config/sparc/t-chorus-elf deleted file mode 100644 index 5fc405bf627..00000000000 --- a/gcc/config/sparc/t-chorus-elf +++ /dev/null @@ -1,29 +0,0 @@ -LIB1ASMSRC = sparc/lb1spc.asm -LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 - -# We want fine grained libraries, so use the new code to build the -# floating point emulation libraries. -FPBIT = fp-bit.c -DPBIT = dp-bit.c - -dp-bit.c: $(srcdir)/config/fp-bit.c - cat $(srcdir)/config/fp-bit.c > dp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c - -# MULTILIB_OPTIONS should have msparclite too, but we'd have to make -# gas build... -MULTILIB_OPTIONS = -MULTILIB_DIRNAMES = -MULTILIB_MATCHES = - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib - -# Assemble startup files. -crti.o: $(srcdir)/config/sparc/sol2-ci.asm $(GCC_PASSES) - $(GCC_FOR_TARGET) -c -o crti.o -x assembler $(srcdir)/config/sparc/sol2-ci.asm -crtn.o: $(srcdir)/config/sparc/sol2-cn.asm $(GCC_PASSES) - $(GCC_FOR_TARGET) -c -o crtn.o -x assembler $(srcdir)/config/sparc/sol2-cn.asm diff --git a/gcc/config/sparc/t-halos b/gcc/config/sparc/t-halos deleted file mode 100644 index 0bd5496ac23..00000000000 --- a/gcc/config/sparc/t-halos +++ /dev/null @@ -1,2 +0,0 @@ -# For a native HALOS compile, we need to set -e1 for the assembler -AS=as -e1 diff --git a/gcc/config/sparc/t-sparcbare b/gcc/config/sparc/t-sparcbare deleted file mode 100644 index bac38de9b79..00000000000 --- a/gcc/config/sparc/t-sparcbare +++ /dev/null @@ -1,25 +0,0 @@ -# configuration file for a bare sparc cpu - -LIB1ASMSRC = sparc/lb1spc.asm -LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 - -# We want fine grained libraries, so use the new code to build the -# floating point emulation libraries. -FPBIT = fp-bit.c -DPBIT = dp-bit.c - -dp-bit.c: $(srcdir)/config/fp-bit.c - cat $(srcdir)/config/fp-bit.c > dp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c - -# MULTILIB_OPTIONS should have msparclite too, but we'd have to make -# gas build... -MULTILIB_OPTIONS = msoft-float mcpu=v8 -MULTILIB_DIRNAMES = soft v8 -MULTILIB_MATCHES = msoft-float=mno-fpu mcpu?v8=mv8 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib diff --git a/gcc/config/sparc/t-splet b/gcc/config/sparc/t-splet deleted file mode 100644 index 3334200dd64..00000000000 --- a/gcc/config/sparc/t-splet +++ /dev/null @@ -1,21 +0,0 @@ -# configuration file for a bare sparclet cpu, aout format files - -LIB1ASMSRC = sparc/lb1spc.asm -LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 - -# We want fine grained libraries, so use the new code to build the -# floating point emulation libraries. -FPBIT = fp-bit.c -DPBIT = dp-bit.c - -dp-bit.c: $(srcdir)/config/fp-bit.c - cat $(srcdir)/config/fp-bit.c > dp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c - -MULTILIB_OPTIONS = mlittle-endian mflat -MULTILIB_DIRNAMES = little flat -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib diff --git a/gcc/config/sparc/t-sunos41 b/gcc/config/sparc/t-sunos41 deleted file mode 100644 index 1056d931f8a..00000000000 --- a/gcc/config/sparc/t-sunos41 +++ /dev/null @@ -1,12 +0,0 @@ -# SunOS 4.1.* - -MULTILIB_OPTIONS = fpic/fPIC mcpu=v8 -MULTILIB_DIRNAMES = pic ucpic v8 -MULTILIB_MATCHES = mcpu?v8=mv8 - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib - -# The native linker doesn't handle linking -fpic code with -fPIC code. Ugh. -# We cope by building both variants of libgcc. -#TARGET_LIBGCC2_CFLAGS = -fPIC diff --git a/gcc/config/v850/rtems.h b/gcc/config/v850/rtems.h deleted file mode 100644 index c495214e0f7..00000000000 --- a/gcc/config/v850/rtems.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Definitions for rtems targeting a v850 using elf - Copyright (C) 1996, 1997, 2000, 2002 Free Software Foundation, Inc. - Contributed by Joel Sherrill (joel@OARcorp.com). - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* Specify predefined symbols in preprocessor. */ -#define TARGET_OS_CPP_BUILTINS() do { \ - builtin_define( "__rtems__" ); \ - builtin_assert( "system=rtems" ); \ -} while (0) |
