diff options
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 8 | ||||
| -rw-r--r-- | gcc/config/arm/neon.md | 39 |
3 files changed, 52 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dccd2ca5f34..df2de77a90d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2012-04-30 Andrew Stubbs <ams@codesourcery.com> + * config/arm/arm.md (negdi2): Use gen_negdi2_neon. + * config/arm/neon.md (negdi2_neon): New insn. + Also add splitters for core and NEON registers. + +2012-04-30 Andrew Stubbs <ams@codesourcery.com> + * config/arm/arm.c (neon_valid_immediate): Allow const_int. (arm_print_operand): Add 'x' format. * config/arm/constraints.md (Dn): Allow const_int. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 79eff0e4fe4..9506228c5e4 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4101,7 +4101,13 @@ (neg:DI (match_operand:DI 1 "s_register_operand" ""))) (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" - "" + { + if (TARGET_NEON) + { + emit_insn (gen_negdi2_neon (operands[0], operands[1])); + DONE; + } + } ) ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 960bf313076..4568dead2f1 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -926,6 +926,45 @@ (const_string "neon_int_3")))] ) +(define_insn "negdi2_neon" + [(set (match_operand:DI 0 "s_register_operand" "=&w, w,r,&r") + (neg:DI (match_operand:DI 1 "s_register_operand" " w, w,0, r"))) + (clobber (match_scratch:DI 2 "= X,&w,X, X")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_NEON" + "#" + [(set_attr "length" "8")] +) + +; Split negdi2_neon for vfp registers +(define_split + [(set (match_operand:DI 0 "s_register_operand" "") + (neg:DI (match_operand:DI 1 "s_register_operand" ""))) + (clobber (match_scratch:DI 2 "")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))" + [(set (match_dup 2) (const_int 0)) + (parallel [(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 1))) + (clobber (reg:CC CC_REGNUM))])] + { + if (!REG_P (operands[2])) + operands[2] = operands[0]; + } +) + +; Split negdi2_neon for core registers +(define_split + [(set (match_operand:DI 0 "s_register_operand" "") + (neg:DI (match_operand:DI 1 "s_register_operand" ""))) + (clobber (match_scratch:DI 2 "")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_32BIT && reload_completed + && arm_general_register_operand (operands[0], DImode)" + [(parallel [(set (match_dup 0) (neg:DI (match_dup 1))) + (clobber (reg:CC CC_REGNUM))])] + "" +) + (define_insn "*umin<mode>3_neon" [(set (match_operand:VDQIW 0 "s_register_operand" "=w") (umin:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w") |
