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-rw-r--r--gcc/ChangeLog11
-rw-r--r--gcc/cfglayout.c2
-rw-r--r--gcc/config/arm/arm.c6
-rw-r--r--gcc/config/arm/cortex-a8.md4
-rw-r--r--gcc/config/arm/neon-schedgen.ml4
-rw-r--r--gcc/config/arm/neon.ml4
-rw-r--r--gcc/config/arm/vec-common.md2
-rw-r--r--gcc/config/ia64/div.md2
-rw-r--r--gcc/cselib.c2
-rw-r--r--gcc/df-core.c2
-rw-r--r--gcc/df.h4
-rw-r--r--gcc/doc/invoke.texi2
-rw-r--r--gcc/dominance.c2
-rw-r--r--gcc/optabs.c2
-rw-r--r--gcc/opts.c2
-rw-r--r--gcc/reg-stack.c4
-rw-r--r--gcc/regstat.c2
-rw-r--r--gcc/target.h2
-rw-r--r--gcc/tree-ssa-live.c2
-rw-r--r--gcc/tree-ssa-pre.c2
-rw-r--r--gcc/tree-vect-transform.c2
-rw-r--r--gcc/tree.def2
22 files changed, 39 insertions, 28 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c8468a17642..009b3332840 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2007-07-28 Kazu Hirata <kazu@codesourcery.com>
+
+ * cfglayout.c, config/arm/arm.c, config/arm/cortex-a8.md,
+ config/arm/neon-schedgen.ml, config/arm/neon.ml,
+ config/arm/vec-common.md, config/ia64/div.md, cselib.c,
+ df-core.c, df.h, dominance.c, optabs.c, opts.c, reg-stack.c,
+ regstat.c, target.h, tree-ssa-live.c, tree-ssa-pre.c,
+ tree-vect-transform.c, tree.def: Fix comment typos. Follow
+ spelling conventions.
+ * doc/invoke.texi: Follow spelling conventions.
+
2007-07-29 Vladimir Yanovsky <yanov@il.ibm.com>
Revital Eres <eres@il.ibm.com>
diff --git a/gcc/cfglayout.c b/gcc/cfglayout.c
index 88fd27243fe..7782096800e 100644
--- a/gcc/cfglayout.c
+++ b/gcc/cfglayout.c
@@ -1001,7 +1001,7 @@ force_one_exit_fallthru (void)
redirect_edge_and_branch_force (e, forwarder);
}
- /* Fix up the chain of blocks -- make FORWARDER immediately preceed the
+ /* Fix up the chain of blocks -- make FORWARDER immediately precede the
exit block. */
FOR_EACH_BB (bb)
{
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 47f33945036..6424498f2cf 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -6083,7 +6083,7 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse,
{
unsigned HOST_WIDE_INT imm = 0;
- /* Un-invert bytes of recognized vector, if neccessary. */
+ /* Un-invert bytes of recognized vector, if necessary. */
if (invmask != 0)
for (i = 0; i < idx; i++)
bytes[i] ^= invmask;
@@ -6212,7 +6212,7 @@ neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode,
}
}
-/* Initialise a vector with non-constant elements. FIXME: We can do better
+/* Initialize a vector with non-constant elements. FIXME: We can do better
than the current implementation (building a vector on the stack and then
loading it) in many cases. See rs6000.c. */
@@ -12664,7 +12664,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
break;
/* %# is a "break" sequence. It doesn't output anything, but is used to
- seperate e.g. operand numbers from following text, if that text consists
+ separate e.g. operand numbers from following text, if that text consists
of further digits which we don't want to be part of the operand
number. */
case '#':
diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md
index 69d44de5720..e8ff16298c9 100644
--- a/gcc/config/arm/cortex-a8.md
+++ b/gcc/config/arm/cortex-a8.md
@@ -129,7 +129,7 @@
"arm_no_early_alu_shift_value_dep")
;; Multiplication instructions. These are categorized according to their
-;; reservation behaviour and the need below to distinguish certain
+;; reservation behavior and the need below to distinguish certain
;; varieties for bypasses. Results are available at the E5 stage
;; (but some of these are multi-cycle instructions which explains the
;; latencies below).
@@ -245,7 +245,7 @@
;; reads the value to be stored at the start of E3 and the ALU insn
;; writes it at the end of E2. Move instructions actually produce the
;; result at the end of E1, but since we don't have delay slots, the
-;; scheduling behaviour will be the same.
+;; scheduling behavior will be the same.
(define_bypass 0 "cortex_a8_alu,cortex_a8_alu_shift,\
cortex_a8_alu_shift_reg,cortex_a8_mov"
"cortex_a8_store1_2,cortex_a8_store3_4"
diff --git a/gcc/config/arm/neon-schedgen.ml b/gcc/config/arm/neon-schedgen.ml
index b47a0ae7d3c..c1094e9b038 100644
--- a/gcc/config/arm/neon-schedgen.ml
+++ b/gcc/config/arm/neon-schedgen.ml
@@ -63,7 +63,7 @@ type availability = Source of int
type guard = Guard_none | Guard_only_m | Guard_only_n | Guard_only_d
-(* Reservation behaviours. All but the last row here correspond to one
+(* Reservation behaviors. All but the last row here correspond to one
pipeline each. Each constructor will correspond to one
define_reservation. *)
type reservation =
@@ -78,7 +78,7 @@ type reservation =
| Fmul_then_fadd | Fmul_then_fadd_2
(* This table must be kept as short as possible by conflating
- entries with the same availability behaviour.
+ entries with the same availability behavior.
First components: instruction group names
Second components: availability requirements, in the order in which
diff --git a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml
index 59f6cc98579..39807a48d37 100644
--- a/gcc/config/arm/neon.ml
+++ b/gcc/config/arm/neon.ml
@@ -177,7 +177,7 @@ type opcode =
(* Set/extract lanes from a vector. *)
| Vget_lane
| Vset_lane
- (* Initialise vector from bit pattern. *)
+ (* Initialize vector from bit pattern. *)
| Vcreate
(* Set all lanes to same value. *)
| Vdup_n
@@ -227,7 +227,7 @@ type features =
names. *)
| Instruction_name of string list
(* Mark that the intrinsic yields no instructions, or expands to yield
- behaviour that the test generator cannot test. *)
+ behavior that the test generator cannot test. *)
| No_op
(* Mark that the intrinsic has constant arguments that cannot be set
to the defaults (zero for pointers and one otherwise) in the test
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 0514b81e55c..9d576ab51f9 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -42,7 +42,7 @@
})
;; Vector arithmetic. Expanders are blank, then unnamed insns implement
-;; patterns seperately for IWMMXT and Neon.
+;; patterns separately for IWMMXT and Neon.
(define_expand "add<mode>3"
[(set (match_operand:VALL 0 "s_register_operand" "")
diff --git a/gcc/config/ia64/div.md b/gcc/config/ia64/div.md
index a4c4721291e..e66a8a05288 100644
--- a/gcc/config/ia64/div.md
+++ b/gcc/config/ia64/div.md
@@ -195,7 +195,7 @@
operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
})
-;; Reciprical approximation
+;; Reciprocal approximation
(define_insn "recip_approx_rf"
[(set (match_operand:RF 0 "fr_register_operand" "=f")
diff --git a/gcc/cselib.c b/gcc/cselib.c
index 338b527cca9..1561762c931 100644
--- a/gcc/cselib.c
+++ b/gcc/cselib.c
@@ -953,7 +953,7 @@ cselib_expand_value_rtx (rtx orig, bitmap regs_active, int max_depth)
STACK_POINTER_REGNUM, FRAME_POINTER or the
HARD_FRAME_POINTER.
- Thses expansions confuses the code that notices that
+ These expansions confuses the code that notices that
stores into the frame go dead at the end of the
function and that the frame is not effected by calls
to subroutines. If you allow the
diff --git a/gcc/df-core.c b/gcc/df-core.c
index 16e55b752ff..453d61a999f 100644
--- a/gcc/df-core.c
+++ b/gcc/df-core.c
@@ -144,7 +144,7 @@ There are four ways of doing the incremental scanning:
For most modern rtl passes, this is certainly the easiest way to
manage rescanning the insns. This technique also has the advantage
that the scanning information is always correct and can be relied
- apon even after changes have been made to the instructions. This
+ upon even after changes have been made to the instructions. This
technique is contra indicated in several cases:
a) If def-use chains OR use-def chains (but not both) are built,
diff --git a/gcc/df.h b/gcc/df.h
index 25472861cef..d5c8d7ec126 100644
--- a/gcc/df.h
+++ b/gcc/df.h
@@ -311,7 +311,7 @@ struct dataflow
struct df_mw_hardreg
{
rtx mw_reg; /* The multiword hardreg. */
- /* These two bitfields are intentially oversized, in the hope that
+ /* These two bitfields are intentionally oversized, in the hope that
accesses to 16-bit fields will usually be quicker. */
ENUM_BITFIELD(df_ref_type) type : 16;
/* Used to see if the ref is read or write. */
@@ -360,7 +360,7 @@ struct df_ref
unsigned int ref_order;
unsigned int regno; /* The register number referenced. */
- /* These two bitfields are intentially oversized, in the hope that
+ /* These two bitfields are intentionally oversized, in the hope that
accesses to 16-bit fields will usually be quicker. */
ENUM_BITFIELD(df_ref_type) type : 16;
/* Type of ref. */
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 20c0d40ceb8..49e29825ea0 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1858,7 +1858,7 @@ been permitted when this option was not used.
In new code it is better to use @option{-fvisibility=hidden} and
export those classes which are intended to be externally visible.
Unfortunately it is possible for code to rely, perhaps accidentally,
-on the Visual Studio behaviour.
+on the Visual Studio behavior.
Among the consequences of these changes are that static data members
of the same type with the same name but defined in different shared
diff --git a/gcc/dominance.c b/gcc/dominance.c
index a67cb37cd09..ecb7f987fe4 100644
--- a/gcc/dominance.c
+++ b/gcc/dominance.c
@@ -1448,7 +1448,7 @@ debug_dominance_info (enum cdi_direction dir)
}
/* Prints to stderr representation of the dominance tree (for direction DIR)
- rooted in ROOT, indented by INDENT tabelators. If INDENT_FIRST is false,
+ rooted in ROOT, indented by INDENT tabulators. If INDENT_FIRST is false,
the first line of the output is not indented. */
static void
diff --git a/gcc/optabs.c b/gcc/optabs.c
index a605afd7ea7..d9346e59615 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -4071,7 +4071,7 @@ emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size,
{
/* If we're not emitting a branch, callers are required to pass
operands in an order conforming to canonical RTL. We relax this
- for commutative comparsions so callers using EQ don't need to do
+ for commutative comparisons so callers using EQ don't need to do
swapping by hand. */
gcc_assert (label || (comparison == swap_condition (comparison)));
diff --git a/gcc/opts.c b/gcc/opts.c
index da6f6fe589d..d6f0ec153ac 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -91,7 +91,7 @@ enum debug_info_level debug_info_level = DINFO_LEVEL_NONE;
generated in the object file of the corresponding source file.
Both of these case are handled when the base name of the file of
the struct definition matches the base name of the source file
- of thet current compilation unit. This matching emits minimal
+ of the current compilation unit. This matching emits minimal
struct debugging information.
The base file name matching rule above will fail to emit debug
diff --git a/gcc/reg-stack.c b/gcc/reg-stack.c
index be94936043c..217c43e5eb9 100644
--- a/gcc/reg-stack.c
+++ b/gcc/reg-stack.c
@@ -1355,9 +1355,9 @@ subst_stack_regs_pat (rtx insn, stack regstack, rtx pat)
}
/* Uninitialized USE might happen for functions returning uninitialized
value. We will properly initialize the USE on the edge to EXIT_BLOCK,
- so it is safe to ignore the use here. This is consistent with behaviour
+ so it is safe to ignore the use here. This is consistent with behavior
of dataflow analyzer that ignores USE too. (This also imply that
- forcingly initializing the register to NaN here would lead to ICE later,
+ forcibly initializing the register to NaN here would lead to ICE later,
since the REG_DEAD notes are not issued.) */
break;
diff --git a/gcc/regstat.c b/gcc/regstat.c
index 86afc389053..9f8e41f35af 100644
--- a/gcc/regstat.c
+++ b/gcc/regstat.c
@@ -395,7 +395,7 @@ regstat_get_setjmp_crosses (void)
Process REG_N_CALLS_CROSSED.
This is used by sched_deps. A good implementation of sched-deps
- would really process the blocks directly rather than going thur
+ would really process the blocks directly rather than going through
lists of insns. If it did this, it could use the exact regs that
cross an individual call rather than using this info that merges
the info for all calls.
diff --git a/gcc/target.h b/gcc/target.h
index d7272bb8768..760656c43a0 100644
--- a/gcc/target.h
+++ b/gcc/target.h
@@ -420,7 +420,7 @@ struct gcc_target
int (*builtin_vectorization_cost) (bool);
/* Return true if vector alignment is reachable (by peeling N
- interations) for the given type. */
+ iterations) for the given type. */
bool (* vector_alignment_reachable) (tree, bool);
} vectorize;
diff --git a/gcc/tree-ssa-live.c b/gcc/tree-ssa-live.c
index 5dcebb5c253..0fba499fe47 100644
--- a/gcc/tree-ssa-live.c
+++ b/gcc/tree-ssa-live.c
@@ -461,7 +461,7 @@ mark_scope_block_unused (tree scope)
or there is precisely one subblocks and the block
has same abstract origin as outer block and declares
no variables, so it is pure wrapper.
- When we are not outputting full debug info, we also elliminate dead variables
+ When we are not outputting full debug info, we also eliminate dead variables
out of scope blocks to let them to be recycled by GGC and to save copying work
done by the inliner. */
diff --git a/gcc/tree-ssa-pre.c b/gcc/tree-ssa-pre.c
index 962f945e6b8..1cebc4a5e86 100644
--- a/gcc/tree-ssa-pre.c
+++ b/gcc/tree-ssa-pre.c
@@ -1431,7 +1431,7 @@ bitmap_find_leader (bitmap_set_t set, tree val)
return NULL;
}
-/* Determine if EXPR, a memory expressionn, is ANTIC_IN at the top of
+/* Determine if EXPR, a memory expression, is ANTIC_IN at the top of
BLOCK by seeing if it is not killed in the block. Note that we are
only determining whether there is a store that kills it. Because
of the order in which clean iterates over values, we are guaranteed
diff --git a/gcc/tree-vect-transform.c b/gcc/tree-vect-transform.c
index 8d309583e72..642437cbbdf 100644
--- a/gcc/tree-vect-transform.c
+++ b/gcc/tree-vect-transform.c
@@ -265,7 +265,7 @@ vect_estimate_min_profitable_iters (loop_vec_info loop_vinfo)
/* If the number of iterations is unknown, or the
peeling-for-misalignment amount is unknown, we eill have to generate
- a runtime test to test the loop count agains the threshold. */
+ a runtime test to test the loop count against the threshold. */
if (!LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo)
|| (byte_misalign < 0))
runtime_test = true;
diff --git a/gcc/tree.def b/gcc/tree.def
index adcac4b2469..aa95cb1db31 100644
--- a/gcc/tree.def
+++ b/gcc/tree.def
@@ -884,7 +884,7 @@ DEFTREECODE (EH_FILTER_EXPR, "eh_filter_expr", tcc_statement, 2)
has no value and generates no executable code. It is only used for
type based alias analysis. This is generated by C++ placement new.
CHANGE_DYNAMIC_TYPE_NEW_TYPE, the first operand, is the new type.
- CHNAGE_DYNAMIC_TYPE_LOCATION, the second operand, is the location
+ CHANGE_DYNAMIC_TYPE_LOCATION, the second operand, is the location
whose type is being changed. */
DEFTREECODE (CHANGE_DYNAMIC_TYPE_EXPR, "change_dynamic_type_expr",
tcc_statement, 2)
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