diff options
| -rw-r--r-- | gcc/ChangeLog | 27 | ||||
| -rw-r--r-- | gcc/config/frv/frv-protos.h | 2 | ||||
| -rw-r--r-- | gcc/config/frv/frv.c | 279 | ||||
| -rw-r--r-- | gcc/config/frv/frv.md | 10 |
4 files changed, 174 insertions, 144 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9b4dccdeebf..1b4df960cd4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,30 @@ +2010-11-08 Joern Rennecke <amylaar@spamcop.net> + Richard Henderson <rth@redhat.com> + + PR target/44758 + * config/frv/frv.md (attribute cpu): Cast value to enum attr_cpu. + (attribute acc_group): Cast value to enum attr_acc_group. + (*movdi_nodouble+6): Use gen_int_mode. + * config/frv/frv-protos.h (frv_trampoline_size): Declare no matter + if RTX_CODE is defined or not. + * config/frv/frv.c (enum frv_io_type): New enum, broken out of + struct frv_io. + (frv_handle_option): Mark parameter value with ATTRIBUTE_UNUSED. + (frv_frame_access, frv_expand_prologue): Remove unused variables. + (frv_expand_block_clear): Likewise. + (frv_trampoline_init): Use LCT_NORMAL. + (struct frv_packet_group): New struct, broken out of type of + frv_packet. + (frv_start_packet, frv_reorder_packet): Initialize group to GROUP_I, + use cast in loop counter increment. + (frv_extract_membar): Cast HOST_WIDE_INT to enum frv_io_type before + assigning to io->type. + (bdesc_set): Use rtx_code UNKNOWN in initializer. + (bdesc_1arg, bdesc_2arg, bdesc_int_void2arg): Likewise. + (bdesc_prefetches, bdesc_cut, bdesc_2argimm, bdesc_void2arg): Likewise. + (bdesc_void3arg, bdesc_voidacc, bdesc_loads, bdesc_stores): Likewise. + (frv_read_argument): Use expand_normal. + 2010-11-08 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> * config/i386/i386.c (ix86_function_arg_boundary): Fix warning diff --git a/gcc/config/frv/frv-protos.h b/gcc/config/frv/frv-protos.h index af9f1cdd7e2..3fd9d0c16d9 100644 --- a/gcc/config/frv/frv-protos.h +++ b/gcc/config/frv/frv-protos.h @@ -89,7 +89,6 @@ extern rtx frv_ifcvt_modify_insn (ce_if_block_t *, rtx, rtx); extern void frv_ifcvt_modify_final (ce_if_block_t *); extern void frv_ifcvt_modify_cancel (ce_if_block_t *); #endif -extern int frv_trampoline_size (void); extern enum reg_class frv_secondary_reload_class (enum reg_class, enum machine_mode, rtx); @@ -101,6 +100,7 @@ extern int frv_legitimate_constant_p (rtx); extern enum machine_mode frv_select_cc_mode (enum rtx_code, rtx, rtx); #endif /* RTX_CODE */ +extern int frv_trampoline_size (void); extern int direct_return_p (void); extern int frv_issue_rate (void); extern int frv_acc_group (rtx); diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c index adc69117c4b..fc127ac115a 100644 --- a/gcc/config/frv/frv.c +++ b/gcc/config/frv/frv.c @@ -109,13 +109,15 @@ static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS]; /* The number of nop instructions in frv_nops[]. */ static unsigned int frv_num_nops; + /* The type of access. FRV_IO_UNKNOWN means the access can be either + a read or a write. */ +enum frv_io_type { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE }; + /* Information about one __builtin_read or __builtin_write access, or the combination of several such accesses. The most general value is all-zeros (an unknown access to an unknown address). */ struct frv_io { - /* The type of access. FRV_IO_UNKNOWN means the access can be either - a read or a write. */ - enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type; + enum frv_io_type type; /* The constant address being accessed, or zero if not known. */ HOST_WIDE_INT const_address; @@ -625,7 +627,7 @@ frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) /* Implement TARGET_HANDLE_OPTION. */ static bool -frv_handle_option (size_t code, const char *arg, int value) +frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) { switch (code) { @@ -1720,9 +1722,10 @@ frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset) && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG) { rtx temp = gen_rtx_REG (SImode, TEMP_REGNO); - rtx insn = emit_move_insn (temp, - gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), - XEXP (XEXP (mem, 0), 1))); + + emit_move_insn (temp, + gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), + XEXP (XEXP (mem, 0), 1))); mem = gen_rtx_MEM (DImode, temp); } emit_insn (gen_rtx_SET (VOIDmode, reg, mem)); @@ -1753,9 +1756,9 @@ frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset) && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG) { rtx temp = gen_rtx_REG (SImode, TEMP_REGNO); - rtx insn = emit_move_insn (temp, - gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), - XEXP (XEXP (mem, 0), 1))); + emit_move_insn (temp, + gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), + XEXP (XEXP (mem, 0), 1))); mem = gen_rtx_MEM (DImode, temp); } @@ -1860,11 +1863,9 @@ frv_expand_prologue (void) accessor.op = FRV_STORE; if (frame_pointer_needed && info->total_size > 2048) { - rtx insn; - accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO); accessor.base_offset = info->total_size; - insn = emit_insn (gen_movsi (accessor.base, sp)); + emit_insn (gen_movsi (accessor.base, sp)); } else { @@ -2393,7 +2394,6 @@ frv_expand_block_clear (rtx operands[]) int align; int bytes; int offset; - int num_reg; rtx dest_reg; rtx dest_addr; rtx dest_mem; @@ -2421,7 +2421,7 @@ frv_expand_block_clear (rtx operands[]) /* Move the address into a scratch register. */ dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); - num_reg = offset = 0; + offset = 0; for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes)) { /* Calculate the correct offset for src/dest. */ @@ -6371,7 +6371,7 @@ frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) rtx sc_reg = force_reg (Pmode, static_chain); emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), - FALSE, VOIDmode, 4, + LCT_NORMAL, VOIDmode, 4, addr, Pmode, GEN_INT (frv_trampoline_size ()), SImode, fnaddr, Pmode, @@ -7167,6 +7167,24 @@ frv_issues_to_branch_unit_p (rtx insn) return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B; } +/* The instructions in the packet, partitioned into groups. */ +struct frv_packet_group { + /* How many instructions in the packet belong to this group. */ + unsigned int num_insns; + + /* A list of the instructions that belong to this group, in the order + they appear in the rtl stream. */ + rtx insns[ARRAY_SIZE (frv_unit_codes)]; + + /* The contents of INSNS after they have been sorted into the correct + assembly-language order. Element X issues to unit X. The list may + contain extra nops. */ + rtx sorted[ARRAY_SIZE (frv_unit_codes)]; + + /* The member of frv_nops[] to use in sorted[]. */ + rtx nop; +}; + /* The current state of the packing pass, implemented by frv_pack_insns. */ static struct { /* The state of the pipeline DFA. */ @@ -7192,22 +7210,7 @@ static struct { unsigned int issue_rate; /* The instructions in the packet, partitioned into groups. */ - struct frv_packet_group { - /* How many instructions in the packet belong to this group. */ - unsigned int num_insns; - - /* A list of the instructions that belong to this group, in the order - they appear in the rtl stream. */ - rtx insns[ARRAY_SIZE (frv_unit_codes)]; - - /* The contents of INSNS after they have been sorted into the correct - assembly-language order. Element X issues to unit X. The list may - contain extra nops. */ - rtx sorted[ARRAY_SIZE (frv_unit_codes)]; - - /* The member of frv_nops[] to use in sorted[]. */ - rtx nop; - } groups[NUM_GROUPS]; + struct frv_packet_group groups[NUM_GROUPS]; /* The instructions that make up the current packet. */ rtx insns[ARRAY_SIZE (frv_unit_codes)]; @@ -7380,7 +7383,8 @@ frv_start_packet (void) memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate)); frv_packet.num_mems = 0; frv_packet.num_insns = 0; - for (group = 0; group < NUM_GROUPS; group++) + for (group = GROUP_I; group < NUM_GROUPS; + group = (enum frv_insn_group) (group + 1)) frv_packet.groups[group].num_insns = 0; } @@ -7729,7 +7733,8 @@ frv_reorder_packet (void) struct frv_packet_group *packet_group; /* First sort each group individually. */ - for (group = 0; group < NUM_GROUPS; group++) + for (group = GROUP_I; group < NUM_GROUPS; + group = (enum frv_insn_group) (group + 1)) { cursor[group] = 0; frv_sort_insn_group (group); @@ -7862,7 +7867,7 @@ static void frv_extract_membar (struct frv_io *io, rtx insn) { extract_insn (insn); - io->type = INTVAL (recog_data.operand[2]); + io->type = (enum frv_io_type) INTVAL (recog_data.operand[2]); io->const_address = INTVAL (recog_data.operand[1]); io->var_address = XEXP (recog_data.operand[0], 0); } @@ -8281,99 +8286,100 @@ struct builtin_description static struct builtin_description bdesc_set[] = { - { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 } + { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, UNKNOWN, 0 } }; /* Media intrinsics that take just one argument. */ static struct builtin_description bdesc_1arg[] = { - { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 }, - { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 }, - { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 }, - { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 }, - { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }, - { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 } + { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, UNKNOWN, 0 }, + { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, UNKNOWN, 0 }, + { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, UNKNOWN, 0 }, + { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, UNKNOWN, 0}, + { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, UNKNOWN, 0 }, + { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, UNKNOWN, 0 } }; /* Media intrinsics that take two arguments. */ static struct builtin_description bdesc_2arg[] = { - { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 }, - { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 }, - { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 }, - { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 }, - { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 }, - { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 }, - { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 }, - { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 }, - { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 }, - { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 }, - { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 }, - { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 }, - { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 }, - { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 }, - { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 }, - { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 }, - { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 }, - { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 }, - { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }, - { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 }, - { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 }, - { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 }, - { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 }, - { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 }, - { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 }, - { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 }, - { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 } + { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, UNKNOWN, 0}, + { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, UNKNOWN, 0}, + { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, UNKNOWN, 0}, + { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, UNKNOWN, 0}, + { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, UNKNOWN, 0}, + { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, UNKNOWN, 0}, + { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, UNKNOWN, 0}, + { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, UNKNOWN, 0}, + { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, UNKNOWN, 0}, + { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, UNKNOWN, 0}, + { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, UNKNOWN, 0}, + { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, UNKNOWN, 0}, + { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, UNKNOWN, 0}, + { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, UNKNOWN, 0}, + { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, UNKNOWN, 0}, + { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, UNKNOWN, 0}, + { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, UNKNOWN, 0}, + { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, UNKNOWN, 0}, + { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, UNKNOWN, 0}, + { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, UNKNOWN, 0}, + { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, UNKNOWN, 0}, + { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, UNKNOWN, 0}, + { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, UNKNOWN, 0}, + { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, UNKNOWN, 0}, + { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, UNKNOWN, 0}, + { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, UNKNOWN, 0}, + { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, UNKNOWN, 0} }; /* Integer intrinsics that take two arguments and have no return value. */ static struct builtin_description bdesc_int_void2arg[] = { - { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 }, - { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 }, - { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 } + { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, UNKNOWN, 0}, + { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, UNKNOWN, 0}, + { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, UNKNOWN, 0} }; static struct builtin_description bdesc_prefetches[] = { - { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 }, - { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 } + { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, UNKNOWN, + 0}, + { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, UNKNOWN, 0} }; /* Media intrinsics that take two arguments, the first being an ACC number. */ static struct builtin_description bdesc_cut[] = { - { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 }, - { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 }, - { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 } + { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, UNKNOWN, 0}, + { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, UNKNOWN, 0}, + { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, UNKNOWN, 0} }; /* Two-argument media intrinsics with an immediate second argument. */ static struct builtin_description bdesc_2argimm[] = { - { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 }, - { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 }, - { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 }, - { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 }, - { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 }, - { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 }, - { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 }, - { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 }, - { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 }, - { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 }, - { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 }, - { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 }, - { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 }, - { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 }, - { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }, - { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 }, - { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 } + { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, UNKNOWN, 0}, + { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, UNKNOWN, 0}, + { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, UNKNOWN, 0}, + { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, UNKNOWN, 0}, + { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, UNKNOWN, 0}, + { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, UNKNOWN, 0}, + { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, UNKNOWN, 0}, + { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, UNKNOWN, 0}, + { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, UNKNOWN, 0}, + { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, UNKNOWN, 0}, + { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, UNKNOWN, 0}, + { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, UNKNOWN, 0}, + { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, UNKNOWN, 0}, + { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, UNKNOWN, 0}, + { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, UNKNOWN, 0}, + { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, UNKNOWN, 0}, + { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, UNKNOWN, 0} }; /* Media intrinsics that take two arguments and return void, the first argument @@ -8381,8 +8387,8 @@ static struct builtin_description bdesc_2argimm[] = static struct builtin_description bdesc_void2arg[] = { - { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 }, - { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 }, + { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, UNKNOWN, 0}, + { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, UNKNOWN, 0}, }; /* Media intrinsics that take three arguments, the first being a const_int that @@ -8390,31 +8396,31 @@ static struct builtin_description bdesc_void2arg[] = static struct builtin_description bdesc_void3arg[] = { - { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 }, - { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 }, - { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 }, - { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 }, - { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 }, - { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 }, - { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 }, - { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 }, - { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 }, - { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 }, - { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 }, - { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 }, - { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 }, - { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 }, - { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 }, - { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 }, - { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 }, - { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 }, - { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 }, - { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 }, - { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 }, - { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 }, - { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 }, - { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 }, - { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 } + { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, UNKNOWN, 0}, + { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, UNKNOWN, 0}, + { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, UNKNOWN, 0}, + { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, UNKNOWN, 0}, + { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, UNKNOWN, 0}, + { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, UNKNOWN, 0}, + { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, UNKNOWN, 0}, + { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, UNKNOWN, 0}, + { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, UNKNOWN, 0}, + { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, UNKNOWN, 0}, + { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, UNKNOWN, 0}, + { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, UNKNOWN, 0}, + { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, UNKNOWN, 0}, + { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, UNKNOWN, 0}, + { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, UNKNOWN, 0}, + { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, UNKNOWN, 0}, + { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, UNKNOWN, 0}, + { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, UNKNOWN, 0}, + { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, UNKNOWN, 0}, + { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, UNKNOWN, 0}, + { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, UNKNOWN, 0}, + { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, UNKNOWN, 0}, + { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, UNKNOWN, 0}, + { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, UNKNOWN, 0}, + { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, UNKNOWN, 0} }; /* Media intrinsics that take two accumulator numbers as argument and @@ -8422,12 +8428,12 @@ static struct builtin_description bdesc_void3arg[] = static struct builtin_description bdesc_voidacc[] = { - { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 }, - { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 }, - { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 }, - { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 }, - { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 }, - { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 } + { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, UNKNOWN, 0}, + { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, UNKNOWN, 0}, + { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, UNKNOWN, 0}, + { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, UNKNOWN, 0}, + { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, UNKNOWN, 0}, + { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, UNKNOWN, 0} }; /* Intrinsics that load a value and then issue a MEMBAR. The load is @@ -8436,13 +8442,13 @@ static struct builtin_description bdesc_voidacc[] = static struct builtin_description bdesc_loads[] = { { CODE_FOR_optional_membar_qi, "__builtin_read8", - FRV_BUILTIN_READ8, 0, 0 }, + FRV_BUILTIN_READ8, UNKNOWN, 0}, { CODE_FOR_optional_membar_hi, "__builtin_read16", - FRV_BUILTIN_READ16, 0, 0 }, + FRV_BUILTIN_READ16, UNKNOWN, 0}, { CODE_FOR_optional_membar_si, "__builtin_read32", - FRV_BUILTIN_READ32, 0, 0 }, + FRV_BUILTIN_READ32, UNKNOWN, 0}, { CODE_FOR_optional_membar_di, "__builtin_read64", - FRV_BUILTIN_READ64, 0, 0 } + FRV_BUILTIN_READ64, UNKNOWN, 0} }; /* Likewise stores. */ @@ -8450,13 +8456,13 @@ static struct builtin_description bdesc_loads[] = static struct builtin_description bdesc_stores[] = { { CODE_FOR_optional_membar_qi, "__builtin_write8", - FRV_BUILTIN_WRITE8, 0, 0 }, + FRV_BUILTIN_WRITE8, UNKNOWN, 0}, { CODE_FOR_optional_membar_hi, "__builtin_write16", - FRV_BUILTIN_WRITE16, 0, 0 }, + FRV_BUILTIN_WRITE16, UNKNOWN, 0}, { CODE_FOR_optional_membar_si, "__builtin_write32", - FRV_BUILTIN_WRITE32, 0, 0 }, + FRV_BUILTIN_WRITE32, UNKNOWN, 0}, { CODE_FOR_optional_membar_di, "__builtin_write64", - FRV_BUILTIN_WRITE64, 0, 0 }, + FRV_BUILTIN_WRITE64, UNKNOWN, 0}, }; /* Initialize media builtins. */ @@ -8811,8 +8817,7 @@ frv_matching_accg_for_acc (rtx acc) static rtx frv_read_argument (tree exp, unsigned int index) { - return expand_expr (CALL_EXPR_ARG (exp, index), - NULL_RTX, VOIDmode, 0); + return expand_normal (CALL_EXPR_ARG (exp, index)); } /* Like frv_read_argument, but interpret the argument as the number diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md index 9315f9b623c..2440d12fccf 100644 --- a/gcc/config/frv/frv.md +++ b/gcc/config/frv/frv.md @@ -345,7 +345,7 @@ ;; enumeration in frv-protos.h. (define_attr "cpu" "generic,fr550,fr500,fr450,fr405,fr400,fr300,simple,tomcat" - (const (symbol_ref "frv_cpu_type"))) + (const (symbol_ref "(enum attr_cpu) frv_cpu_type"))) ;; Attribute is "yes" for branches and jumps that span too great a distance ;; to be implemented in the most natural way. Such instructions will use @@ -360,7 +360,7 @@ (const_string "unknown")) (define_attr "acc_group" "none,even,odd" - (symbol_ref "frv_acc_group (insn)")) + (symbol_ref "(enum attr_acc_group) frv_acc_group (insn)")) ;; Scheduling and Packing Overview ;; ------------------------------- @@ -1895,10 +1895,8 @@ } else { - operands[4] = GEN_INT ((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16) - >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31) - - ((unsigned HOST_WIDE_INT)1 << 31)); - operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode)); + operands[4] = gen_int_mode ((INTVAL (op1) >> 16) >> 16, SImode); + operands[5] = gen_int_mode (INTVAL (op1), SImode); } }") |
