diff options
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 12 |
2 files changed, 13 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 534cfae2cae..db45e7e2e9e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2004-06-23 Richard Earnshaw <rearnsha@arm.com> + * PR target/15948 + * arm.md (bicsi3_cbranch): Add alternative to handle tying operands + one and two. + +2004-06-23 Richard Earnshaw <rearnsha@arm.com> + PR target/15927 * arm.h (THUMB_SECONDARY_OUTPUT_RELOAD_CLASS): Don't need a secondary reload if CLASS is BASE_REGS. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 82f1701674f..fb13fe061f5 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6167,22 +6167,24 @@ [(set (pc) (if_then_else (match_operator 5 "equality_operator" - [(and:SI (not:SI (match_operand:SI 3 "s_register_operand" "l,l,l,l")) - (match_operand:SI 2 "s_register_operand" "0,1,1,1")) + [(and:SI (not:SI (match_operand:SI 3 "s_register_operand" "l,l,l,l,l")) + (match_operand:SI 2 "s_register_operand" "0,1,1,1,1")) (const_int 0)]) (label_ref (match_operand 4 "" "")) (pc))) - (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") + (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=!l,l,*?h,*?m,*?m") (and:SI (not:SI (match_dup 3)) (match_dup 2))) - (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] + (clobber (match_scratch:SI 1 "=X,l,l,&l,&l"))] "TARGET_THUMB" "* { if (which_alternative == 0) output_asm_insn (\"bic\\t%0, %3\", operands); - else if (which_alternative == 1) + else if (which_alternative <= 2) { output_asm_insn (\"bic\\t%1, %3\", operands); + /* It's ok if OP0 is a lo-reg, even though the mov will set the + conditions again, since we're only testing for equality. */ output_asm_insn (\"mov\\t%0, %1\", operands); } else |
