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authorrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>2012-07-10 08:26:00 +0000
committerrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>2012-07-10 08:26:00 +0000
commitdc5ba181ed3d6e27807bd895d24e409a9d78a7c8 (patch)
tree73a829a24b50697296c2f3ee51f084a5b5e19a64 /gcc/config
parent04fb053a642208358c674531f8f5c17e3b7a8d13 (diff)
downloadppe42-gcc-dc5ba181ed3d6e27807bd895d24e409a9d78a7c8.tar.gz
ppe42-gcc-dc5ba181ed3d6e27807bd895d24e409a9d78a7c8.zip
Zap now unused builtin_mul_widen_even/odd target hooks
* target.def (builtin_mul_widen_even, builtin_mul_widen_odd): Remove. * system.h (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Poison. (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Poison. * config/i386/i386.c (IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V4SI): Remove. (IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V8SI): Remove. (IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V4SI): Remove. (IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V8SI): Remove. (IX86_BUILTIN_VEC_WIDEN_SMUL_EVEN_V4SI): Remove. (IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V4SI): Remove. (IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V8SI): Remove. (bdesc_args): Remove entries to match. (ix86_builtin_mul_widen_even, ix86_builtin_mul_widen_odd): Remove. (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Remove. (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Remove. * config/rs6000/rs6000.c (rs6000_builtin_mul_widen_even): Remove. (rs6000_builtin_mul_widen_odd): Remove. (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Remove. (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Remove. * config/spu/spu.c (spu_builtin_mul_widen_even): Remove. (spu_builtin_mul_widen_odd): Remove. (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN): Remove. (TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD): Remove. * doc/tm.texi.in: Don't document the removed hooks. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@189409 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/i386/i386.c76
-rw-r--r--gcc/config/rs6000/rs6000.c51
-rw-r--r--gcc/config/spu/spu.c42
3 files changed, 0 insertions, 169 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 3cb34cea569..23abe0126c5 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -25754,14 +25754,6 @@ enum ix86_builtins
IX86_BUILTIN_CPYSGNPS256,
IX86_BUILTIN_CPYSGNPD256,
- IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V4SI,
- IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V8SI,
- IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V4SI,
- IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V8SI,
- IX86_BUILTIN_VEC_WIDEN_SMUL_EVEN_V4SI,
- IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V4SI,
- IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V8SI,
-
/* FMA4 instructions. */
IX86_BUILTIN_VFMADDSS,
IX86_BUILTIN_VFMADDSD,
@@ -26620,10 +26612,6 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
- { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_vw_umul_even_v4si", IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V4SI, UNKNOWN, (int) V2UDI_FTYPE_V4USI_V4USI },
- { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_smult_even_v4si, "__builtin_ia32_vw_smul_even_v4si", IX86_BUILTIN_VEC_WIDEN_SMUL_EVEN_V4SI, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
- { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_odd_v4si, "__builtin_ia32_vw_umul_odd_v4si", IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V4SI, UNKNOWN, (int) V2UDI_FTYPE_V4USI_V4USI },
- { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_smult_odd_v4si, "__builtin_ia32_vw_smul_odd_v4si", IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V4SI, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
@@ -27016,15 +27004,12 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
- { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_odd_v8si, "__builtin_ia32_vw_smul_odd_v8si", IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V8SI, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_umulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
- { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_i386_vw_umul_even_v8si", IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V8SI, UNKNOWN, (int) V4UDI_FTYPE_V8USI_V8USI },
- { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_odd_v8si, "__builtin_ia32_vw_umul_odd_v8si", IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V8SI, UNKNOWN, (int) V4UDI_FTYPE_V8USI_V8USI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
@@ -31063,62 +31048,6 @@ ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
return NULL_TREE;
}
}
-
-static tree
-ix86_builtin_mul_widen_even (tree type)
-{
- bool uns_p = TYPE_UNSIGNED (type);
- enum ix86_builtins code;
-
- switch (TYPE_MODE (type))
- {
- case V4SImode:
- if (!TARGET_SSE2)
- return NULL;
- code = (uns_p ? IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V4SI
- : IX86_BUILTIN_VEC_WIDEN_SMUL_EVEN_V4SI);
- break;
-
- case V8SImode:
- if (!TARGET_AVX2)
- return NULL;
- code = (uns_p ? IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V8SI
- : IX86_BUILTIN_PMULDQ256);
- break;
-
- default:
- return NULL;
- }
- return ix86_builtins[code];
-}
-
-static tree
-ix86_builtin_mul_widen_odd (tree type)
-{
- bool uns_p = TYPE_UNSIGNED (type);
- enum ix86_builtins code;
-
- switch (TYPE_MODE (type))
- {
- case V4SImode:
- if (!TARGET_SSE2)
- return NULL;
- code = (uns_p ? IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V4SI
- : IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V4SI);
- break;
-
- case V8SImode:
- if (!TARGET_AVX2)
- return NULL;
- code = (uns_p ? IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V8SI
- : IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V8SI);
- break;
-
- default:
- return NULL;
- }
- return ix86_builtins[code];
-}
/* Helper for avx_vpermilps256_operand et al. This is also used by
the expansion functions to turn the parallel back into a mask.
@@ -40204,11 +40133,6 @@ ix86_memmodel_check (unsigned HOST_WIDE_INT val)
#undef TARGET_VECTORIZE_BUILTIN_GATHER
#define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
-#undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
-#define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN ix86_builtin_mul_widen_even
-#undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
-#define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD ix86_builtin_mul_widen_odd
-
#undef TARGET_BUILTIN_RECIPROCAL
#define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index c124c639e0d..1d0e247dcd3 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1273,10 +1273,6 @@ static const struct attribute_spec rs6000_attribute_table[] =
#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
-#undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
-#define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
-#undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
-#define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
#undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
#define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
rs6000_builtin_support_vector_misalignment
@@ -3285,53 +3281,6 @@ rs6000_loop_align_max_skip (rtx label)
return (1 << rs6000_loop_align (label)) - 1;
}
-/* Implement targetm.vectorize.builtin_mul_widen_even. */
-static tree
-rs6000_builtin_mul_widen_even (tree type)
-{
- if (!TARGET_ALTIVEC)
- return NULL_TREE;
-
- switch (TYPE_MODE (type))
- {
- case V8HImode:
- return TYPE_UNSIGNED (type)
- ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH_UNS]
- : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
-
- case V16QImode:
- return TYPE_UNSIGNED (type)
- ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB_UNS]
- : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
- default:
- return NULL_TREE;
- }
-}
-
-/* Implement targetm.vectorize.builtin_mul_widen_odd. */
-static tree
-rs6000_builtin_mul_widen_odd (tree type)
-{
- if (!TARGET_ALTIVEC)
- return NULL_TREE;
-
- switch (TYPE_MODE (type))
- {
- case V8HImode:
- return TYPE_UNSIGNED (type)
- ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH_UNS]
- : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
-
- case V16QImode:
- return TYPE_UNSIGNED (type)
- ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB_UNS]
- : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
- default:
- return NULL_TREE;
- }
-}
-
-
/* Return true iff, data reference of TYPE can reach vector alignment (16)
after applying N number of iterations. This routine does not determine
how may iterations are required to reach desired alignment. */
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index 3e0135fb592..7ca40a0d89d 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -211,8 +211,6 @@ static void spu_encode_section_info (tree, rtx, int);
static rtx spu_legitimize_address (rtx, rtx, enum machine_mode);
static rtx spu_addr_space_legitimize_address (rtx, rtx, enum machine_mode,
addr_space_t);
-static tree spu_builtin_mul_widen_even (tree);
-static tree spu_builtin_mul_widen_odd (tree);
static tree spu_builtin_mask_for_load (void);
static int spu_builtin_vectorization_cost (enum vect_cost_for_stmt, tree, int);
static bool spu_vector_alignment_reachable (const_tree, bool);
@@ -431,12 +429,6 @@ static void spu_setup_incoming_varargs (cumulative_args_t cum,
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO spu_encode_section_info
-#undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
-#define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN spu_builtin_mul_widen_even
-
-#undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
-#define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD spu_builtin_mul_widen_odd
-
#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD spu_builtin_mask_for_load
@@ -6863,40 +6855,6 @@ spu_expand_builtin (tree exp,
abort ();
}
-/* Implement targetm.vectorize.builtin_mul_widen_even. */
-static tree
-spu_builtin_mul_widen_even (tree type)
-{
- switch (TYPE_MODE (type))
- {
- case V8HImode:
- if (TYPE_UNSIGNED (type))
- return spu_builtin_decls[SPU_MULE_0];
- else
- return spu_builtin_decls[SPU_MULE_1];
- break;
- default:
- return NULL_TREE;
- }
-}
-
-/* Implement targetm.vectorize.builtin_mul_widen_odd. */
-static tree
-spu_builtin_mul_widen_odd (tree type)
-{
- switch (TYPE_MODE (type))
- {
- case V8HImode:
- if (TYPE_UNSIGNED (type))
- return spu_builtin_decls[SPU_MULO_1];
- else
- return spu_builtin_decls[SPU_MULO_0];
- break;
- default:
- return NULL_TREE;
- }
-}
-
/* Implement targetm.vectorize.builtin_mask_for_load. */
static tree
spu_builtin_mask_for_load (void)
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