diff options
| author | cgd <cgd@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-01-25 23:45:48 +0000 |
|---|---|---|
| committer | cgd <cgd@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-01-25 23:45:48 +0000 |
| commit | e78db7f7abc2d40fb40968d4d9f0a9bfd8697d89 (patch) | |
| tree | 2863832dddcc0373989de7d3572a458eddf9cb10 | |
| parent | ef57ef9796070211a6fc10bdbecffa6d31b33714 (diff) | |
| download | ppe42-gcc-e78db7f7abc2d40fb40968d4d9f0a9bfd8697d89.tar.gz ppe42-gcc-e78db7f7abc2d40fb40968d4d9f0a9bfd8697d89.zip | |
2003-04-25 Chris Demetriou <cgd@broadcom.com>
* config/mips/mips.h (ISA_HAS_HILO_INTERLOCKS): MIPS32, MIPS32r2,
and MIPS64 have HI/LO interlocks. Update comment.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@76597 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.h | 18 |
2 files changed, 20 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 64cc3881fa1..4b6de596f5c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2003-04-25 Chris Demetriou <cgd@broadcom.com> + + * config/mips/mips.h (ISA_HAS_HILO_INTERLOCKS): MIPS32, MIPS32r2, + and MIPS64 have HI/LO interlocks. Update comment. + 2004-01-25 Kazu Hirata <kazu@cs.umass.edu> * config/stormy16/stormy16-protos.h: Remove the prototype for diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index ae1f55f132c..2ea0f67f3d9 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -942,9 +942,21 @@ extern const struct mips_cpu_info *mips_tune_info; #define ISA_HAS_FCMP_DELAY (mips_isa <= 3) /* True if mflo and mfhi can be immediately followed by instructions - which write to the HI and LO registers. Most targets require a - two-instruction gap. */ -#define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1) + which write to the HI and LO registers. + + According to MIPS specifications, MIPS ISAs I, II, and III need + (at least) two instructions between the reads of HI/LO and + instructions which write them, and later ISAs do not. Contradicting + the MIPS specifications, some MIPS IV processor user manuals (e.g. + the UM for the NEC Vr5000) document needing the instructions between + HI/LO reads and writes, as well. Therefore, we declare only MIPS32, + MIPS64 and later ISAs to have the interlocks, plus any specific + earlier-ISA CPUs for which CPU documentation declares that the + instructions are really interlocked. */ +#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ + || ISA_MIPS32R2 \ + || ISA_MIPS64 \ + || TARGET_MIPS5500) /* Add -G xx support. */ |
