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| author | nemet <nemet@138bc75d-0d04-0410-961f-82ee72b054a4> | 2008-12-11 22:50:12 +0000 |
|---|---|---|
| committer | nemet <nemet@138bc75d-0d04-0410-961f-82ee72b054a4> | 2008-12-11 22:50:12 +0000 |
| commit | e757dcfa86e365604393a0b52f2e155e0bb06027 (patch) | |
| tree | 52ccd67c4acff03a4acaf8813e0ef0974b8fd200 | |
| parent | 22c680e3266580b1cd7519fb13e2e081f6a0234a (diff) | |
| download | ppe42-gcc-e757dcfa86e365604393a0b52f2e155e0bb06027.tar.gz ppe42-gcc-e757dcfa86e365604393a0b52f2e155e0bb06027.zip | |
* config/mips/mips.md (*branch_bit<bbv><mode>,
*branch_bit<bbv><mode>_inverted): Renumber operands so that the
label becomes operands[1].
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@142694 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 16 |
2 files changed, 14 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 64a7b927315..c792f1e2598 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2008-12-11 Adam Nemet <anemet@caviumnetworks.com> + + * config/mips/mips.md (*branch_bit<bbv><mode>, + *branch_bit<bbv><mode>_inverted): Renumber operands so that the + label becomes operands[1]. + 2008-12-11 Harsha Jagasia <harsha.jagasia@amd.com> PR tree-optimization/38446 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index b9226c5c61d..1b26f029853 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -5203,18 +5203,18 @@ [(set (pc) (if_then_else (equality_op (zero_extract:GPR - (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 0 "register_operand" "d") (const_int 1) (match_operand 2 "const_int_operand" "")) (const_int 0)) - (label_ref (match_operand 0 "")) + (label_ref (match_operand 1 "")) (pc)))] "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" { return mips_output_conditional_branch (insn, operands, - MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"), - MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0")); + MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"), + MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1")); } [(set_attr "type" "branch") (set_attr "mode" "none") @@ -5224,18 +5224,18 @@ [(set (pc) (if_then_else (equality_op (zero_extract:GPR - (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 0 "register_operand" "d") (const_int 1) (match_operand 2 "const_int_operand" "")) (const_int 0)) (pc) - (label_ref (match_operand 0 ""))))] + (label_ref (match_operand 1 ""))))] "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" { return mips_output_conditional_branch (insn, operands, - MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"), - MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0")); + MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"), + MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1")); } [(set_attr "type" "branch") (set_attr "mode" "none") |
