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| author | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-10-07 19:25:54 +0000 |
|---|---|---|
| committer | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-10-07 19:25:54 +0000 |
| commit | e18a9aa09e0d81d580eb4a7e2986520bc9549436 (patch) | |
| tree | 63501f8b6661a6f72597444aeb019f97525e8329 | |
| parent | c918d62e2bf8b5e6448f7cb13f9c89959a2e53ff (diff) | |
| download | ppe42-gcc-e18a9aa09e0d81d580eb4a7e2986520bc9549436.tar.gz ppe42-gcc-e18a9aa09e0d81d580eb4a7e2986520bc9549436.zip | |
Comment out peepholes that generate buggy code
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@29858 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 44 |
2 files changed, 27 insertions, 22 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 06bebfcb6cb..29f74543d3c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Thu Oct 7 15:23:28 1999 Michael Meissner <meissner@cygnus.com> + + * alpha.md (peephole2's): Comment out peephole2's that generate + buggy code. + Thu Oct 7 12:00:53 1999 Richard Henderson <rth@cygnus.com> * genrecog.c (add_to_sequence): Disable mode check for diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index ab7dcb3b967..4fe909df2bd 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -5407,25 +5407,25 @@ ;; Optimize sign-extension of SImode loads. This shows up in the wake of ;; reload when converting fp->int. -(define_peephole2 - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:SI 1 "memory_operand" "m")) - (set (match_operand:DI 2 "register_operand" "=r") - (sign_extend:DI (match_dup 0)))] - "rtx_equal_p (operands[0], operands[2]) - || reg_dead_p (insn, operands[0])" - [(set (match_dup 2) - (sign_extend:DI (match_dup 1)))] - "") - -(define_peephole2 - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operand:SI 1 "hard_fp_register_operand" "f")) - (set (match_operand:DI 2 "register_operand" "=r") - (sign_extend:DI (match_dup 0)))] - "TARGET_FIX - && (rtx_equal_p (operands[0], operands[2]) - || reg_dead_p (insn, operands[0]))" - [(set (match_dup 2) - (sign_extend:DI (match_dup 1)))] - "") +;(define_peephole2 +; [(set (match_operand:SI 0 "register_operand" "=r") +; (match_operand:SI 1 "memory_operand" "m")) +; (set (match_operand:DI 2 "register_operand" "=r") +; (sign_extend:DI (match_dup 0)))] +; "rtx_equal_p (operands[0], operands[2]) +; || reg_dead_p (insn, operands[0])" +; [(set (match_dup 2) +; (sign_extend:DI (match_dup 1)))] +; "") +; +;(define_peephole2 +; [(set (match_operand:SI 0 "register_operand" "=r") +; (match_operand:SI 1 "hard_fp_register_operand" "f")) +; (set (match_operand:DI 2 "register_operand" "=r") +; (sign_extend:DI (match_dup 0)))] +; "TARGET_FIX +; && (rtx_equal_p (operands[0], operands[2]) +; || reg_dead_p (insn, operands[0]))" +; [(set (match_dup 2) +; (sign_extend:DI (match_dup 1)))] +; "") |
