Add ppe405 and ppe42 cpu types

8 files changed, 146 insertions, 112 deletions

diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md
index b2a83b163f7..bd6e7b60db0 100644
--- a/gcc/config/rs6000/40x.md
+++ b/gcc/config/rs6000/40x.md
@@ -28,34 +28,34 @@
 (define_insn_reservation "ppc403-load" 2
   (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
 			load_l,store_c,sync")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "iu_40x")
 
 (define_insn_reservation "ppc403-store" 2
   (and (eq_attr "type" "store,store_ux,store_u")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "iu_40x")
 
 (define_insn_reservation "ppc403-integer" 1
   (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
                         var_shift_rotate,cntlz,exts,isel")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "iu_40x")
 
 (define_insn_reservation "ppc403-two" 1
   (and (eq_attr "type" "two")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "iu_40x,iu_40x")
 
 (define_insn_reservation "ppc403-three" 1
   (and (eq_attr "type" "three")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "iu_40x,iu_40x,iu_40x")
 
 (define_insn_reservation "ppc403-compare" 3
   (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
                         var_delayed_compare")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "iu_40x,nothing,bpu_40x")
 
 (define_insn_reservation "ppc403-imul" 4
@@ -85,36 +85,36 @@
 
 (define_insn_reservation "ppc403-mfcr" 2
   (and (eq_attr "type" "mfcr")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "iu_40x")
 
 (define_insn_reservation "ppc403-mtcr" 3
   (and (eq_attr "type" "mtcr")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "iu_40x")
 
 (define_insn_reservation "ppc403-mtjmpr" 4
   (and (eq_attr "type" "mtjmpr")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "iu_40x")
 
 (define_insn_reservation "ppc403-mfjmpr" 2
   (and (eq_attr "type" "mfjmpr")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "iu_40x")
 
 (define_insn_reservation "ppc403-jmpreg" 1
   (and (eq_attr "type" "jmpreg,branch,isync")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "bpu_40x")
 
 (define_insn_reservation "ppc403-cr" 2
   (and (eq_attr "type" "cr_logical,delayed_cr")
-       (eq_attr "cpu" "ppc403,ppc405"))
+       (eq_attr "cpu" "ppc403,ppc405,ppe405,ppe42"))
   "bpu_40x")
 
 (define_insn_reservation "ppc405-float" 11
   (and (eq_attr "type" "fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,\
 			fpcompare,fp,dmul,sdiv,ddiv")
-       (eq_attr "cpu" "ppc405"))
+       (eq_attr "cpu" "ppc405,ppe405,ppe42"))
   "fpu_405*10")
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 5e8bfea1713..494fd81f00a 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -413,6 +413,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
   /* Used by lwarx/stwcx. errata work-around.  */
   if (rs6000_cpu == PROCESSOR_PPC405)
     builtin_define ("__PPC405__");
+  if (rs6000_cpu == PROCESSOR_PPE405 || rs6000_cpu == PROCESSOR_PPE42)
+    builtin_define ("__PPE42__");
   /* Used by libstdc++.  */
   if (TARGET_NO_LWSYNC)
     builtin_define ("__NO_LWSYNC__");
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 98b738ff104..c39457681af 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -117,6 +117,8 @@ RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
 RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
 RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT)
 RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
+RS6000_CPU ("ppe405", PROCESSOR_PPE405, MASK_SOFT_FLOAT)
+RS6000_CPU ("ppe42", PROCESSOR_PPE42, MASK_SOFT_FLOAT)
 RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
 RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
 RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 72151d88403..4f226723469 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -43,6 +43,8 @@ enum processor_type
 
    PROCESSOR_PPC403,
    PROCESSOR_PPC405,
+   PROCESSOR_PPE405,
+   PROCESSOR_PPE42,
    PROCESSOR_PPC440,
    PROCESSOR_PPC476,
 
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 85678d2bc6a..de022c8fca2 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -39,152 +39,158 @@ EnumValue
 Enum(rs6000_cpu_opt_value) String(405fp) Value(3)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(440) Value(4)
+Enum(rs6000_cpu_opt_value) String(ppe405) Value(4)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(440fp) Value(5)
+Enum(rs6000_cpu_opt_value) String(ppe42) Value(5)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(464) Value(6)
+Enum(rs6000_cpu_opt_value) String(440) Value(6)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(464fp) Value(7)
+Enum(rs6000_cpu_opt_value) String(440fp) Value(7)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(476) Value(8)
+Enum(rs6000_cpu_opt_value) String(464) Value(8)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(476fp) Value(9)
+Enum(rs6000_cpu_opt_value) String(464fp) Value(9)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(505) Value(10)
+Enum(rs6000_cpu_opt_value) String(476) Value(10)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(601) Value(11)
+Enum(rs6000_cpu_opt_value) String(476fp) Value(11)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(602) Value(12)
+Enum(rs6000_cpu_opt_value) String(505) Value(12)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(603) Value(13)
+Enum(rs6000_cpu_opt_value) String(601) Value(13)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(603e) Value(14)
+Enum(rs6000_cpu_opt_value) String(602) Value(14)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(604) Value(15)
+Enum(rs6000_cpu_opt_value) String(603) Value(15)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(604e) Value(16)
+Enum(rs6000_cpu_opt_value) String(603e) Value(16)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(620) Value(17)
+Enum(rs6000_cpu_opt_value) String(604) Value(17)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(630) Value(18)
+Enum(rs6000_cpu_opt_value) String(604e) Value(18)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(740) Value(19)
+Enum(rs6000_cpu_opt_value) String(620) Value(19)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(7400) Value(20)
+Enum(rs6000_cpu_opt_value) String(630) Value(20)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(7450) Value(21)
+Enum(rs6000_cpu_opt_value) String(740) Value(21)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(750) Value(22)
+Enum(rs6000_cpu_opt_value) String(7400) Value(22)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(801) Value(23)
+Enum(rs6000_cpu_opt_value) String(7450) Value(23)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(821) Value(24)
+Enum(rs6000_cpu_opt_value) String(750) Value(24)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(823) Value(25)
+Enum(rs6000_cpu_opt_value) String(801) Value(25)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(8540) Value(26)
+Enum(rs6000_cpu_opt_value) String(821) Value(26)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(8548) Value(27)
+Enum(rs6000_cpu_opt_value) String(823) Value(27)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(a2) Value(28)
+Enum(rs6000_cpu_opt_value) String(8540) Value(28)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(e300c2) Value(29)
+Enum(rs6000_cpu_opt_value) String(8548) Value(29)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(e300c3) Value(30)
+Enum(rs6000_cpu_opt_value) String(a2) Value(30)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(e500mc) Value(31)
+Enum(rs6000_cpu_opt_value) String(e300c2) Value(31)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(e500mc64) Value(32)
+Enum(rs6000_cpu_opt_value) String(e300c3) Value(32)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(e5500) Value(33)
+Enum(rs6000_cpu_opt_value) String(e500mc) Value(33)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(e6500) Value(34)
+Enum(rs6000_cpu_opt_value) String(e500mc64) Value(34)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(860) Value(35)
+Enum(rs6000_cpu_opt_value) String(e5500) Value(35)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(970) Value(36)
+Enum(rs6000_cpu_opt_value) String(e6500) Value(36)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(cell) Value(37)
+Enum(rs6000_cpu_opt_value) String(860) Value(37)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(ec603e) Value(38)
+Enum(rs6000_cpu_opt_value) String(970) Value(38)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(G3) Value(39)
+Enum(rs6000_cpu_opt_value) String(cell) Value(39)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(G4) Value(40)
+Enum(rs6000_cpu_opt_value) String(ec603e) Value(40)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(G5) Value(41)
+Enum(rs6000_cpu_opt_value) String(G3) Value(41)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(titan) Value(42)
+Enum(rs6000_cpu_opt_value) String(G4) Value(42)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power3) Value(43)
+Enum(rs6000_cpu_opt_value) String(G5) Value(43)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power4) Value(44)
+Enum(rs6000_cpu_opt_value) String(titan) Value(44)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power5) Value(45)
+Enum(rs6000_cpu_opt_value) String(power3) Value(45)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power5+) Value(46)
+Enum(rs6000_cpu_opt_value) String(power4) Value(46)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power6) Value(47)
+Enum(rs6000_cpu_opt_value) String(power5) Value(47)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power6x) Value(48)
+Enum(rs6000_cpu_opt_value) String(power5+) Value(48)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power7) Value(49)
+Enum(rs6000_cpu_opt_value) String(power6) Value(49)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(power8) Value(50)
+Enum(rs6000_cpu_opt_value) String(power6x) Value(50)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc) Value(51)
+Enum(rs6000_cpu_opt_value) String(power7) Value(51)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64) Value(52)
+Enum(rs6000_cpu_opt_value) String(power8) Value(52)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(rs64) Value(53)
+Enum(rs6000_cpu_opt_value) String(powerpc) Value(53)
+
+EnumValue
+Enum(rs6000_cpu_opt_value) String(powerpc64) Value(54)
+
+EnumValue
+Enum(rs6000_cpu_opt_value) String(rs64) Value(55)
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ff292750628..34afd972f0f 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -3849,6 +3849,8 @@ rs6000_option_override_internal (bool global_init_p)
 	break;
 
       case PROCESSOR_PPC405:
+      case PROCESSOR_PPE405:
+      case PROCESSOR_PPE42:
 	rs6000_cost = &ppc405_cost;
 	break;
 
@@ -19147,10 +19149,9 @@ rs6000_emit_cbranch (enum machine_mode mode, rtx operands[])
 
   loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
 
-  // TODO if not PPE42
-  // Split the compare and branch if not optimized for size
+  // Split the compare and branch if not PPE42 or not optimized for size
   // or can't meet the constraints of fused compare-branch.
-  if(!optimize_size ||
+  if( (rs6000_cpu != PROCESSOR_PPE42) || !optimize_size ||
      ((GET_CODE (operands[2]) == CONST_INT) &&
      ((INTVAL(operands[2]) < 0) || (INTVAL(operands[2]) > 31))))
   {
@@ -20502,6 +20503,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
   int nregs;
 
   // if ppe42 then use 64bit load/store
+  if(rs6000_cpu == PROCESSOR_PPE42)
   {
       rtx reg_op = NULL;
       rtx mem_op = NULL;
@@ -23403,32 +23405,38 @@ rs6000_emit_prologue (void)
       if ((strategy & SAVE_INLINE_GPRS))
 	{
         // ppe42 - use 64 bit stores  - No evidence that this gained anything
-        i = 0;
-        if((info->first_gp_reg_save & 0x01) == 1) // odd reg num
+        if(rs6000_cpu == PROCESSOR_PPE42)
         {
-            if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save))
-	            emit_frame_save (spe_save_area_ptr,
-                                 reg_mode,
-                                 info->first_gp_reg_save,
-	                             (info->spe_gp_save_offset + save_off),
-                        	     sp_off - save_off);
-            i = 1;
+      i = 0;
+      if((info->first_gp_reg_save & 0x01) == 1) // odd reg num
+      {
+          if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save))
+	          emit_frame_save (spe_save_area_ptr,
+                               reg_mode,
+                               info->first_gp_reg_save,
+	                           (info->spe_gp_save_offset + save_off),
+                        	    sp_off - save_off);
+             i = 1;
+      }
+      for(;i < 32 - info->first_gp_reg_save; i += 2)
+          if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
+              emit_frame_save (spe_save_area_ptr, DImode,
+                               info->first_gp_reg_save + i,
+                               (info->spe_gp_save_offset + save_off
+                                + reg_size * i),
+                               sp_off - save_off);
+        }
+        else
+        {
+
+	  for (i = 0; i < 32 - info->first_gp_reg_save; i++)
+	    if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
+	      emit_frame_save (spe_save_area_ptr, reg_mode,
+      		       info->first_gp_reg_save + i,
+	  	       (info->spe_gp_save_offset + save_off
+				+ reg_size * i),
+			       sp_off - save_off);
         }
-        for(;i < 32 - info->first_gp_reg_save; i += 2)
-            if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
-                emit_frame_save (spe_save_area_ptr, DImode,
-                                 info->first_gp_reg_save + i,
-                                 (info->spe_gp_save_offset + save_off
-                                  + reg_size * i),
-                                 sp_off - save_off);
-
-	  //for (i = 0; i < 32 - info->first_gp_reg_save; i++)
-	  //  if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
-	  //    emit_frame_save (spe_save_area_ptr, reg_mode,
-      //		       info->first_gp_reg_save + i,
-	  //	       (info->spe_gp_save_offset + save_off
-	//			+ reg_size * i),
-	//		       sp_off - save_off);
 	}
       else
 	{
@@ -23511,6 +23519,8 @@ rs6000_emit_prologue (void)
       int i;
 
       // ppe42 save using 64-bit stores
+     if(rs6000_cpu == PROCESSOR_PPE42)
+     {
       i = 0;
       if((info->first_gp_reg_save & 0x1) == 1) // odd regnum
       {
@@ -23528,13 +23538,17 @@ rs6000_emit_prologue (void)
                                info->first_gp_reg_save + i,
                                info->gp_save_offset + frame_off + reg_size * i,
                                sp_off - frame_off);
+     }
+     else
+     {
 
-//      for (i = 0; i < 32 - info->first_gp_reg_save; i++)
-//	if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
-//	  emit_frame_save (frame_reg_rtx, reg_mode,
-//			   info->first_gp_reg_save + i,
-//			   info->gp_save_offset + frame_off + reg_size * i,
-//			   sp_off - frame_off);
+      for (i = 0; i < 32 - info->first_gp_reg_save; i++)
+	if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
+	  emit_frame_save (frame_reg_rtx, reg_mode,
+			   info->first_gp_reg_save + i,
+			   info->gp_save_offset + frame_off + reg_size * i,
+			   sp_off - frame_off);
+     }
     }
 
   if (crtl->calls_eh_return)
@@ -24962,6 +24976,8 @@ rs6000_emit_epilogue (int sibcall)
   else
     {
         // ppe42 - use 64 bit loads
+      if(rs6000_cpu == PROCESSOR_PPE42)
+      {
         i = 0;
         if((info->first_gp_reg_save & 0x1) == 1) // odd reg
         {
@@ -24972,7 +24988,6 @@ rs6000_emit_epilogue (int sibcall)
                             info->gp_save_offset + frame_off));
             i = 1;
         }
-        reg_mode = DImode;
         for(; i < 32 - info->first_gp_reg_save; i += 2)
         {
 	        if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
@@ -24980,8 +24995,8 @@ rs6000_emit_epilogue (int sibcall)
                 emit_insn
                     (gen_rtx_SET
                      (VOIDmode,
-                      gen_rtx_REG(reg_mode, info->first_gp_reg_save + i),
-                      gen_frame_mem(reg_mode,
+                      gen_rtx_REG(DImode, info->first_gp_reg_save + i),
+                      gen_frame_mem(DImode,
                                     gen_rtx_PLUS
                                     (Pmode,
                                      frame_reg_rtx,
@@ -24992,15 +25007,17 @@ rs6000_emit_epilogue (int sibcall)
 
             }
         }
-        reg_mode = Pmode;
-/*
+      }
+      else
+      {
+
       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
 	if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
 	  emit_insn (gen_frame_load
 		     (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
 		      frame_reg_rtx,
 		      info->gp_save_offset + frame_off + reg_size * i));
-              */
+      }
     }
 
   if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
@@ -33316,8 +33333,8 @@ bool mem_contiguous(rtx mem1, rtx mem2)
     int offset1 = -1;
     int offset2 = -2;
 
-    debug_rtx(mem1);
-    debug_rtx(mem2);
+    //debug_rtx(mem1);
+    //debug_rtx(mem2);
     int code = GET_CODE(XEXP(mem1,0));
     if(code == PLUS)
     {
@@ -33355,7 +33372,7 @@ bool mem_contiguous(rtx mem1, rtx mem2)
     {
         result = true;
     }
-    fprintf(stderr,"Return %s\n",(result ? "true":"false"));
+    // fprintf(stderr,"Return %s\n",(result ? "true":"false"));
     return result;
 }
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f85327ae357..1d01f725523 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -192,7 +192,7 @@
 (define_attr "cpu"
   "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
    ppc750,ppc7400,ppc7450,
-   ppc403,ppc405,ppc440,ppc476,
+   ppc403,ppc405,ppe405,ppe42,ppc440,ppc476,
    ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
    power4,power5,power6,power7,power8,
    rs64a,mpccore,cell,ppca2,titan"
@@ -13516,7 +13516,8 @@
           (match_operand:SI 1 "offsettable_mem_operand" "m"))
      (set (match_operand:SI 2 "gpc_reg_operand" "r")
           (match_operand:SI 3 "offsettable_mem_operand" "m"))]
-"((REGNO(operands[0]) + 1) == REGNO(operands[2])) &&
+"((rs6000_cpu == PROCESSOR_PPE42) &&
+ (REGNO(operands[0]) + 1) == REGNO(operands[2])) &&
   mem_contiguous(operands[1],operands[3])"
 "lvd %0, %1 #peephole %0 %1 %2 %3"
 [(set_attr "type" "load")])
@@ -13526,7 +13527,8 @@
           (match_operand:SI 1 "offsettable_mem_operand" "m"))
      (set (match_operand:SI 2 "gpc_reg_operand" "r")
           (match_operand:SI 3 "offsettable_mem_operand" "m"))]
-"((REGNO(operands[0]) - 1) == REGNO(operands[2])) &&
+"((rs6000_cpu == PROCESSOR_PPE42) &&
+ (REGNO(operands[0]) - 1) == REGNO(operands[2])) &&
   mem_contiguous(operands[3],operands[1])"
 "lvd %2, %3 #peephole %0 %1 %2 %3"
 [(set_attr "type" "load")])
@@ -13536,7 +13538,8 @@
           (match_operand:SI 1 "gpc_reg_operand" "r"))
      (set (match_operand:SI 2 "offsettable_mem_operand" "m")
           (match_operand:SI 3 "gpc_reg_operand" "r"))]
-"((REGNO(operands[1]) + 1) == REGNO(operands[3])) &&
+"((rs6000_cpu == PROCESSOR_PPE42) &&
+ (REGNO(operands[1]) + 1) == REGNO(operands[3])) &&
   mem_contiguous(operands[0],operands[2])"
 "stvd %1, %0 # peephole %0 %1 %2 %3"
 [(set_attr "type" "store")])
@@ -13546,7 +13549,8 @@
           (match_operand:SI 1 "gpc_reg_operand" "r"))
      (set (match_operand:SI 2 "offsettable_mem_operand" "m")
           (match_operand:SI 3 "gpc_reg_operand" "r"))]
-"((REGNO(operands[1]) - 1) == REGNO(operands[3])) &&
+"((rs6000_cpu == PROCESSOR_PPE42) &&
+ (REGNO(operands[1]) - 1) == REGNO(operands[3])) &&
   mem_contiguous(operands[2],operands[0])"
 "stvd %3, %2 # peephole %0 %1 %2 %3"
 [(set_attr "type" "store")])
@@ -14739,7 +14743,7 @@
                          (match_operand:GPR 3 "reg_or_short_operand" "rI")])
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
-  "optimize_size"
+  "(rs6000_cpu == PROCESSOR_PPE42) && optimize_size"
   "*
 {
     return output_fused_cbranch (operands, \"%l0\", insn);
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index bea8be20aff..ada0fdf160c 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -18942,7 +18942,8 @@ and to treat GPRs as 64-bit, doubleword quantities.  GCC defaults to
 Set architecture type, register usage, and
 instruction scheduling parameters for machine type @var{cpu_type}.
 Supported values for @var{cpu_type} are @samp{401}, @samp{403},
-@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{464}, @samp{464fp},
+@samp{405}, @samp{405fp}, @samp{ppe405}, @samp{ppe42}, @samp{440},
+@samp{440fp}, @samp{464}, @samp{464fp},
 @samp{476}, @samp{476fp}, @samp{505}, @samp{601}, @samp{602}, @samp{603},
 @samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740},
 @samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},