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| author | law <law@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-08-25 08:21:46 +0000 |
|---|---|---|
| committer | law <law@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-08-25 08:21:46 +0000 |
| commit | d93cb711178b067014a59ed96f4a4349987f1ba4 (patch) | |
| tree | 8c8efe8c50b6f7e339038dc58cd5a032218a1826 | |
| parent | bb55524f6f742883baabdcf585617ee24d442c6a (diff) | |
| download | ppe42-gcc-d93cb711178b067014a59ed96f4a4349987f1ba4.tar.gz ppe42-gcc-d93cb711178b067014a59ed96f4a4349987f1ba4.zip | |
Fix typo.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@28852 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/NEWS | 2 | ||||
| -rw-r--r-- | gcc/config/ns32k/ns32k.md | 4 | ||||
| -rw-r--r-- | gcc/f/ffe.texi | 2 | ||||
| -rw-r--r-- | gcc/tm.texi | 2 |
4 files changed, 5 insertions, 5 deletions
@@ -68,7 +68,7 @@ Build time improvements for targets which support lots of sched parameters (alpha and mips primarily). Compile time for certain programs using large constant initializers has been -improved (effects glibc significantly). +improved (affects glibc significantly). Plus an incredible number of infrastructure changes, warning fixes, bugfixes and local optimizations. diff --git a/gcc/config/ns32k/ns32k.md b/gcc/config/ns32k/ns32k.md index 69ba564638b..c5fe1602b43 100644 --- a/gcc/config/ns32k/ns32k.md +++ b/gcc/config/ns32k/ns32k.md @@ -1335,7 +1335,7 @@ DONE; }") -;; deiw wants two hi's in seperate registers or else they can be adjacent +;; deiw wants two hi's in separate registers or else they can be adjacent ;; in memory. DI mode will ensure two registers are available, but if we ;; want to allow memory as an operand we would need SI mode. There is no ;; way to do this, so just restrict operand 0 and 1 to be in registers. @@ -1392,7 +1392,7 @@ DONE; }") -;; deib wants two qi's in seperate registers or else they can be adjacent +;; deib wants two qi's in separate registers or else they can be adjacent ;; in memory. DI mode will ensure two registers are available, but if we ;; want to allow memory as an operand we would need HI mode. There is no ;; way to do this, so just restrict operand 0 and 1 to be in registers. diff --git a/gcc/f/ffe.texi b/gcc/f/ffe.texi index e30333280d1..630fe35b862 100644 --- a/gcc/f/ffe.texi +++ b/gcc/f/ffe.texi @@ -640,7 +640,7 @@ and except it also provides automatic conversion of tabs and ignoring of newline-related carriage returns. -It also effects the ``pure visual'' model, +It also affects the ``pure visual'' model, by which is meant that a user viewing his code in a typical text editor (assuming it's not preprocessed via @code{g77stripcard} or similar) diff --git a/gcc/tm.texi b/gcc/tm.texi index e181371bcd0..ed286fe2010 100644 --- a/gcc/tm.texi +++ b/gcc/tm.texi @@ -2981,7 +2981,7 @@ stack. @item LOAD_ARGS_REVERSED If defined, the order in which arguments are loaded into their respective argument registers is reversed so that the last -argument is loaded first. This macro only effects arguments +argument is loaded first. This macro only affects arguments passed in registers. @end table |
