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authornickc <nickc@138bc75d-0d04-0410-961f-82ee72b054a4>2003-03-13 13:27:17 +0000
committernickc <nickc@138bc75d-0d04-0410-961f-82ee72b054a4>2003-03-13 13:27:17 +0000
commitd4309f760fba804f8263ef9c36950ec6fc7cb42b (patch)
treead8b08cb89de02c49a6dec03cd5fd5d84a2d31fe
parentf29bf0d0fe9f1a648bbc6e1f182f69588e38d58d (diff)
downloadppe42-gcc-d4309f760fba804f8263ef9c36950ec6fc7cb42b.tar.gz
ppe42-gcc-d4309f760fba804f8263ef9c36950ec6fc7cb42b.zip
Remove redundant writeback test in previous delta.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@64307 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/config/arm/arm.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index b7c85911ba8..79088e3d5b9 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7207,11 +7207,14 @@ print_multi_reg (stream, instr, reg, mask)
fprintf (stream, "}");
/* Add a ^ character for the 26-bit ABI, but only if we were loading
- the PC or not updating the stack pointer. Otherwise we generate
- an UNPREDICTABLE instruction. */
+ the PC. Otherwise we would generate an UNPREDICTABLE instruction.
+ Strictly speaking the instruction would be unpredicatble only if
+ we were writing back the base register as well, but since we never
+ want to generate an LDM type 2 instruction (register bank switching)
+ which is what you get if the PC is not being loaded, we do not need
+ to check for writeback. */
if (! TARGET_APCS_32
- && (((mask & (1 << PC_REGNUM)) != 0)
- || strchr (instr, '!') == NULL))
+ && ((mask & (1 << PC_REGNUM)) != 0))
fprintf (stream, "^");
fprintf (stream, "\n");
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