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author | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-11-30 15:48:13 +0000 |
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committer | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-11-30 15:48:13 +0000 |
commit | bef6482d2265ece9aa0b71096d0d1a662e29b25f (patch) | |
tree | 31cbdf78dcce2a3a65b85460bdd36ad19c803e73 | |
parent | a3664b60752da4e34271caa07777533bd6dfd98c (diff) | |
download | ppe42-gcc-bef6482d2265ece9aa0b71096d0d1a662e29b25f.tar.gz ppe42-gcc-bef6482d2265ece9aa0b71096d0d1a662e29b25f.zip |
sparc: Convert to atomic_load/store.
* config/sparc/predicates.md (register_or_v9_zero_operand): New.
* config/sparc/sparc.md (UNSPEC_ATOMIC): New.
* config/sparc/sync.md (atomic_load<I>): New.
(atomic_loaddi_1, atomic_store<I>, atomic_storedi_1): New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@181849 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r-- | gcc/ChangeLog | 7 | ||||
-rw-r--r-- | gcc/config/sparc/predicates.md | 5 | ||||
-rw-r--r-- | gcc/config/sparc/sparc.md | 1 | ||||
-rw-r--r-- | gcc/config/sparc/sync.md | 59 |
4 files changed, 72 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eee535f9047..e48130eb0ee 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2011-11-30 Richard Henderson <rth@redhat.com> + * config/sparc/predicates.md (register_or_v9_zero_operand): New. + * config/sparc/sparc.md (UNSPEC_ATOMIC): New. + * config/sparc/sync.md (atomic_load<I>): New. + (atomic_loaddi_1, atomic_store<I>, atomic_storedi_1): New. + +2011-11-30 Richard Henderson <rth@redhat.com> + * config/sparc/predicates.md (zero_or_v7_operand): New. * config/sparc/sparc.c (sparc_emit_membar_for_model): New. * config/sparc/sparc-protos.h: Update. diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md index 047b21786fc..a9207beaadb 100644 --- a/gcc/config/sparc/predicates.md +++ b/gcc/config/sparc/predicates.md @@ -239,6 +239,11 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "const_zero_operand"))) +(define_predicate "register_or_v9_zero_operand" + (ior (match_operand 0 "register_operand") + (and (match_test "TARGET_V9") + (match_operand 0 "const_zero_operand")))) + ;; Return true if OP is either the zero constant, the all-ones ;; constant, or a register. (define_predicate "register_or_zero_or_all_ones_operand" diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index c059dc5e730..37ac1701b69 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -41,6 +41,7 @@ (UNSPEC_MOVE_GOTDATA 19) (UNSPEC_MEMBAR 20) + (UNSPEC_ATOMIC 21) (UNSPEC_TLSGD 30) (UNSPEC_TLSLDM 31) diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md index e22f5167fec..e2f45968666 100644 --- a/gcc/config/sparc/sync.md +++ b/gcc/config/sparc/sync.md @@ -102,6 +102,65 @@ "membar\t%1" [(set_attr "type" "multi")]) +(define_expand "atomic_load<mode>" + [(match_operand:I 0 "register_operand" "") + (match_operand:I 1 "memory_operand" "") + (match_operand:SI 2 "const_int_operand" "")] + "" +{ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + + sparc_emit_membar_for_model (model, 1, 1); + + if (TARGET_ARCH64 || <MODE>mode != DImode) + emit_move_insn (operands[0], operands[1]); + else + emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); + + sparc_emit_membar_for_model (model, 1, 2); + DONE; +}) + +(define_insn "atomic_loaddi_1" + [(set (match_operand:DI 0 "register_operand" "=U,?*f") + (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")] + UNSPEC_ATOMIC))] + "!TARGET_ARCH64" + "ldd\t%1, %0" + [(set_attr "type" "load,fpload")]) + +(define_expand "atomic_store<mode>" + [(match_operand:I 0 "register_operand" "") + (match_operand:I 1 "memory_operand" "") + (match_operand:SI 2 "const_int_operand" "")] + "" +{ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + + sparc_emit_membar_for_model (model, 2, 1); + + if (TARGET_ARCH64 || <MODE>mode != DImode) + emit_move_insn (operands[0], operands[1]); + else + emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); + + sparc_emit_membar_for_model (model, 2, 2); + DONE; +}) + +(define_insn "atomic_storedi_1" + [(set (match_operand:DI 0 "memory_operand" "=m,m,m") + (unspec:DI + [(match_operand:DI 1 "register_or_v9_zero_operand" "J,U,?*f")] + UNSPEC_ATOMIC))] + "!TARGET_ARCH64" + "@ + stx\t%r1, %0 + std\t%1, %0 + std\t%1, %0" + [(set_attr "type" "store,store,fpstore") + (set_attr "cpu_feature" "v9,*,*")]) + ;;;;;;;; (define_expand "sync_compare_and_swap<mode>" |