gcc/

	* config/rs6000/altivec.md (altivec_lvsl, altivec_lvsr): Add mode.
	(altivec_vsumsws_nomode): Delete.
	(reduc_splus_<mode>, reduc_uplus_<mode>): Call gen_altivec_vsumsws
	instead of gen_altivec_vsumsws_nomode.
	(altivec_lvlx, altivec_lvlxl, altivec_lvrx, altivec_lvrxl):
	Add mode.
	* config/rs6000/rs6000.md (probe_stack): Rename to...
	(probe_stack_<mode>): ... this.  Add mode.  Change pattern to
	use std instead of stw when appropriate.
	(probe_stack): New expander.
	(move_from_CR_ov_bit): Add mode.
	(splitter for compare_plus_ne0_<mode>, splitter for
	compare_plus_ne0_<mode>_1): Remove constraints.
	* config/rs6000/sync.md (loadsync): Rename to...
	(loadsync_<mode>): ... this.  Add mode.
	(atomic_load<mode>): Adjust.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@192568 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 67 insertions, 35 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 146355041d7..8da1c078483 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2012-10-18  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/altivec.md (altivec_lvsl, altivec_lvsr): Add mode.
+	(altivec_vsumsws_nomode): Delete.
+	(reduc_splus_<mode>, reduc_uplus_<mode>): Call gen_altivec_vsumsws
+	instead of gen_altivec_vsumsws_nomode.
+	(altivec_lvlx, altivec_lvlxl, altivec_lvrx, altivec_lvrxl):
+	Add mode.
+	* config/rs6000/rs6000.md (probe_stack): Rename to...
+	(probe_stack_<mode>): ... this.  Add mode.  Change pattern to
+	use std instead of stw when appropriate.
+	(probe_stack): New expander.
+	(move_from_CR_ov_bit): Add mode.
+	(splitter for compare_plus_ne0_<mode>, splitter for
+	compare_plus_ne0_<mode>_1): Remove constraints.
+	* config/rs6000/sync.md (loadsync): Rename to...
+	(loadsync_<mode>): ... this.  Add mode.
+	(atomic_load<mode>): Adjust.
+
 2012-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* loop-invariant.c: Include target.h.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 8c168c85daf..7ca496f937a 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1674,14 +1674,16 @@
 
 (define_insn "altivec_lvsl"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
-	(unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
+	(unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "Z")]
+		      UNSPEC_LVSL))]
   "TARGET_ALTIVEC"
   "lvsl %0,%y1"
   [(set_attr "type" "vecload")])
 
 (define_insn "altivec_lvsr"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
-	(unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
+	(unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "Z")]
+		      UNSPEC_LVSR))]
   "TARGET_ALTIVEC"
   "lvsr %0,%y1"
   [(set_attr "type" "vecload")])
@@ -1831,47 +1833,37 @@
   operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
 })
 
-(define_insn "altivec_vsumsws_nomode"
-  [(set (match_operand 0 "register_operand" "=v")
-        (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")]
-		     UNSPEC_VSUMSWS))
-   (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-  "TARGET_ALTIVEC"
-  "vsumsws %0,%1,%2"
-  [(set_attr "type" "veccomplex")])
-
 (define_expand "reduc_splus_<mode>"
   [(set (match_operand:VIshort 0 "register_operand" "=v")
         (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
 			UNSPEC_REDUC_PLUS))]
   "TARGET_ALTIVEC"
-  "
-{ 
+{
   rtx vzero = gen_reg_rtx (V4SImode);
   rtx vtmp1 = gen_reg_rtx (V4SImode);
+  rtx dest = gen_lowpart (V4SImode, operands[0]);
 
   emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
   emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
-  emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
+  emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero));
   DONE;
-}")
+})
 
 (define_expand "reduc_uplus_v16qi"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
 		      UNSPEC_REDUC_PLUS))]
   "TARGET_ALTIVEC"
-  "
 {
   rtx vzero = gen_reg_rtx (V4SImode);
   rtx vtmp1 = gen_reg_rtx (V4SImode);
+  rtx dest = gen_lowpart (V4SImode, operands[0]);
 
   emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
   emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
-  emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
+  emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero));
   DONE;
-}")
+})
 
 (define_expand "neg<mode>2"
   [(use (match_operand:VI 0 "register_operand" ""))
@@ -2348,7 +2340,7 @@
 ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell.
 (define_insn "altivec_lvlx"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
-        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
+        (unspec:V16QI [(match_operand:BLK 1 "memory_operand" "Z")]
 		      UNSPEC_LVLX))]
   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
   "lvlx %0,%y1"
@@ -2356,7 +2348,7 @@
 
 (define_insn "altivec_lvlxl"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
-        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
+        (unspec:V16QI [(match_operand:BLK 1 "memory_operand" "Z")]
 		      UNSPEC_LVLXL))]
   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
   "lvlxl %0,%y1"
@@ -2364,7 +2356,7 @@
 
 (define_insn "altivec_lvrx"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
-        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
+        (unspec:V16QI [(match_operand:BLK 1 "memory_operand" "Z")]
 		      UNSPEC_LVRX))]
   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
   "lvrx %0,%y1"
@@ -2372,7 +2364,7 @@
 
 (define_insn "altivec_lvrxl"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
-        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
+        (unspec:V16QI [(match_operand:BLK 1 "memory_operand" "Z")]
 		      UNSPEC_LVRXL))]
   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
   "lvrxl %0,%y1"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5bf2fec18e4..2625bd72c07 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11134,15 +11134,26 @@
   ""
   "")
 
-(define_insn "probe_stack"
+(define_expand "probe_stack"
   [(set (match_operand 0 "memory_operand" "=m")
         (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
   ""
-  "*
+{
+  if (TARGET_64BIT)
+    emit_insn (gen_probe_stack_di (operands[0]));
+  else
+    emit_insn (gen_probe_stack_si (operands[0]));
+  DONE;
+})
+
+(define_insn "probe_stack_<mode>"
+  [(set (match_operand:P 0 "memory_operand" "=m")
+        (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
+  ""
 {
   operands[1] = gen_rtx_REG (Pmode, 0);
-  return \"stw%U0%X0 %1,%0\";
-}"
+  return "st<wd>%U0%X0 %1,%0";
+}
   [(set_attr "type" "store")
    (set_attr "length" "4")])
 
@@ -11560,7 +11571,8 @@
 ;; Same as above, but get the OV/ORDERED bit.
 (define_insn "move_from_CR_ov_bit"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
+	(unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
+		   UNSPEC_MV_CR_OV))]
   "TARGET_ISEL"
   "mfcr %0\;rlwinm %0,%0,%t1,1"
   [(set_attr "type" "mfcr")
@@ -12008,9 +12020,9 @@
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "r,r")
+	(compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
 			  (const_int 0))
-		    (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
+		    (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
    (clobber (match_scratch:P 3 ""))
    (clobber (match_scratch:P 4 ""))]
   "reload_completed"
@@ -12041,9 +12053,9 @@
 
 (define_split
   [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "r,r")
+	(compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
 			    (const_int 0))
-		      (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
+		      (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
    (clobber (match_scratch:P 3 ""))
    (clobber (match_scratch:P 4 ""))]
   "reload_completed"
diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md
index ab60cbcd483..42ac90373e5 100644
--- a/gcc/config/rs6000/sync.md
+++ b/gcc/config/rs6000/sync.md
@@ -100,8 +100,8 @@
 
 ;; The control dependency used for load dependency described
 ;; in B.2.3 of the Power ISA 2.06B.
-(define_insn "loadsync"
-  [(unspec_volatile:BLK [(match_operand 0 "register_operand" "r")]
+(define_insn "loadsync_<mode>"
+  [(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")]
 			UNSPECV_ISYNC)
    (clobber (match_scratch:CC 1 "=y"))]
   ""
@@ -129,7 +129,16 @@
     case MEMMODEL_CONSUME:
     case MEMMODEL_ACQUIRE:
     case MEMMODEL_SEQ_CST:
-      emit_insn (gen_loadsync (operands[0]));
+      if (GET_MODE (operands[0]) == QImode)
+	emit_insn (gen_loadsync_qi (operands[0]));
+      else if (GET_MODE (operands[0]) == HImode)
+	emit_insn (gen_loadsync_hi (operands[0]));
+      else if (GET_MODE (operands[0]) == SImode)
+	emit_insn (gen_loadsync_si (operands[0]));
+      else if (GET_MODE (operands[0]) == DImode)
+	emit_insn (gen_loadsync_di (operands[0]));
+      else
+	gcc_unreachable ();
       break;
     default:
       gcc_unreachable ();