* i386.c (ix86_expand_store_builtin): Always force op1 to register.

	(mov*_internal): Fix predicates; require one of operands to not be
	memory.
	(SSE?MMX move expanders):  Fix predicates; force one of operands to
	register.
	(SSE/MMX push patterns): Reorganize; fix x86-64 code generation.
	(movups/movupd/movdqu patterns): Force one of operands to not be
	memory.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@62339 138bc75d-0d04-0410-961f-82ee72b054a4

3 files changed, 130 insertions, 151 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d89b2153e9c..8deaf03973b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+Mon Feb  3 21:19:11 CET 2003  Jan Hubicka  <jh@suse.cz>
+
+	* i386.c (ix86_expand_store_builtin):  Always force op1 to register.
+	(mov*_internal): Fix predicates; require one of operands to not be
+	memory.
+	(SSE?MMX move expanders):  Fix predicates; force one of operands to
+	register.
+	(SSE/MMX push patterns): Reorganize; fix x86-64 code generation.
+	(movups/movupd/movdqu patterns): Force one of operands to not be
+	memory.
+
 2002-02-03  Roger Sayle  <roger@eyesopen.com>
 
 	* hooks.c (hook_rtx_rtx_identity): Generic hook function that
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 2f7a300f8ec..2d799bb653c 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -13469,9 +13469,7 @@ ix86_expand_store_builtin (icode, arglist)
     op1 = safe_vector_operand (op1, mode1);
 
   op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
-
-  if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
-    op1 = copy_to_mode_reg (mode1, op1);
+  op1 = copy_to_mode_reg (mode1, op1);
 
   pat = GEN_FCN (icode) (op0, op1);
   if (pat)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 4c8211356ee..292ddf371ba 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -18566,7 +18566,8 @@
 (define_insn "movv8qi_internal"
   [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
 	(match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))]
-  "TARGET_MMX"
+  "TARGET_MMX
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "movq\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmxmov")
    (set_attr "mode" "DI")])
@@ -18574,7 +18575,8 @@
 (define_insn "movv4hi_internal"
   [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
 	(match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))]
-  "TARGET_MMX"
+  "TARGET_MMX
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "movq\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmxmov")
    (set_attr "mode" "DI")])
@@ -18582,7 +18584,8 @@
 (define_insn "movv2si_internal"
   [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
 	(match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))]
-  "TARGET_MMX"
+  "TARGET_MMX
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "movq\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmxcvt")
    (set_attr "mode" "DI")])
@@ -18590,14 +18593,15 @@
 (define_insn "movv2sf_internal"
   [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
         (match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))]
-  "TARGET_3DNOW"
+  "TARGET_3DNOW
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "movq\\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmxcvt")
    (set_attr "mode" "DI")])
 
 (define_expand "movti"
-  [(set (match_operand:TI 0 "general_operand" "")
-	(match_operand:TI 1 "general_operand" ""))]
+  [(set (match_operand:TI 0 "nonimmediate_operand" "")
+	(match_operand:TI 1 "nonimmediate_operand" ""))]
   "TARGET_SSE || TARGET_64BIT"
 {
   if (TARGET_64BIT)
@@ -18610,7 +18614,8 @@
 (define_insn "movv2df_internal"
   [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
 	(match_operand:V2DF 1 "nonimmediate_operand" "xm,x"))]
-  "TARGET_SSE2"
+  "TARGET_SSE2
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   if (get_attr_mode (insn) == MODE_V4SF)
     return "movaps\t{%1, %0|%0, %1}";
@@ -18638,7 +18643,8 @@
 (define_insn "movv8hi_internal"
   [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
 	(match_operand:V8HI 1 "nonimmediate_operand" "xm,x"))]
-  "TARGET_SSE2"
+  "TARGET_SSE2
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   if (get_attr_mode (insn) == MODE_V4SF)
     return "movaps\t{%1, %0|%0, %1}";
@@ -18666,7 +18672,8 @@
 (define_insn "movv16qi_internal"
   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
 	(match_operand:V16QI 1 "nonimmediate_operand" "xm,x"))]
-  "TARGET_SSE2"
+  "TARGET_SSE2
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   if (get_attr_mode (insn) == MODE_V4SF)
     return "movaps\t{%1, %0|%0, %1}";
@@ -18692,8 +18699,8 @@
 	       (const_string "TI")))])
 
 (define_expand "movv2df"
-  [(set (match_operand:V2DF 0 "general_operand" "")
-	(match_operand:V2DF 1 "general_operand" ""))]
+  [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
+	(match_operand:V2DF 1 "nonimmediate_operand" ""))]
   "TARGET_SSE2"
 {
   ix86_expand_vector_move (V2DFmode, operands);
@@ -18701,8 +18708,8 @@
 })
 
 (define_expand "movv8hi"
-  [(set (match_operand:V8HI 0 "general_operand" "")
-	(match_operand:V8HI 1 "general_operand" ""))]
+  [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
+	(match_operand:V8HI 1 "nonimmediate_operand" ""))]
   "TARGET_SSE2"
 {
   ix86_expand_vector_move (V8HImode, operands);
@@ -18710,8 +18717,8 @@
 })
 
 (define_expand "movv16qi"
-  [(set (match_operand:V16QI 0 "general_operand" "")
-	(match_operand:V16QI 1 "general_operand" ""))]
+  [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
+	(match_operand:V16QI 1 "nonimmediate_operand" ""))]
   "TARGET_SSE2"
 {
   ix86_expand_vector_move (V16QImode, operands);
@@ -18719,8 +18726,8 @@
 })
 
 (define_expand "movv4sf"
-  [(set (match_operand:V4SF 0 "general_operand" "")
-	(match_operand:V4SF 1 "general_operand" ""))]
+  [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+	(match_operand:V4SF 1 "nonimmediate_operand" ""))]
   "TARGET_SSE"
 {
   ix86_expand_vector_move (V4SFmode, operands);
@@ -18728,8 +18735,8 @@
 })
 
 (define_expand "movv4si"
-  [(set (match_operand:V4SI 0 "general_operand" "")
-	(match_operand:V4SI 1 "general_operand" ""))]
+  [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
+	(match_operand:V4SI 1 "nonimmediate_operand" ""))]
   "TARGET_SSE"
 {
   ix86_expand_vector_move (V4SImode, operands);
@@ -18737,8 +18744,8 @@
 })
 
 (define_expand "movv2di"
-  [(set (match_operand:V2DI 0 "general_operand" "")
-	(match_operand:V2DI 1 "general_operand" ""))]
+  [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
+	(match_operand:V2DI 1 "nonimmediate_operand" ""))]
   "TARGET_SSE"
 {
   ix86_expand_vector_move (V2DImode, operands);
@@ -18746,8 +18753,8 @@
 })
 
 (define_expand "movv2si"
-  [(set (match_operand:V2SI 0 "general_operand" "")
-	(match_operand:V2SI 1 "general_operand" ""))]
+  [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
+	(match_operand:V2SI 1 "nonimmediate_operand" ""))]
   "TARGET_MMX"
 {
   ix86_expand_vector_move (V2SImode, operands);
@@ -18755,8 +18762,8 @@
 })
 
 (define_expand "movv4hi"
-  [(set (match_operand:V4HI 0 "general_operand" "")
-	(match_operand:V4HI 1 "general_operand" ""))]
+  [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
+	(match_operand:V4HI 1 "nonimmediate_operand" ""))]
   "TARGET_MMX"
 {
   ix86_expand_vector_move (V4HImode, operands);
@@ -18764,8 +18771,8 @@
 })
 
 (define_expand "movv8qi"
-  [(set (match_operand:V8QI 0 "general_operand" "")
-	(match_operand:V8QI 1 "general_operand" ""))]
+  [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
+	(match_operand:V8QI 1 "nonimmediate_operand" ""))]
   "TARGET_MMX"
 {
   ix86_expand_vector_move (V8QImode, operands);
@@ -18773,139 +18780,108 @@
 })
 
 (define_expand "movv2sf"
-  [(set (match_operand:V2SF 0 "general_operand" "")
-	(match_operand:V2SF 1 "general_operand" ""))]
+  [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
+	(match_operand:V2SF 1 "nonimmediate_operand" ""))]
    "TARGET_3DNOW"
 {
   ix86_expand_vector_move (V2SFmode, operands);
   DONE;
 })
 
-(define_insn_and_split "*pushti"
+(define_insn "*pushti"
   [(set (match_operand:TI 0 "push_operand" "=<")
-	(match_operand:TI 1 "nonmemory_operand" "x"))]
+	(match_operand:TI 1 "register_operand" "x"))]
   "TARGET_SSE"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
-   (set (mem:TI (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "multi")])
+  "#")
 
-(define_insn_and_split "*pushv2df"
+(define_insn "*pushv2df"
   [(set (match_operand:V2DF 0 "push_operand" "=<")
-	(match_operand:V2DF 1 "nonmemory_operand" "x"))]
-  "TARGET_SSE2"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
-   (set (mem:V2DF (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "multi")])
+	(match_operand:V2DF 1 "register_operand" "x"))]
+  "TARGET_SSE"
+  "#")
 
-(define_insn_and_split "*pushv2di"
+(define_insn "*pushv2di"
   [(set (match_operand:V2DI 0 "push_operand" "=<")
-	(match_operand:V2DI 1 "nonmemory_operand" "x"))]
+	(match_operand:V2DI 1 "register_operand" "x"))]
   "TARGET_SSE2"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
-   (set (mem:V2DI (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "multi")])
+  "#")
 
-(define_insn_and_split "*pushv8hi"
+(define_insn "*pushv8hi"
   [(set (match_operand:V8HI 0 "push_operand" "=<")
-	(match_operand:V8HI 1 "nonmemory_operand" "x"))]
+	(match_operand:V8HI 1 "register_operand" "x"))]
   "TARGET_SSE2"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
-   (set (mem:V8HI (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "multi")])
+  "#")
 
-(define_insn_and_split "*pushv16qi"
+(define_insn "*pushv16qi"
   [(set (match_operand:V16QI 0 "push_operand" "=<")
-	(match_operand:V16QI 1 "nonmemory_operand" "x"))]
+	(match_operand:V16QI 1 "register_operand" "x"))]
   "TARGET_SSE2"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
-   (set (mem:V16QI (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "multi")])
+  "#")
 
-(define_insn_and_split "*pushv4sf"
+(define_insn "*pushv4sf"
   [(set (match_operand:V4SF 0 "push_operand" "=<")
-	(match_operand:V4SF 1 "nonmemory_operand" "x"))]
+	(match_operand:V4SF 1 "register_operand" "x"))]
   "TARGET_SSE"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
-   (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "multi")])
+  "#")
 
-(define_insn_and_split "*pushv4si"
+(define_insn "*pushv4si"
   [(set (match_operand:V4SI 0 "push_operand" "=<")
-	(match_operand:V4SI 1 "nonmemory_operand" "x"))]
-  "TARGET_SSE"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
-   (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "multi")])
+	(match_operand:V4SI 1 "register_operand" "x"))]
+  "TARGET_SSE2"
+  "#")
 
-(define_insn_and_split "*pushv2si"
+(define_insn "*pushv2si"
   [(set (match_operand:V2SI 0 "push_operand" "=<")
-	(match_operand:V2SI 1 "nonmemory_operand" "y"))]
+	(match_operand:V2SI 1 "register_operand" "y"))]
   "TARGET_MMX"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
-   (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "mmx")])
+  "#")
 
-(define_insn_and_split "*pushv4hi"
+(define_insn "*pushv4hi"
   [(set (match_operand:V4HI 0 "push_operand" "=<")
-	(match_operand:V4HI 1 "nonmemory_operand" "y"))]
+	(match_operand:V4HI 1 "register_operand" "y"))]
   "TARGET_MMX"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
-   (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "mmx")])
+  "#")
 
-(define_insn_and_split "*pushv8qi"
+(define_insn "*pushv8qi"
   [(set (match_operand:V8QI 0 "push_operand" "=<")
-	(match_operand:V8QI 1 "nonmemory_operand" "y"))]
+	(match_operand:V8QI 1 "register_operand" "y"))]
   "TARGET_MMX"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
-   (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "mmx")])
+  "#")
 
-(define_insn_and_split "*pushv2sf"
+(define_insn "*pushv2sf"
   [(set (match_operand:V2SF 0 "push_operand" "=<")
-	(match_operand:V2SF 1 "nonmemory_operand" "y"))]
+	(match_operand:V2SF 1 "register_operand" "y"))]
   "TARGET_3DNOW"
-  "#"
-  ""
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
-   (set (mem:V2SF (reg:SI 7)) (match_dup 1))]
-  ""
-  [(set_attr "type" "mmx")])
+  "#")
+
+(define_split
+  [(set (match_operand 0 "push_operand" "")
+	(match_operand 1 "register_operand" ""))]
+  "!TARGET_64BIT && reload_completed
+   && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
+  [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))
+   (set (match_dup 2) (match_dup 1))]
+  "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
+				 stack_pointer_rtx);
+   operands[3] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));")
+
+(define_split
+  [(set (match_operand 0 "push_operand" "")
+	(match_operand 1 "register_operand" ""))]
+  "TARGET_64BIT && reload_completed
+   && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
+  [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
+   (set (match_dup 2) (match_dup 1))]
+  "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
+				 stack_pointer_rtx);
+   operands[3] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));")
+
 
 (define_insn "movti_internal"
   [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
 	(match_operand:TI 1 "general_operand" "C,xm,x"))]
-  "TARGET_SSE && !TARGET_64BIT"
+  "TARGET_SSE && !TARGET_64BIT
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   switch (which_alternative)
     {
@@ -18998,10 +18974,9 @@
   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
 	(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
 		     UNSPEC_MOVA))]
-  "TARGET_SSE"
-  "@
-   movaps\t{%1, %0|%0, %1}
-   movaps\t{%1, %0|%0, %1}"
+  "TARGET_SSE
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+  "movaps\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov,ssemov")
    (set_attr "mode" "V4SF")])
 
@@ -19009,10 +18984,9 @@
   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
 	(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
 		     UNSPEC_MOVU))]
-  "TARGET_SSE"
-  "@
-   movups\t{%1, %0|%0, %1}
-   movups\t{%1, %0|%0, %1}"
+  "TARGET_SSE
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+  "movups\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt,ssecvt")
    (set_attr "mode" "V4SF")])
 
@@ -22451,45 +22425,41 @@
 
 (define_insn "sse2_movapd"
   [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
-	(unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
+	(unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
 		     UNSPEC_MOVA))]
-  "TARGET_SSE2"
-  "@
-   movapd\t{%1, %0|%0, %1}
-   movapd\t{%1, %0|%0, %1}"
+  "TARGET_SSE2
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+  "movapd\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "mode" "V2DF")])
 
 (define_insn "sse2_movupd"
   [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
-	(unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
+	(unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
 		     UNSPEC_MOVU))]
-  "TARGET_SSE2"
-  "@
-   movupd\t{%1, %0|%0, %1}
-   movupd\t{%1, %0|%0, %1}"
+  "TARGET_SSE2
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+  "movupd\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "mode" "V2DF")])
 
 (define_insn "sse2_movdqa"
   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
-	(unspec:V16QI [(match_operand:V16QI 1 "general_operand" "xm,x")]
+	(unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
 		       UNSPEC_MOVA))]
-  "TARGET_SSE2"
-  "@
-   movdqa\t{%1, %0|%0, %1}
-   movdqa\t{%1, %0|%0, %1}"
+  "TARGET_SSE2
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+  "movdqa\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "mode" "TI")])
 
 (define_insn "sse2_movdqu"
   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
-	(unspec:V16QI [(match_operand:V16QI 1 "general_operand" "xm,x")]
+	(unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
 		       UNSPEC_MOVU))]
-  "TARGET_SSE2"
-  "@
-   movdqu\t{%1, %0|%0, %1}
-   movdqu\t{%1, %0|%0, %1}"
+  "TARGET_SSE2
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+  "movdqu\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "mode" "TI")])