diff options
author | Doug Gilbert <dgilbert@us.ibm.com> | 2015-04-24 16:50:21 -0500 |
---|---|---|
committer | Patrick Williams <patrick@stwcx.xyz> | 2016-08-15 11:45:09 -0500 |
commit | 9869efd8bf59fa3e95c77640fce5831673ca57af (patch) | |
tree | 055583a0ecb086bea1d32ae4f73d379034f9ad1b | |
parent | fed5881806e6dc3894210a1927a7c88175ae6162 (diff) | |
download | ppe42-gcc-9869efd8bf59fa3e95c77640fce5831673ca57af.tar.gz ppe42-gcc-9869efd8bf59fa3e95c77640fce5831673ca57af.zip |
64 bit load/store
-rw-r--r-- | gcc/config/rs6000/rs6000.c | 26 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.h | 14 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.md | 22 |
3 files changed, 43 insertions, 19 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index e1f66c99ab9..889b9885219 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -20501,6 +20501,30 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* The number of registers that will be moved. */ int nregs; + // if ppe42 then use 64bit load/store + { + rtx reg_op = NULL; + rtx mem_op = NULL; + + if( MEM_P (src) && REG_P (dst) ) + { + mem_op = src; + reg_op = dst; + } + else if( REG_P (src) && MEM_P (dst) ) + { + mem_op = dst; + reg_op = src; + } + if(reg_op && mem_op && + (GET_MODE (dst) == DImode && GET_MODE (src) == DImode)) + { + // TODO check for alignment on memory + emit_insn (gen_rtx_SET (DImode, dst, src)); + return; + } + } + reg = REG_P (dst) ? REGNO (dst) : REGNO (src); mode = GET_MODE (dst); nregs = hard_regno_nregs[reg][mode]; @@ -31622,7 +31646,7 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = struct rs6000_opt_var { const char *name; /* option name */ size_t global_offset; /* offset of the option in global_options. */ - size_t target_offset; /* offset of the option in target optiosn. */ + size_t target_offset; /* offset of the option in target options. */ }; static struct rs6000_opt_var const rs6000_opt_vars[] = diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 203f669376f..8dee7c7b199 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -886,7 +886,7 @@ enum data_align { align_abi, align_opt, align_both }; /* Nonzero if move instructions will actually fail to work when given unaligned data. */ -#define STRICT_ALIGNMENT 0 +#define STRICT_ALIGNMENT 1 /* Define this macro to be the value 1 if unaligned accesses have a cost many times greater than aligned accesses, for example if they are @@ -1029,8 +1029,8 @@ enum data_align { align_abi, align_opt, align_both }; of `CALL_USED_REGISTERS'. */ #define CALL_REALLY_USED_REGISTERS \ - {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 1, 1, \ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \ + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, FIXED_R13, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ @@ -1112,9 +1112,9 @@ enum data_align { align_abi, align_opt, align_both }; 68, \ MAYBE_R2_AVAILABLE \ 9, 10, 8, 7, 6, 5, 4, \ - 3, EARLY_R12 0, \ + 3, 0, \ 31, 30, 29, 28, \ - 13, LATE_R12 \ + 13, \ 66, 65, \ 73, 1, MAYBE_R2_FIXED 67, 76, \ /* AltiVec registers. */ \ @@ -1407,9 +1407,9 @@ enum reg_class /* NO_REGS. */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ /* BASE_REGS. */ \ - { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ + { 0xf00027fe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ /* GENERAL_REGS. */ \ - { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ + { 0xf00027ff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ /* FLOAT_REGS. */ \ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \ /* ALTIVEC_REGS. */ \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4860b1731b2..42f23ff19ce 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -10213,11 +10213,11 @@ "@ stvd%U0%X0 %1, %0 lvd%U1%X1 %0, %1 - # ret to reg not supported + # movedi_internal32 %0, %1 FIXME stfd%U0%X0 %1,%0 lfd%U1%X1 %0,%1 fmr %0,%1 - # What is this? movdi_internal32" + # This message should never be seen" [(set_attr_alternative "type" [(const_string "store") (const_string "load") @@ -10258,15 +10258,15 @@ operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); }") -;; disable DImode load/store splits for PPE - use 64-bit load/store instructions -;;(define_split -;; [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "") -;; (match_operand:DIFD 1 "input_operand" ""))] -;; "reload_completed && !TARGET_POWERPC64 -;; && gpr_or_gpr_p (operands[0], operands[1]) -;; && !direct_move_p (operands[0], operands[1])" -;; [(pc)] -;;{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) +;; DImode load/store splits for PPE reg-to reg +(define_split + [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "") + (match_operand:DIFD 1 "input_operand" ""))] + "reload_completed && !TARGET_POWERPC64 + && gpr_or_gpr_p (operands[0], operands[1]) + && !direct_move_p (operands[0], operands[1])" + [(pc)] +{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi") |