* c-pretty-print.h: Fix comment typos.

	* integrate.c: Likewise.
	* varasm.c: Likewise.
	* config/c4x/c4x.h: Likewise.
	* config/c4x/c4x.md: Likewise.
	* config/fr30/fr30.md: Likewise.
	* config/frv/frv.c: Likewise.
	* config/h8300/h8300.c: Likewise.
	* config/i386/i386.c: Likewise.
	* config/i386/i386.h: Likewise.
	* config/ia64/ia64.c: Likewise.
	* config/ia64/ia64.h: Likewise.
	* config/ip2k/ip2k.md: Likewise.
	* config/m68hc11/m68hc11-crt0.S: Likewise.
	* config/m68hc11/m68hc11.h: Likewise.
	* config/m68hc11/m68hc11.md: Likewise.
	* config/m68hc11/m68hc12.h: Likewise.
	* config/mcore/mcore.md: Likewise.
	* config/mips/mips.c: Likewise.
	* config/mips/mips.md: Likewise.
	* config/mmix/mmix-modes.def: Likewise.
	* config/pa/pa.c: Likewise.
	* config/rs6000/rs6000.c: Likewise.
	* config/rs6000/rs6000.h: Likewise.
	* config/rs6000/rs6000.md: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@60354 138bc75d-0d04-0410-961f-82ee72b054a4

27 files changed, 66 insertions, 38 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 209e12fc496..65ba2596a27 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,33 @@
 2002-12-19  Kazu Hirata  <kazu@cs.umass.edu>
 
+	* c-pretty-print.h: Fix comment typos.
+	* integrate.c: Likewise.
+	* varasm.c: Likewise.
+	* config/c4x/c4x.h: Likewise.
+	* config/c4x/c4x.md: Likewise.
+	* config/fr30/fr30.md: Likewise.
+	* config/frv/frv.c: Likewise.
+	* config/h8300/h8300.c: Likewise.
+	* config/i386/i386.c: Likewise.
+	* config/i386/i386.h: Likewise.
+	* config/ia64/ia64.c: Likewise.
+	* config/ia64/ia64.h: Likewise.
+	* config/ip2k/ip2k.md: Likewise.
+	* config/m68hc11/m68hc11-crt0.S: Likewise.
+	* config/m68hc11/m68hc11.h: Likewise.
+	* config/m68hc11/m68hc11.md: Likewise.
+	* config/m68hc11/m68hc12.h: Likewise.
+	* config/mcore/mcore.md: Likewise.
+	* config/mips/mips.c: Likewise.
+	* config/mips/mips.md: Likewise.
+	* config/mmix/mmix-modes.def: Likewise.
+	* config/pa/pa.c: Likewise.
+	* config/rs6000/rs6000.c: Likewise.
+	* config/rs6000/rs6000.h: Likewise.
+	* config/rs6000/rs6000.md: Likewise.
+
+2002-12-19  Kazu Hirata  <kazu@cs.umass.edu>
+
 	* config/h8300/h8300.md (output_a_shift): Clean up the code to
 	output shifts using rotation.
 
diff --git a/gcc/c-pretty-print.h b/gcc/c-pretty-print.h
index 0ab702e0a51..013ab6fa4a6 100644
--- a/gcc/c-pretty-print.h
+++ b/gcc/c-pretty-print.h
@@ -41,7 +41,7 @@ struct c_pretty_print_info
      Not used yet.  */
   int *offset_list;
 
-  /* These must be overriden by each of the C and C++ front-end to
+  /* These must be overridden by each of the C and C++ front-end to
      reflect their understanding of syntatic productions when they differ.  */
   c_pretty_print_fn declaration;
   c_pretty_print_fn declaration_specifiers;
@@ -141,7 +141,7 @@ struct c_pretty_print_info
 
 
 /* Returns the c_pretty_printer base object of PRETTY-PRINTER.  This
-   macro must be overriden by any subclass of c_pretty_print_info.  */
+   macro must be overridden by any subclass of c_pretty_print_info.  */
 #define pp_c_base(PP)  (PP)
 
 extern void pp_c_pretty_printer_init   PARAMS ((c_pretty_printer));
diff --git a/gcc/config/c4x/c4x.h b/gcc/config/c4x/c4x.h
index 576aaff3826..e75769b9407 100644
--- a/gcc/config/c4x/c4x.h
+++ b/gcc/config/c4x/c4x.h
@@ -1334,7 +1334,7 @@ CUMULATIVE_ARGS;
 
 #ifndef REG_OK_STRICT
 
-/* Nonzero if X is a hard or pseudo reg that can be used as an base.  */
+/* Nonzero if X is a hard or pseudo reg that can be used as a base.  */
 
 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
 
diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md
index 2d52082da35..68d933ba594 100644
--- a/gcc/config/c4x/c4x.md
+++ b/gcc/config/c4x/c4x.md
@@ -231,7 +231,7 @@
 ;  a new spill register.
 
 ;  Note that the floating point representation of 0.0 on the C4x
-;  is 0x80000000 (-2147483648).  This value produces an warning
+;  is 0x80000000 (-2147483648).  This value produces a warning
 ;  message on 32-bit machines about the decimal constant being so large
 ;  that it is unsigned.
 
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index 8ba00cce8e9..6d2a291f469 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -36,7 +36,7 @@
 ;; Define an attribute to be used by the delay slot code.
 ;; An instruction by default is considered to be 'delyabable'
 ;; that is, it can be placed into a delay slot, but it is not
-;; itself an delyaed branch type instruction.  An instruction
+;; itself a delyaed branch type instruction.  An instruction
 ;; whoes type is 'delayed' is one which has a delay slot, and
 ;; an instruction whoes delay_type is 'other' is one which does
 ;; not have a delay slot, nor can it be placed into a delay slot.
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index aa29d248c47..f1ad90b46ee 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -1061,7 +1061,7 @@ frv_stack_info ()
 	case STACK_REGS_STDARG:
 	  if (varargs_p)
 	    {
-	      /* If this is a stdarg function with an non varardic argument split
+	      /* If this is a stdarg function with a non varardic argument split
 		 between registers and the stack, adjust the saved registers
 		 downward */
 	      last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
@@ -4791,7 +4791,7 @@ call_operand (op, mode)
   return gpr_or_int12_operand (op, mode);
 }
 
-/* Return true if operator is an kind of relational operator */
+/* Return true if operator is a kind of relational operator.  */
 
 int
 relational_operator (op, mode)
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index ab2cc1544ed..a01db55a4c9 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -667,7 +667,7 @@ h8300_output_function_epilogue (file, size)
     }
 
   /* Monitor epilogues are the same as interrupt function epilogues.
-     Just make a note that we're in an monitor epilogue.  */
+     Just make a note that we're in a monitor epilogue.  */
   if (monitor)
     fprintf (file, ";monitor epilogue\n");
 
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 4ebf16b0875..78233283d93 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2414,7 +2414,7 @@ function_arg (cum, mode, type, named)
     (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
   int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
 
-  /* Handle an hidden AL argument containing number of registers for varargs
+  /* Handle a hidden AL argument containing number of registers for varargs
      x86-64 functions.  For i386 ABI just return constm1_rtx to avoid
      any AL settings.  */
   if (mode == VOIDmode)
@@ -8619,7 +8619,7 @@ ix86_fp_comparison_codes (code, bypass_code, first_code, second_code)
 }
 
 /* Return cost of comparison done fcom + arithmetics operations on AX.
-   All following functions do use number of instructions as an cost metrics.
+   All following functions do use number of instructions as a cost metrics.
    In future this should be tweaked to compute bytes for optimize_size and
    take into account performance of various instructions on various CPUs.  */
 static int
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 964237d10bb..b05e7edcc02 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -891,7 +891,7 @@ extern int x86_prefetch_sse;
    and are not available for the register allocator.
    On the 80386, the stack pointer is such, as is the arg pointer.
 
-   The value is an mask - bit 1 is set for fixed registers
+   The value is a mask - bit 1 is set for fixed registers
    for 32bit target, while 2 is set for fixed registers for 64bit.
    Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
  */
@@ -917,7 +917,7 @@ extern int x86_prefetch_sse;
    and the register where structure-value addresses are passed.
    Aside from that, you can include as many other registers as you like.
 
-   The value is an mask - bit 1 is set for call used
+   The value is a mask - bit 1 is set for call used
    for 32bit target, while 2 is set for call used for 64bit.
    Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
 */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index d625f586d46..16a5207666a 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5320,7 +5320,7 @@
       if (! rtx_equal_p (operands[0], operands[1]))
 	abort ();
       /* ???? We ought to handle there the 32bit case too
-	 - do we need new constrant?  */
+	 - do we need new constraint?  */
       /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
 	 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
       if (GET_CODE (operands[2]) == CONST_INT
@@ -5370,7 +5370,7 @@
       if (! rtx_equal_p (operands[0], operands[1]))
 	abort ();
       /* ???? We ought to handle there the 32bit case too
-	 - do we need new constrant?  */
+	 - do we need new constraint?  */
       /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
 	 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
       if (GET_CODE (operands[2]) == CONST_INT
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 96e12b402fd..3009d1c1200 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -795,7 +795,7 @@ not_postinc_memory_operand (op, mode)
 	  && GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != 'a');
 }
 
-/* Return 1 if this is a comparison operator, which accepts an normal 8-bit
+/* Return 1 if this is a comparison operator, which accepts a normal 8-bit
    signed immediate operand.  */
 
 int
@@ -5126,7 +5126,7 @@ safe_group_barrier_needed_p (insn)
   return t;
 }
 
-/* INSNS is an chain of instructions.  Scan the chain, and insert stop bits
+/* INSNS is a chain of instructions.  Scan the chain, and insert stop bits
    as necessary to eliminate dependendencies.  This function assumes that
    a final instruction scheduling pass has been run which has already
    inserted most of the necessary stop bits.  This function only inserts
diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h
index 3cfc061920f..091510c387c 100644
--- a/gcc/config/ia64/ia64.h
+++ b/gcc/config/ia64/ia64.h
@@ -277,7 +277,7 @@ extern const char *ia64_tls_size_string;
 
 /* A C expression whose value is zero if pointers that need to be extended
    from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
-   they are zero-extended and negative one if there is an ptr_extend operation.
+   they are zero-extended and negative one if there is a ptr_extend operation.
 
    You need not define this macro if the `POINTER_SIZE' is equal to the width
    of `Pmode'.  */
diff --git a/gcc/config/ip2k/ip2k.md b/gcc/config/ip2k/ip2k.md
index 3fa272e328f..f29d05acb30 100644
--- a/gcc/config/ip2k/ip2k.md
+++ b/gcc/config/ip2k/ip2k.md
@@ -5089,7 +5089,7 @@
 
 ;; Nop instruction.
 ;;
-;; We don't really want nops to appear in our code so just insert an comment.
+;; We don't really want nops to appear in our code so just insert a comment.
 ;;
 (define_insn "nop"
   [(const_int 0)]
diff --git a/gcc/config/m68hc11/m68hc11-crt0.S b/gcc/config/m68hc11/m68hc11-crt0.S
index 9351ee69c49..5cd7384119f 100644
--- a/gcc/config/m68hc11/m68hc11-crt0.S
+++ b/gcc/config/m68hc11/m68hc11-crt0.S
@@ -74,7 +74,7 @@ _start:
 	.sect	.install2,"ax",@progbits
 ;;
 ;; Call a specific initialization operation.  The default is empty.
-;; It can be overriden by applications.  It is intended to initialize
+;; It can be overridden by applications.  It is intended to initialize
 ;; the 68hc11 registers.  Function prototype is:
 ;; 
 ;;	int __premain(void);
diff --git a/gcc/config/m68hc11/m68hc11.h b/gcc/config/m68hc11/m68hc11.h
index 393ab7bbf42..6911b41d150 100644
--- a/gcc/config/m68hc11/m68hc11.h
+++ b/gcc/config/m68hc11/m68hc11.h
@@ -47,7 +47,7 @@ Note:
 #endif
 
 /* We need to tell the linker the target elf format.  Just pass an
-   emulation option.  This can be overriden by -Wl option of gcc.  */
+   emulation option.  This can be overridden by -Wl option of gcc.  */
 #ifndef LINK_SPEC
 #define LINK_SPEC      "%{m68hc12:-m m68hc12elf}%{!m68hc12:-m m68hc11elf} %{mrelax:-relax}"
 #endif
diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md
index beeded3d6ad..db1a8922dfe 100644
--- a/gcc/config/m68hc11/m68hc11.md
+++ b/gcc/config/m68hc11/m68hc11.md
@@ -6820,7 +6820,7 @@
 
 ;;;
 ;;; Catch an xgdx/xgdy followed by a (set D X/Y). If X/Y is dead, we don't
-;;; need to emit anything. Otherwise, we just need an copy of D to X/Y.
+;;; need to emit anything. Otherwise, we just need a copy of D to X/Y.
 ;;;
 (define_peephole
   [(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A"))
@@ -6836,7 +6836,7 @@
 
 ;;;
 ;;; Catch an xgdx/xgdy followed by a (set D X/Y). If X/Y is dead, we don't
-;;; need to emit anything. Otherwise, we just need an copy of D to X/Y.
+;;; need to emit anything. Otherwise, we just need a copy of D to X/Y.
 ;;;
 (define_peephole
   [(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A"))
diff --git a/gcc/config/m68hc11/m68hc12.h b/gcc/config/m68hc11/m68hc12.h
index ba56c172993..a9f09dd42bb 100644
--- a/gcc/config/m68hc11/m68hc12.h
+++ b/gcc/config/m68hc11/m68hc12.h
@@ -25,7 +25,7 @@ Boston, MA 02111-1307, USA.  */
 #define CC1_SPEC       ""
 
 /* We need to tell the linker the target elf format.  Just pass an
-   emulation option.  This can be overriden by -Wl option of gcc.  */
+   emulation option.  This can be overridden by -Wl option of gcc.  */
 #define LINK_SPEC      "%{m68hc11:-m m68hc11elf}%{!m68hc11:-m m68hc12elf}"
 
 #define CPP_SPEC  \
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index fe71e377290..dd1c614dbf1 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -150,7 +150,7 @@
 ;; ;    This is done to allow bit field masks to fold together in combine.
 ;; ;    The reload phase will force the immediate into a register at the
 ;; ;    very end.  This helps in some cases, but hurts in others: we'd
-;; ;    really like to cse these immediates.  However, there is an phase
+;; ;    really like to cse these immediates.  However, there is a phase
 ;; ;    ordering problem here.  cse picks up individual masks and cse's
 ;; ;    those, but not folded masks (cse happens before combine).  It's
 ;; ;    not clear what the best solution is because we really want cse
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index f8f3cb6eb7c..6fb7eb4057c 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -5688,7 +5688,7 @@ mips_debugger_offset (addr, offset)
    '^'	Print the name of the pic call-through register (t9 or $25).
    '$'	Print the name of the stack pointer register (sp or $29).
    '+'	Print the name of the gp register (gp or $28).
-   '~'	Output an branch alignment to LABEL_ALIGN(NULL).  */
+   '~'	Output a branch alignment to LABEL_ALIGN(NULL).  */
 
 void
 print_operand (file, op, letter)
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 0edd32e4239..3d2d617f69d 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1282,7 +1282,7 @@
 			       (const_int 8))
 		 (const_int 4)])])
 
-;; On the mips16, we can sometimes split an subtract of a constant
+;; On the mips16, we can sometimes split a subtract of a constant
 ;; which is a 4 byte instruction into two adds which are both 2 byte
 ;; instructions.  There are two cases: one where we are setting a
 ;; register to a register minus a constant, and one where we are
diff --git a/gcc/config/mmix/mmix-modes.def b/gcc/config/mmix/mmix-modes.def
index 27cf3f8c3aa..001a04dce77 100644
--- a/gcc/config/mmix/mmix-modes.def
+++ b/gcc/config/mmix/mmix-modes.def
@@ -34,7 +34,7 @@ Boston, MA 02111-1307, USA.  */
    the CMPU insn.  Result values correspond to those in CCmode.  */
 CC (CC_UNS)
 
-/* The CC_FP mode is for an non-equality floating-point comparison, using
+/* The CC_FP mode is for a non-equality floating-point comparison, using
    the FCMP or FCMPE insn.  The result is (integer) -1 or 1 for
    espectively a < b and a > b, otherwise 0.  */
 CC (CC_FP)
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 7ba4f7bbcfa..cd52977abb6 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1458,7 +1458,7 @@ emit_move_sequence (operands, mode, scratch_reg)
      use scratch_reg to hold the address of the memory location.
 
      The proper fix is to change PREFERRED_RELOAD_CLASS to return
-     NO_REGS when presented with a const_int and an register class
+     NO_REGS when presented with a const_int and a register class
      containing only FP registers.  Doing so unfortunately creates
      more problems than it solves.   Fix this for 2.5.  */
   else if (fp_reg_operand (operand0, mode)
@@ -4300,7 +4300,7 @@ print_operand (file, x, code)
 	fputs ("\n\tnop", file);
       return;
     case '*':
-      /* Output an nullification completer if there's nothing for the */
+      /* Output a nullification completer if there's nothing for the */
       /* delay slot or nullification is requested.  */
       if (dbr_sequence_length () == 0 ||
 	  (final_sequence &&
@@ -5428,7 +5428,7 @@ output_cbranch (operands, nullify, length, negated, insn)
 	  strcat (buf, " %2,%r1,%0");
 	break;
 
-     /* All long conditionals.  Note an short backward branch with an
+     /* All long conditionals.  Note a short backward branch with an
 	unfilled delay slot is treated just like a long backward branch
 	with an unfilled delay slot.  */
       case 8:
@@ -5650,7 +5650,7 @@ output_bb (operands, nullify, length, negated, insn, which)
 	  strcat (buf, " %0,%1,%2");
 	break;
 
-     /* All long conditionals.  Note an short backward branch with an
+     /* All long conditionals.  Note a short backward branch with an
 	unfilled delay slot is treated just like a long backward branch
 	with an unfilled delay slot.  */
       case 8:
@@ -5798,7 +5798,7 @@ output_bvb (operands, nullify, length, negated, insn, which)
 	  strcat (buf, "{ %0,%2| %0,%%sar,%2}");
 	break;
 
-     /* All long conditionals.  Note an short backward branch with an
+     /* All long conditionals.  Note a short backward branch with an
 	unfilled delay slot is treated just like a long backward branch
 	with an unfilled delay slot.  */
       case 8:
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 27069b6f1d9..6ca020966a1 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2349,7 +2349,7 @@ rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win)
    refers to a constant pool entry of an address (or the sum of it
    plus a constant), a short (16-bit signed) constant plus a register,
    the sum of two registers, or a register indirect, possibly with an
-   auto-increment.  For DFmode and DImode with an constant plus register,
+   auto-increment.  For DFmode and DImode with a constant plus register,
    we must ensure that both words are addressable or PowerPC64 with offset
    word aligned.
 
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 9bb6373682b..27954f2d2f2 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2021,7 +2021,7 @@ typedef struct rs6000_args
    refers to a constant pool entry of an address (or the sum of it
    plus a constant), a short (16-bit signed) constant plus a register,
    the sum of two registers, or a register indirect, possibly with an
-   auto-increment.  For DFmode and DImode with an constant plus register,
+   auto-increment.  For DFmode and DImode with a constant plus register,
    we must ensure that both words are addressable or PowerPC64 with offset
    word aligned.
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index acd5c4764ee..85d918235e8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3306,7 +3306,7 @@
 		    (const_int 0)))]
   "")
 
-;; Split an logical operation that we can't do in one insn into two insns, 
+;; Split a logical operation that we can't do in one insn into two insns, 
 ;; each of which does one 16-bit part.  This is used by combine.
 
 (define_split
@@ -7980,7 +7980,7 @@
 		    (const_int 0)))]
   "")
 
-;; Split an logical operation that we can't do in one insn into two insns, 
+;; Split a logical operation that we can't do in one insn into two insns, 
 ;; each of which does one 16-bit part.  This is used by combine.
 
 (define_split
diff --git a/gcc/integrate.c b/gcc/integrate.c
index 355cac345eb..eace82abe94 100644
--- a/gcc/integrate.c
+++ b/gcc/integrate.c
@@ -264,7 +264,7 @@ function_cannot_inline_p (fndecl)
     }
 
   /* If the function has a target specific attribute attached to it,
-     then we assume that we should not inline it.  This can be overriden
+     then we assume that we should not inline it.  This can be overridden
      by the target if it defines TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P.  */
   if (!function_attribute_inlinable_p (fndecl))
     return N_("function with target specific attribute(s) cannot be inlined");
diff --git a/gcc/varasm.c b/gcc/varasm.c
index b0d5f8372f9..ffa653ba877 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -5418,7 +5418,7 @@ default_binds_local_p_1 (exp, shlib)
 }
 
 /* Determine whether or not a pointer mode is valid. Assume defaults
-   of ptr_mode or Pmode - can be overriden.  */
+   of ptr_mode or Pmode - can be overridden.  */
 bool
 default_valid_pointer_mode (mode)
      enum machine_mode mode;