* config/alpha/alpha.c, config/alpha/alpha.md,

	config/alpha/lib1funcs.asm, config/alpha/vms-crt0-64.c,
	config/alpha/vms-psxcrt0-64.c, config/arc/arc.c,
	config/arc/arc.h, config/arm/arm.c, config/arm/arm.md,
	config/arm/lib1funcs.asm: Follow spelling conventions.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@122150 138bc75d-0d04-0410-961f-82ee72b054a4

11 files changed, 30 insertions, 22 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cc601c8e648..2861d3f7215 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2007-02-20  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/alpha/alpha.c, config/alpha/alpha.md,
+	config/alpha/lib1funcs.asm, config/alpha/vms-crt0-64.c,
+	config/alpha/vms-psxcrt0-64.c, config/arc/arc.c,
+	config/arc/arc.h, config/arm/arm.c, config/arm/arm.md,
+	config/arm/lib1funcs.asm: Follow spelling conventions.
+
 2007-02-20  Alan Modra  <amodra@bigpond.net.au>
 
 	PR target/29943
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index e0ece7561b8..023bbcc92f7 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -3343,7 +3343,7 @@ alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
 
       /* We must use tgt here for the target.  Alpha-vms port fails if we use
 	 addr for the target, because addr is marked as a pointer and combine
-	 knows that pointers are always sign-extended 32 bit values.  */
+	 knows that pointers are always sign-extended 32-bit values.  */
       addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
       addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
 			   addr, 1, OPTAB_WIDEN);
@@ -6580,7 +6580,7 @@ alpha_expand_builtin (tree exp, rtx target,
 #endif
 
 /* Fold the builtin for the CMPBGE instruction.  This is a vector comparison
-   with an 8 bit output vector.  OPINT contains the integer operands; bit N
+   with an 8-bit output vector.  OPINT contains the integer operands; bit N
    of OP_CONST is set if OPINT[N] is valid.  */
 
 static tree
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 3edd04c8f03..2e9e1311405 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -6568,7 +6568,7 @@
     {
       int ofs;
 
-      /* Fail 8 bit fields, falling back on a simple byte load.  */
+      /* Fail 8-bit fields, falling back on a simple byte load.  */
       if (INTVAL (operands[2]) == 8)
 	FAIL;
 
diff --git a/gcc/config/alpha/lib1funcs.asm b/gcc/config/alpha/lib1funcs.asm
index 41a551057d4..4c29309583c 100644
--- a/gcc/config/alpha/lib1funcs.asm
+++ b/gcc/config/alpha/lib1funcs.asm
@@ -200,7 +200,7 @@ FUNCTION_NAME:
 #define N RETREG
 #endif
 
-/* Perform conversion from 32 bit types to 64 bit types.  */
+/* Perform conversion from 32-bit types to 64-bit types.  */
 #if SIZE == 32
 #if TYPE == SIGNED
 	/* If there are problems with the signed case, add these instructions.
@@ -303,7 +303,7 @@ $46:
 #endif
 
 
-/* Sign extend an *unsigned* 32 bit result, as required by the Alpha
+/* Sign extend an *unsigned* 32-bit result, as required by the Alpha
    conventions.  */
 #if TYPE == UNSIGNED && SIZE == 32
 	/* This could be avoided by adding some CPP hair to the divide loop.
diff --git a/gcc/config/alpha/vms-crt0-64.c b/gcc/config/alpha/vms-crt0-64.c
index 2e87965e6cc..d7c8ca4d972 100644
--- a/gcc/config/alpha/vms-crt0-64.c
+++ b/gcc/config/alpha/vms-crt0-64.c
@@ -77,7 +77,7 @@ __main (arg1, arg2, arg3, image_file_desc, arg5, arg6)
 
 #pragma __pointer_size long
 
-  /* Reallocate argv with 64 bit pointers.  */
+  /* Reallocate argv with 64-bit pointers.  */
   long_argv = (char **) malloc (sizeof (char *) * (argc + 1));
 
   for (i = 0; i < argc; i++)
diff --git a/gcc/config/alpha/vms-psxcrt0-64.c b/gcc/config/alpha/vms-psxcrt0-64.c
index 02c77019abe..cf4e8679e11 100644
--- a/gcc/config/alpha/vms-psxcrt0-64.c
+++ b/gcc/config/alpha/vms-psxcrt0-64.c
@@ -79,7 +79,7 @@ __main (arg1, arg2, arg3, image_file_desc, arg5, arg6)
 
 #pragma __pointer_size long
 
-  /* Reallocate argv with 64 bit pointers.  */
+  /* Reallocate argv with 64-bit pointers.  */
   long_argv = (char **) malloc (sizeof (char *) * (argc + 1));
 
   for (i = 0; i < argc; i++)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 78a95f40ce9..919f03b39a3 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -262,7 +262,7 @@ arc_select_cc_mode (enum rtx_code op,
    indexed by hard register number, and one indexed by mode.  */
 
 /* The purpose of arc_mode_class is to shrink the range of modes so that
-   they all fit (as bit numbers) in a 32 bit word (again).  Each real mode is
+   they all fit (as bit numbers) in a 32-bit word (again).  Each real mode is
    mapped into one arc_mode_class mode.  */
 
 enum arc_mode_class {
@@ -479,7 +479,7 @@ long_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
     case CONST_INT :
       return !SMALL_INT (INTVAL (op));
     case CONST_DOUBLE :
-      /* These can happen because large unsigned 32 bit constants are
+      /* These can happen because large unsigned 32-bit constants are
 	 represented this way (the multiplication patterns can cause these
 	 to be generated).  They also occur for SFmode values.  */
       return 1;
@@ -516,7 +516,7 @@ long_immediate_loadstore_operand (rtx op,
 	 assume that it does.  */
       return 1;
     case CONST_DOUBLE :
-      /* These can happen because large unsigned 32 bit constants are
+      /* These can happen because large unsigned 32-bit constants are
 	 represented this way (the multiplication patterns can cause these
 	 to be generated).  They also occur for SFmode values.  */
       return 1;
@@ -550,10 +550,10 @@ move_src_operand (rtx op, enum machine_mode mode)
     case CONST_DOUBLE :
       /* We can handle DImode integer constants in SImode if the value
 	 (signed or unsigned) will fit in 32 bits.  This is needed because
-	 large unsigned 32 bit constants are represented as CONST_DOUBLEs.  */
+	 large unsigned 32-bit constants are represented as CONST_DOUBLEs.  */
       if (mode == SImode)
 	return arc_double_limm_p (op);
-      /* We can handle 32 bit floating point constants.  */
+      /* We can handle 32-bit floating point constants.  */
       if (mode == SFmode)
 	return GET_MODE (op) == SFmode;
       return 0;
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 9b9f2d6eec6..69ec6376764 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -430,7 +430,7 @@ extern enum reg_class arc_regno_reg_class[FIRST_PSEUDO_REGISTER];
    Here VALUE is the CONST_DOUBLE rtx itself.  */
 /* 'G' is used for integer values for the multiplication insns where the
    operands are extended from 4 bytes to 8 bytes.
-   'H' is used when any 64 bit constant is allowed.  */
+   'H' is used when any 64-bit constant is allowed.  */
 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
 ((C) == 'G' ? arc_double_limm_p (VALUE) \
  : (C) == 'H' ? 1 \
@@ -671,7 +671,7 @@ arc_eligible_for_epilogue_delay (TRIAL, SLOTS_FILLED)
 
 /* Output assembler code for a block containing the constant parts
    of a trampoline, leaving space for the variable parts.  */
-/* On the ARC, the trampoline is quite simple as we have 32 bit immediate
+/* On the ARC, the trampoline is quite simple as we have 32-bit immediate
    constants.
 
 	mov r24,STATIC
@@ -714,7 +714,7 @@ do { \
  || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
 
 /* Nonzero if the constant value X is a legitimate general operand.
-   We can handle any 32 or 64 bit constant.  */
+   We can handle any 32- or 64-bit constant.  */
 /* "1" should work since the largest constant should be a 64 bit critter.  */
 /* ??? Not sure what to do for 64x32 compiler.  */
 #define LEGITIMATE_CONSTANT_P(X) 1
@@ -1060,7 +1060,7 @@ do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); } while (0)
 /* Specify the machine mode that pointers have.
    After generation of rtl, the compiler makes no further distinction
    between pointers and any other objects of this machine mode.  */
-/* ??? The arc doesn't have full 32 bit pointers, but making this PSImode has
+/* ??? The arc doesn't have full 32-bit pointers, but making this PSImode has
    its own problems (you have to add extendpsisi2 and trucnsipsi2 but how does
    one do it without getting excess code?).  Try to avoid it.  */
 #define Pmode SImode
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 5c47533e6aa..b4c1289075a 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3190,7 +3190,7 @@ current_file_function_operand (rtx sym_ref)
   return 0;
 }
 
-/* Return nonzero if a 32 bit "long_call" should be generated for
+/* Return nonzero if a 32-bit "long_call" should be generated for
    this call.  We generate a long_call if the function:
 
         a.  has an __attribute__((long call))
@@ -4076,7 +4076,7 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
 	       && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
 	return 1;
 
-      /* REG+const has 10 bit offset for SP, but only SImode and
+      /* REG+const has 10-bit offset for SP, but only SImode and
 	 larger is supported.  */
       /* ??? Should probably check for DI/DFmode overflow here
 	 just like GO_IF_LEGITIMATE_OFFSET does.  */
@@ -4385,8 +4385,8 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
       HOST_WIDE_INT mask, base, index;
       rtx base_reg;
 
-      /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
-         use a 8 bit index. So let's use a 12 bit index for SImode only and
+      /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
+         use a 8-bit index. So let's use a 12-bit index for SImode only and
          hope that arm_gen_constant will enable ldrb to use more bits. */
       bits = (mode == SImode) ? 12 : 8;
       mask = (1 << bits) - 1;
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 6d8f914c4cb..37bfe886f3b 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8152,7 +8152,7 @@
       operands[2] = const0_rtx;
       
     /* This is to decide if we should generate indirect calls by loading the
-       32 bit address of the callee into a register before performing the
+       32-bit address of the callee into a register before performing the
        branch and link.  operand[2] encodes the long_call/short_call
        attribute of the function being called.  This attribute is set whenever
        __attribute__((long_call/short_call)) or #pragma long_call/no_long_call
diff --git a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm
index d69d1f187d7..4d455aa1917 100644
--- a/gcc/config/arm/lib1funcs.asm
+++ b/gcc/config/arm/lib1funcs.asm
@@ -444,7 +444,7 @@ pc		.req	r15
 
 	@ Initially shift the divisor left 3 bits if possible,
 	@ set curbit accordingly.  This allows for curbit to be located
-	@ at the left end of each 4 bit nibbles in the division loop
+	@ at the left end of each 4-bit nibbles in the division loop
 	@ to save one loop in most cases.
 	tst	\divisor, #0xe0000000
 	moveq	\divisor, \divisor, lsl #3