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authorlaw <law@138bc75d-0d04-0410-961f-82ee72b054a4>2014-04-04 13:13:20 +0000
committerlaw <law@138bc75d-0d04-0410-961f-82ee72b054a4>2014-04-04 13:13:20 +0000
commit809003b3fb402a83cc4970b5453350271956f968 (patch)
treef45dceb88e46544cd9cd6663618a9d1d09acba4c
parent98107def4d92f0f02d34c53e5971c5e68176815a (diff)
downloadppe42-gcc-809003b3fb402a83cc4970b5453350271956f968.tar.gz
ppe42-gcc-809003b3fb402a83cc4970b5453350271956f968.zip
PR target/60657
* config/arm/predicates.md (const_int_I_operand): New predicate. (const_int_M_operand): Similarly. * config/arm/arm.md (insv_zero): Use const_int_M_operand instead of const_int_operand. (insv_t2, extv_reg, extzv_t2): Likewise. (load_multiple_with_writeback): Similarly for const_int_I_operand. (pop_multiple_with_writeback_and_return): Likewise. (vfp_pop_multiple_with_writeback): Likewise PR target/60657 * gcc.target/arm/pr60657.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209085 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog12
-rw-r--r--gcc/config/arm/arm.md22
-rw-r--r--gcc/config/arm/predicates.md8
-rw-r--r--gcc/testsuite/ChangeLog5
-rw-r--r--gcc/testsuite/gcc.target/arm/pr60657.c13
5 files changed, 49 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4dc3a9ea7f7..33c1669d09d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2014-04-04 Jeff Law <law@redhat.com>
+
+ PR target/60657
+ * config/arm/predicates.md (const_int_I_operand): New predicate.
+ (const_int_M_operand): Similarly.
+ * config/arm/arm.md (insv_zero): Use const_int_M_operand instead of
+ const_int_operand.
+ (insv_t2, extv_reg, extzv_t2): Likewise.
+ (load_multiple_with_writeback): Similarly for const_int_I_operand.
+ (pop_multiple_with_writeback_and_return): Likewise.
+ (vfp_pop_multiple_with_writeback): Likewise
+
2014-04-04 Richard Biener <rguenther@suse.de>
PR ipa/60746
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 4df24a236a2..4b81ee27211 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -2784,8 +2784,8 @@
(define_insn "insv_zero"
[(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
- (match_operand:SI 1 "const_int_operand" "M")
- (match_operand:SI 2 "const_int_operand" "M"))
+ (match_operand:SI 1 "const_int_M_operand" "M")
+ (match_operand:SI 2 "const_int_M_operand" "M"))
(const_int 0))]
"arm_arch_thumb2"
"bfc%?\t%0, %2, %1"
@@ -2797,8 +2797,8 @@
(define_insn "insv_t2"
[(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
- (match_operand:SI 1 "const_int_operand" "M")
- (match_operand:SI 2 "const_int_operand" "M"))
+ (match_operand:SI 1 "const_int_M_operand" "M")
+ (match_operand:SI 2 "const_int_M_operand" "M"))
(match_operand:SI 3 "s_register_operand" "r"))]
"arm_arch_thumb2"
"bfi%?\t%0, %3, %2, %1"
@@ -4480,8 +4480,8 @@
(define_insn "*extv_reg"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "M")
- (match_operand:SI 3 "const_int_operand" "M")))]
+ (match_operand:SI 2 "const_int_M_operand" "M")
+ (match_operand:SI 3 "const_int_M_operand" "M")))]
"arm_arch_thumb2"
"sbfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
@@ -4493,8 +4493,8 @@
(define_insn "extzv_t2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "M")
- (match_operand:SI 3 "const_int_operand" "M")))]
+ (match_operand:SI 2 "const_int_M_operand" "M")
+ (match_operand:SI 3 "const_int_M_operand" "M")))]
"arm_arch_thumb2"
"ubfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
@@ -12073,7 +12073,7 @@
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "+rk")
(plus:SI (match_dup 1)
- (match_operand:SI 2 "const_int_operand" "I")))
+ (match_operand:SI 2 "const_int_I_operand" "I")))
(set (match_operand:SI 3 "s_register_operand" "=rk")
(mem:SI (match_dup 1)))
])]
@@ -12102,7 +12102,7 @@
[(return)
(set (match_operand:SI 1 "s_register_operand" "+rk")
(plus:SI (match_dup 1)
- (match_operand:SI 2 "const_int_operand" "I")))
+ (match_operand:SI 2 "const_int_I_operand" "I")))
(set (match_operand:SI 3 "s_register_operand" "=rk")
(mem:SI (match_dup 1)))
])]
@@ -12155,7 +12155,7 @@
[(match_parallel 0 "pop_multiple_fp"
[(set (match_operand:SI 1 "s_register_operand" "+rk")
(plus:SI (match_dup 1)
- (match_operand:SI 2 "const_int_operand" "I")))
+ (match_operand:SI 2 "const_int_I_operand" "I")))
(set (match_operand:DF 3 "vfp_hard_register_operand" "")
(mem:DF (match_dup 1)))])]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index ce5c9a830cd..6273e8820c6 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -153,6 +153,14 @@
(ior (match_operand 0 "arm_rhs_operand")
(match_operand 0 "memory_operand")))
+(define_predicate "const_int_I_operand"
+ (and (match_operand 0 "const_int_operand")
+ (match_test "satisfies_constraint_I (op)")))
+
+(define_predicate "const_int_M_operand"
+ (and (match_operand 0 "const_int_operand")
+ (match_test "satisfies_constraint_M (op)")))
+
;; This doesn't have to do much because the constant is already checked
;; in the shift_operator predicate.
(define_predicate "shift_amount_operand"
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3c64a2bf96b..528cf7a4c12 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2014-04-04 Jeff Law <law@redhat.com>
+
+ PR target/60657
+ * gcc.target/arm/pr60657.c: New test.
+
2014-04-04 Richard Biener <rguenther@suse.de>
PR ipa/60746
diff --git a/gcc/testsuite/gcc.target/arm/pr60657.c b/gcc/testsuite/gcc.target/arm/pr60657.c
new file mode 100644
index 00000000000..d70e58c73d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr60657.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv7-a" } */
+
+
+void foo (void);
+
+void
+bar (int x, int y)
+{
+ y = 9999;
+ if (x & (1 << y))
+ foo ();
+
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