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| author | Doug Gilbert <dgilbert@us.ibm.com> | 2016-07-14 12:46:00 -0500 |
|---|---|---|
| committer | Patrick Williams <patrick@stwcx.xyz> | 2016-08-15 11:45:09 -0500 |
| commit | 79924b0de80bf4b5eda8cd130c2930428aff5183 (patch) | |
| tree | e37eda5cb51e3766c3c40abfd10664d20f9f85f3 | |
| parent | 0c6c36e8fef06605a16e6de6f38017167fcc75fc (diff) | |
| download | ppe42-gcc-79924b0de80bf4b5eda8cd130c2930428aff5183.tar.gz ppe42-gcc-79924b0de80bf4b5eda8cd130c2930428aff5183.zip | |
Add RTL to correctly handle unavailable lwzux instruction
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index abaca0c934d..8befce96dec 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8954,11 +8954,24 @@ (match_test "update_address_mem (operands[0], VOIDmode)") (const_string "store_u") (const_string "store")))]) - (set_attr "length" "8")]) + ;; PPE42 lacks lwzux -> lwzx; then add -;; TODO +(define_insn "*movsi_internal3" + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r") + (mem:SI + (pre_modify:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (plus:SI (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand:SI 3 "gpc_reg_operand" "r")))))] + "!TARGET_SINGLE_FPU && (rs6000_cpu == PROCESSOR_PPE42) && + REGNO (operands[1]) == REGNO (operands[2]) && + (gpc_reg_operand (operands[1], SImode) || gpc_reg_operand (operands[0], SImode))" + "lwzx %0,%1,%3\;add %1,%2,%3 #lwzux %0,%1,%3" + [(set_attr_alternative "type" + [(const_string "load_ux")]) + (set_attr "length" "8")]) + (define_insn "*movsi_internal1" [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h") |
