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| author | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2001-08-10 13:01:31 +0000 |
|---|---|---|
| committer | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2001-08-10 13:01:31 +0000 |
| commit | 6e5778afc7192bbc3d8faa36526ac5d89b8280bb (patch) | |
| tree | 11044688c3ea55e5971db054834a5b3804eb0455 | |
| parent | 397496841f3abcbe909e30b1c9f9b4187c7eb1d5 (diff) | |
| download | ppe42-gcc-6e5778afc7192bbc3d8faa36526ac5d89b8280bb.tar.gz ppe42-gcc-6e5778afc7192bbc3d8faa36526ac5d89b8280bb.zip | |
* config/mips/mips.md (reload_outcc): Use HARD_REGNO_NREGS to
access the second half of the TFmode scratch operand.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@44759 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 9 |
2 files changed, 12 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e0f097e99f7..366b53362d8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2001-08-10 Richard Sandiford <rsandifo@redhat.com> + + * config/mips/mips.md (reload_outcc): Use HARD_REGNO_NREGS to + access the second half of the TFmode scratch operand. + 2001-08-10 Anthony Green <green@redhat.com> * java/class.c (emit_register_classes): Conditionalize code on diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 092e396c87c..d0ab2a32059 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -5667,6 +5667,7 @@ move\\t%0,%z4\\n\\ { rtx source; rtx fp1, fp2; + int regno; /* This is called when are copying some value into a condition code register. Operand 0 is the condition code register. Operand 1 @@ -5685,8 +5686,12 @@ move\\t%0,%z4\\n\\ else source = operands[1]; - fp1 = gen_rtx_REG (SFmode, REGNO (operands[2])); - fp2 = gen_rtx_REG (SFmode, REGNO (operands[2]) + 1); + /* FP1 and FP2 are the two halves of the TFmode scratch operand. They + will be single registers in 64-bit mode and register pairs in 32-bit + mode. SOURCE is loaded into FP1 and zero is loaded into FP2. */ + regno = REGNO (operands[2]); + fp1 = gen_rtx_REG (SFmode, regno); + fp2 = gen_rtx_REG (SFmode, regno + HARD_REGNO_NREGS (regno, DFmode)); emit_insn (gen_move_insn (fp1, source)); emit_insn (gen_move_insn (fp2, gen_rtx_REG (SFmode, 0))); |
