Remove more places lbzux was being used

1 files changed, 507 insertions, 466 deletions

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index afc76cb33e4..8379598b90c 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -878,11 +878,10 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
   ""
-  "@
-   lbz%U1%X1 %0,%1
+  "
    rlwinm %0,%1,0,0xff"
   [(set_attr_alternative "type"
       [(if_then_else
@@ -891,8 +890,34 @@
 	 (if_then_else
 	   (match_test "update_address_mem (operands[1], VOIDmode)")
 	   (const_string "load_u")
+	   (const_string "*")))])])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m")))]
+  ""
+  "*
+{
+    /* PPE42 does not support the lbzux instruction */
+    /* Probably a better way to implement this */
+    if(update_indexed_address_mem (operands[1], VOIDmode))
+    {
+        static char buf[16];
+        int r1 = REGNO(XEXP(XEXP(operands[1],0),0));
+        sprintf(buf,\"add %d,%%1 #lbzux\;lbz %%0,0(%d)\",r1,r1);
+        return buf;
+    }
+    else return \"lbz%U1%X1 %0,%1\";
+}"
+  [(set_attr_alternative "type"
+      [(if_then_else
+	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
+	 (const_string "load_ux")
+	 (if_then_else
+	   (match_test "update_address_mem (operands[1], VOIDmode)")
+	   (const_string "load_u")
 	   (const_string "load")))
-       (const_string "*")])])
+       ])])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -1010,7 +1035,7 @@
 	(zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
   ""
   "@
-   lbz%U1%X1 %0,%1
+   lbz%U1%X1 %0,%1 #DEBUGME 2 %1
    rlwinm %0,%1,0,0xff"
   [(set_attr_alternative "type"
       [(if_then_else
@@ -1293,415 +1318,415 @@
 
 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
 
-;;(define_insn "*macchwc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (plus:SI (mult:SI (ashiftrt:SI
-;;                                       (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                                       (const_int 16))
-;;                                      (sign_extend:SI
-;;                                       (match_operand:HI 1 "gpc_reg_operand" "r")))
-;;                             (match_operand:SI 4 "gpc_reg_operand" "0"))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (ashiftrt:SI
-;;                           (match_dup 2)
-;;                           (const_int 16))
-;;                          (sign_extend:SI
-;;                           (match_dup 1)))
-;;                 (match_dup 4)))]
-;;  "TARGET_MULHW"
-;;  "macchw. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*macchw"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (ashiftrt:SI
-;;                           (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                           (const_int 16))
-;;                          (sign_extend:SI
-;;                           (match_operand:HI 1 "gpc_reg_operand" "r")))
-;;                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
-;;  "TARGET_MULHW"
-;;  "macchw %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*macchwuc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (plus:SI (mult:SI (lshiftrt:SI
-;;                                       (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                                       (const_int 16))
-;;                                      (zero_extend:SI
-;;                                       (match_operand:HI 1 "gpc_reg_operand" "r")))
-;;                             (match_operand:SI 4 "gpc_reg_operand" "0"))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (lshiftrt:SI
-;;                           (match_dup 2)
-;;                           (const_int 16))
-;;                          (zero_extend:SI
-;;                           (match_dup 1)))
-;;                 (match_dup 4)))]
-;;  "TARGET_MULHW"
-;;  "macchwu. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*macchwu"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (lshiftrt:SI
-;;                           (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                           (const_int 16))
-;;                          (zero_extend:SI
-;;                           (match_operand:HI 1 "gpc_reg_operand" "r")))
-;;                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
-;;  "TARGET_MULHW"
-;;  "macchwu %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*machhwc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (plus:SI (mult:SI (ashiftrt:SI
-;;                                       (match_operand:SI 1 "gpc_reg_operand" "%r")
-;;                                       (const_int 16))
-;;                                      (ashiftrt:SI
-;;                                       (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                                       (const_int 16)))
-;;                             (match_operand:SI 4 "gpc_reg_operand" "0"))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (ashiftrt:SI
-;;                           (match_dup 1)
-;;                           (const_int 16))
-;;                          (ashiftrt:SI
-;;                           (match_dup 2)
-;;                           (const_int 16)))
-;;                 (match_dup 4)))]
-;;  "TARGET_MULHW"
-;;  "machhw. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*machhw"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (ashiftrt:SI
-;;                           (match_operand:SI 1 "gpc_reg_operand" "%r")
-;;                           (const_int 16))
-;;                          (ashiftrt:SI
-;;                           (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                           (const_int 16)))
-;;                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
-;;  "TARGET_MULHW"
-;;  "machhw %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*machhwuc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (plus:SI (mult:SI (lshiftrt:SI
-;;                                       (match_operand:SI 1 "gpc_reg_operand" "%r")
-;;                                       (const_int 16))
-;;                                      (lshiftrt:SI
-;;                                       (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                                       (const_int 16)))
-;;                             (match_operand:SI 4 "gpc_reg_operand" "0"))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (lshiftrt:SI
-;;                           (match_dup 1)
-;;                           (const_int 16))
-;;                          (lshiftrt:SI
-;;                           (match_dup 2)
-;;                           (const_int 16)))
-;;                 (match_dup 4)))]
-;;  "TARGET_MULHW"
-;;  "machhwu. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*machhwu"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (lshiftrt:SI
-;;                           (match_operand:SI 1 "gpc_reg_operand" "%r")
-;;                           (const_int 16))
-;;                          (lshiftrt:SI
-;;                           (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                           (const_int 16)))
-;;                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
-;;  "TARGET_MULHW"
-;;  "machhwu %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*maclhwc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (plus:SI (mult:SI (sign_extend:SI
-;;                                       (match_operand:HI 1 "gpc_reg_operand" "%r"))
-;;                                      (sign_extend:SI
-;;                                       (match_operand:HI 2 "gpc_reg_operand" "r")))
-;;                             (match_operand:SI 4 "gpc_reg_operand" "0"))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (sign_extend:SI
-;;                           (match_dup 1))
-;;                          (sign_extend:SI
-;;                           (match_dup 2)))
-;;                 (match_dup 4)))]
-;;  "TARGET_MULHW"
-;;  "maclhw. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*maclhw"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (sign_extend:SI
-;;                           (match_operand:HI 1 "gpc_reg_operand" "%r"))
-;;                          (sign_extend:SI
-;;                           (match_operand:HI 2 "gpc_reg_operand" "r")))
-;;                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
-;;  "TARGET_MULHW"
-;;  "maclhw %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-;;
-;;(define_insn "*maclhwuc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (plus:SI (mult:SI (zero_extend:SI
-;;                                       (match_operand:HI 1 "gpc_reg_operand" "%r"))
-;;                                      (zero_extend:SI
-;;                                       (match_operand:HI 2 "gpc_reg_operand" "r")))
-;;                             (match_operand:SI 4 "gpc_reg_operand" "0"))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (zero_extend:SI
-;;                           (match_dup 1))
-;;                          (zero_extend:SI
-;;                           (match_dup 2)))
-;;                 (match_dup 4)))]
-;;  "TARGET_MULHW"
-;;  "maclhwu. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*maclhwu"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (plus:SI (mult:SI (zero_extend:SI
-;;                           (match_operand:HI 1 "gpc_reg_operand" "%r"))
-;;                          (zero_extend:SI
-;;                           (match_operand:HI 2 "gpc_reg_operand" "r")))
-;;                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
-;;  "TARGET_MULHW"
-;;  "maclhwu %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*nmacchwc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
-;;                              (mult:SI (ashiftrt:SI
-;;                                        (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                                        (const_int 16))
-;;                                       (sign_extend:SI
-;;                                        (match_operand:HI 1 "gpc_reg_operand" "r"))))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (minus:SI (match_dup 4)
-;;                  (mult:SI (ashiftrt:SI
-;;                            (match_dup 2)
-;;                            (const_int 16))
-;;                           (sign_extend:SI
-;;                            (match_dup 1)))))]
-;;  "TARGET_MULHW"
-;;  "nmacchw. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*nmacchw"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
-;;                  (mult:SI (ashiftrt:SI
-;;                            (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                            (const_int 16))
-;;                           (sign_extend:SI
-;;                            (match_operand:HI 1 "gpc_reg_operand" "r")))))]
-;;  "TARGET_MULHW"
-;;  "nmacchw %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*nmachhwc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
-;;                              (mult:SI (ashiftrt:SI
-;;                                        (match_operand:SI 1 "gpc_reg_operand" "%r")
-;;                                        (const_int 16))
-;;                                       (ashiftrt:SI
-;;                                        (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                                        (const_int 16))))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (minus:SI (match_dup 4)
-;;                  (mult:SI (ashiftrt:SI
-;;                            (match_dup 1)
-;;                            (const_int 16))
-;;                           (ashiftrt:SI
-;;                            (match_dup 2)
-;;                            (const_int 16)))))]
-;;  "TARGET_MULHW"
-;;  "nmachhw. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*nmachhw"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
-;;                  (mult:SI (ashiftrt:SI
-;;                            (match_operand:SI 1 "gpc_reg_operand" "%r")
-;;                            (const_int 16))
-;;                           (ashiftrt:SI
-;;                            (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                            (const_int 16)))))]
-;;  "TARGET_MULHW"
-;;  "nmachhw %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*nmaclhwc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
-;;                              (mult:SI (sign_extend:SI
-;;                                        (match_operand:HI 1 "gpc_reg_operand" "%r"))
-;;                                       (sign_extend:SI
-;;                                        (match_operand:HI 2 "gpc_reg_operand" "r"))))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (minus:SI (match_dup 4)
-;;                  (mult:SI (sign_extend:SI
-;;                            (match_dup 1))
-;;                           (sign_extend:SI
-;;                            (match_dup 2)))))]
-;;  "TARGET_MULHW"
-;;  "nmaclhw. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*nmaclhw"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
-;;                  (mult:SI (sign_extend:SI
-;;                            (match_operand:HI 1 "gpc_reg_operand" "%r"))
-;;                           (sign_extend:SI
-;;                            (match_operand:HI 2 "gpc_reg_operand" "r")))))]
-;;  "TARGET_MULHW"
-;;  "nmaclhw %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*mulchwc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (mult:SI (ashiftrt:SI
-;;                              (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                              (const_int 16))
-;;                             (sign_extend:SI
-;;                              (match_operand:HI 1 "gpc_reg_operand" "r")))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (mult:SI (ashiftrt:SI
-;;                  (match_dup 2)
-;;                  (const_int 16))
-;;                 (sign_extend:SI
-;;                  (match_dup 1))))]
-;;  "TARGET_MULHW"
-;;  "mulchw. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*mulchw"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (mult:SI (ashiftrt:SI
-;;                  (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                  (const_int 16))
-;;                 (sign_extend:SI
-;;                  (match_operand:HI 1 "gpc_reg_operand" "r"))))]
-;;  "TARGET_MULHW"
-;;  "mulchw %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*mulchwuc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (mult:SI (lshiftrt:SI
-;;                              (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                              (const_int 16))
-;;                             (zero_extend:SI
-;;                              (match_operand:HI 1 "gpc_reg_operand" "r")))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (mult:SI (lshiftrt:SI
-;;                  (match_dup 2)
-;;                  (const_int 16))
-;;                 (zero_extend:SI
-;;                 (match_dup 1))))]
-;;  "TARGET_MULHW"
-;;  "mulchwu. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*mulchwu"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (mult:SI (lshiftrt:SI
-;;                  (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                 (const_int 16))
-;;                (zero_extend:SI
-;;                  (match_operand:HI 1 "gpc_reg_operand" "r"))))]
-;;  "TARGET_MULHW"
-;;  "mulchwu %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*mulhhwc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (mult:SI (ashiftrt:SI
-;;                              (match_operand:SI 1 "gpc_reg_operand" "%r")
-;;                              (const_int 16))
-;;                             (ashiftrt:SI
-;;                              (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                              (const_int 16)))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (mult:SI (ashiftrt:SI
-;;                  (match_dup 1)
-;;                  (const_int 16))
-;;                 (ashiftrt:SI
-;;                  (match_dup 2)
-;;                  (const_int 16))))]
-;;  "TARGET_MULHW"
-;;  "mulhhw. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*mulhhw"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (mult:SI (ashiftrt:SI
-;;                  (match_operand:SI 1 "gpc_reg_operand" "%r")
-;;                  (const_int 16))
-;;                 (ashiftrt:SI
-;;                  (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                  (const_int 16))))]
-;;  "TARGET_MULHW"
-;;  "mulhhw %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*mulhhwuc"
-;;  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-;;        (compare:CC (mult:SI (lshiftrt:SI
-;;                              (match_operand:SI 1 "gpc_reg_operand" "%r")
-;;                              (const_int 16))
-;;                             (lshiftrt:SI
-;;                              (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                              (const_int 16)))
-;;                    (const_int 0)))
-;;   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (mult:SI (lshiftrt:SI
-;;                  (match_dup 1)
-;;                  (const_int 16))
-;;                 (lshiftrt:SI
-;;                  (match_dup 2)
-;;                  (const_int 16))))]
-;;  "TARGET_MULHW"
-;;  "mulhhwu. %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
-
-;;(define_insn "*mulhhwu"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;        (mult:SI (lshiftrt:SI
-;;                  (match_operand:SI 1 "gpc_reg_operand" "%r")
-;;                  (const_int 16))
-;;                 (lshiftrt:SI
-;;                  (match_operand:SI 2 "gpc_reg_operand" "r")
-;;                  (const_int 16))))]
-;;  "TARGET_MULHW"
-;;  "mulhhwu %0,%1,%2"
-;;  [(set_attr "type" "imul3")])
+(define_insn "*macchwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (ashiftrt:SI
+                                       (match_operand:SI 2 "gpc_reg_operand" "r")
+                                       (const_int 16))
+                                      (sign_extend:SI
+                                       (match_operand:HI 1 "gpc_reg_operand" "r")))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (ashiftrt:SI
+                           (match_dup 2)
+                           (const_int 16))
+                          (sign_extend:SI
+                           (match_dup 1)))
+                 (match_dup 4)))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "macchw. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*macchw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (ashiftrt:SI
+                           (match_operand:SI 2 "gpc_reg_operand" "r")
+                           (const_int 16))
+                          (sign_extend:SI
+                           (match_operand:HI 1 "gpc_reg_operand" "r")))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "macchw %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*macchwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (lshiftrt:SI
+                                       (match_operand:SI 2 "gpc_reg_operand" "r")
+                                       (const_int 16))
+                                      (zero_extend:SI
+                                       (match_operand:HI 1 "gpc_reg_operand" "r")))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (lshiftrt:SI
+                           (match_dup 2)
+                           (const_int 16))
+                          (zero_extend:SI
+                           (match_dup 1)))
+                 (match_dup 4)))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "macchwu. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*macchwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (lshiftrt:SI
+                           (match_operand:SI 2 "gpc_reg_operand" "r")
+                           (const_int 16))
+                          (zero_extend:SI
+                           (match_operand:HI 1 "gpc_reg_operand" "r")))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "macchwu %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*machhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (ashiftrt:SI
+                                       (match_operand:SI 1 "gpc_reg_operand" "%r")
+                                       (const_int 16))
+                                      (ashiftrt:SI
+                                       (match_operand:SI 2 "gpc_reg_operand" "r")
+                                       (const_int 16)))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (ashiftrt:SI
+                           (match_dup 1)
+                           (const_int 16))
+                          (ashiftrt:SI
+                           (match_dup 2)
+                           (const_int 16)))
+                 (match_dup 4)))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "machhw. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*machhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (ashiftrt:SI
+                           (match_operand:SI 1 "gpc_reg_operand" "%r")
+                           (const_int 16))
+                          (ashiftrt:SI
+                           (match_operand:SI 2 "gpc_reg_operand" "r")
+                           (const_int 16)))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "machhw %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*machhwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (lshiftrt:SI
+                                       (match_operand:SI 1 "gpc_reg_operand" "%r")
+                                       (const_int 16))
+                                      (lshiftrt:SI
+                                       (match_operand:SI 2 "gpc_reg_operand" "r")
+                                       (const_int 16)))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (lshiftrt:SI
+                           (match_dup 1)
+                           (const_int 16))
+                          (lshiftrt:SI
+                           (match_dup 2)
+                           (const_int 16)))
+                 (match_dup 4)))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "machhwu. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*machhwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (lshiftrt:SI
+                           (match_operand:SI 1 "gpc_reg_operand" "%r")
+                           (const_int 16))
+                          (lshiftrt:SI
+                           (match_operand:SI 2 "gpc_reg_operand" "r")
+                           (const_int 16)))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "machhwu %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*maclhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (sign_extend:SI
+                                       (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                                      (sign_extend:SI
+                                       (match_operand:HI 2 "gpc_reg_operand" "r")))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (sign_extend:SI
+                           (match_dup 1))
+                          (sign_extend:SI
+                           (match_dup 2)))
+                 (match_dup 4)))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "maclhw. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*maclhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (sign_extend:SI
+                           (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                          (sign_extend:SI
+                           (match_operand:HI 2 "gpc_reg_operand" "r")))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "maclhw %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*maclhwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (zero_extend:SI
+                                       (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                                      (zero_extend:SI
+                                       (match_operand:HI 2 "gpc_reg_operand" "r")))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (zero_extend:SI
+                           (match_dup 1))
+                          (zero_extend:SI
+                           (match_dup 2)))
+                 (match_dup 4)))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "maclhwu. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*maclhwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (zero_extend:SI
+                           (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                          (zero_extend:SI
+                           (match_operand:HI 2 "gpc_reg_operand" "r")))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "maclhwu %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmacchwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+                              (mult:SI (ashiftrt:SI
+                                        (match_operand:SI 2 "gpc_reg_operand" "r")
+                                        (const_int 16))
+                                       (sign_extend:SI
+                                        (match_operand:HI 1 "gpc_reg_operand" "r"))))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_dup 4)
+                  (mult:SI (ashiftrt:SI
+                            (match_dup 2)
+                            (const_int 16))
+                           (sign_extend:SI
+                            (match_dup 1)))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "nmacchw. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmacchw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+                  (mult:SI (ashiftrt:SI
+                            (match_operand:SI 2 "gpc_reg_operand" "r")
+                            (const_int 16))
+                           (sign_extend:SI
+                            (match_operand:HI 1 "gpc_reg_operand" "r")))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "nmacchw %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmachhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+                              (mult:SI (ashiftrt:SI
+                                        (match_operand:SI 1 "gpc_reg_operand" "%r")
+                                        (const_int 16))
+                                       (ashiftrt:SI
+                                        (match_operand:SI 2 "gpc_reg_operand" "r")
+                                        (const_int 16))))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_dup 4)
+                  (mult:SI (ashiftrt:SI
+                            (match_dup 1)
+                            (const_int 16))
+                           (ashiftrt:SI
+                            (match_dup 2)
+                            (const_int 16)))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "nmachhw. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmachhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+                  (mult:SI (ashiftrt:SI
+                            (match_operand:SI 1 "gpc_reg_operand" "%r")
+                            (const_int 16))
+                           (ashiftrt:SI
+                            (match_operand:SI 2 "gpc_reg_operand" "r")
+                            (const_int 16)))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "nmachhw %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmaclhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+                              (mult:SI (sign_extend:SI
+                                        (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                                       (sign_extend:SI
+                                        (match_operand:HI 2 "gpc_reg_operand" "r"))))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_dup 4)
+                  (mult:SI (sign_extend:SI
+                            (match_dup 1))
+                           (sign_extend:SI
+                            (match_dup 2)))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "nmaclhw. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmaclhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+                  (mult:SI (sign_extend:SI
+                            (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                           (sign_extend:SI
+                            (match_operand:HI 2 "gpc_reg_operand" "r")))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "nmaclhw %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulchwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (mult:SI (ashiftrt:SI
+                              (match_operand:SI 2 "gpc_reg_operand" "r")
+                              (const_int 16))
+                             (sign_extend:SI
+                              (match_operand:HI 1 "gpc_reg_operand" "r")))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (ashiftrt:SI
+                  (match_dup 2)
+                  (const_int 16))
+                 (sign_extend:SI
+                  (match_dup 1))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "mulchw. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulchw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (ashiftrt:SI
+                  (match_operand:SI 2 "gpc_reg_operand" "r")
+                  (const_int 16))
+                 (sign_extend:SI
+                  (match_operand:HI 1 "gpc_reg_operand" "r"))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "mulchw %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulchwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (mult:SI (lshiftrt:SI
+                              (match_operand:SI 2 "gpc_reg_operand" "r")
+                              (const_int 16))
+                             (zero_extend:SI
+                              (match_operand:HI 1 "gpc_reg_operand" "r")))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (lshiftrt:SI
+                  (match_dup 2)
+                  (const_int 16))
+                 (zero_extend:SI
+                 (match_dup 1))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "mulchwu. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulchwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (lshiftrt:SI
+                  (match_operand:SI 2 "gpc_reg_operand" "r")
+                 (const_int 16))
+                (zero_extend:SI
+                  (match_operand:HI 1 "gpc_reg_operand" "r"))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "mulchwu %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (mult:SI (ashiftrt:SI
+                              (match_operand:SI 1 "gpc_reg_operand" "%r")
+                              (const_int 16))
+                             (ashiftrt:SI
+                              (match_operand:SI 2 "gpc_reg_operand" "r")
+                              (const_int 16)))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (ashiftrt:SI
+                  (match_dup 1)
+                  (const_int 16))
+                 (ashiftrt:SI
+                  (match_dup 2)
+                  (const_int 16))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "mulhhw. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (ashiftrt:SI
+                  (match_operand:SI 1 "gpc_reg_operand" "%r")
+                  (const_int 16))
+                 (ashiftrt:SI
+                  (match_operand:SI 2 "gpc_reg_operand" "r")
+                  (const_int 16))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "mulhhw %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (mult:SI (lshiftrt:SI
+                              (match_operand:SI 1 "gpc_reg_operand" "%r")
+                              (const_int 16))
+                             (lshiftrt:SI
+                              (match_operand:SI 2 "gpc_reg_operand" "r")
+                              (const_int 16)))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (lshiftrt:SI
+                  (match_dup 1)
+                  (const_int 16))
+                 (lshiftrt:SI
+                  (match_dup 2)
+                  (const_int 16))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "mulhhwu. %0,%1,%2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (lshiftrt:SI
+                  (match_operand:SI 1 "gpc_reg_operand" "%r")
+                  (const_int 16))
+                 (lshiftrt:SI
+                  (match_operand:SI 2 "gpc_reg_operand" "r")
+                  (const_int 16))))]
+  "TARGET_MULHW && (rs6000_cpu != PROCESSOR_PPE42)"
+  "mulhhwu %0,%1,%2"
+  [(set_attr "type" "imul3")])
 
 (define_insn "*mullhwc"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -2720,14 +2745,30 @@
   emit_insn (gen_bswapsi2 (dest2, src1));
 }")
 
+(define_insn "mulsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+		 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
+  "rs6000_cpu != PROCESSOR_PPE42 && rs6000_cpu != PROCESSOR_PPE405"
+  "@
+   mullhw %0,%1,%2
+   mulli %0,%1,%2"
+   [(set (attr "type")
+      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
+		(const_string "imul3")
+             (match_operand:SI 2 "short_cint_operand" "")
+		(const_string "imul2")]
+	(const_string "imul")))])
+
+;; Try this:
 ;;(define_insn "mulsi3"
 ;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 ;;	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-;;		 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
+;;		 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
 ;;  ""
 ;;  "@
 ;;   mullhw %0,%1,%2
-;;   mulli %0,%1,%2"
+;;   # mulli %0,%1,%2"
 ;;   [(set (attr "type")
 ;;      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
 ;;		(const_string "imul3")
@@ -6673,18 +6714,18 @@
   [(set_attr "type" "two")
    (set_attr "length" "8")])
 
-;;(define_insn "mulsidi3"
-;;  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
-;;	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-;;		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
-;;  "! TARGET_POWERPC64"
-;;{
-;;  return (WORDS_BIG_ENDIAN)
-;;    ? \"mulhw %0,%1,%2\;mullhw %L0,%1,%2\"
-;;    : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
-;;}
-;;  [(set_attr "type" "imul")
-;;   (set_attr "length" "8")])
+(define_insn "mulsidi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+  "(!TARGET_POWERPC64) && (rs6000_cpu != PROCESSOR_PPE42)"
+{
+  return (WORDS_BIG_ENDIAN)
+    ? \"mulhw %0,%1,%2\;mullhw %L0,%1,%2\"
+    : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
+}
+  [(set_attr "type" "imul")
+   (set_attr "length" "8")])
 
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -6706,19 +6747,19 @@
   operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
 }")
 
-;;(define_insn "umulsidi3"
-;;  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
-;;	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-;;		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
-;;  "! TARGET_POWERPC64"
-;;  "*
-;;{
-;;  return (WORDS_BIG_ENDIAN)
-;;    ? \"mulhwu %0,%1,%2\;mullhw %L0,%1,%2\"
-;;    : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
-;;}"
-;;  [(set_attr "type" "imul")
-;;   (set_attr "length" "8")])
+(define_insn "umulsidi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+  "(!TARGET_POWERPC64) && (rs6000_cpu != PROCESSOR_PPE42)"
+  "*
+{
+  return (WORDS_BIG_ENDIAN)
+    ? \"mulhwu %0,%1,%2\;mullhw %L0,%1,%2\"
+    : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
+}"
+  [(set_attr "type" "imul")
+   (set_attr "length" "8")])
 
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -6740,29 +6781,29 @@
   operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
 }")
 
-;;(define_insn "smulsi3_highpart"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;	(truncate:SI
-;;	 (lshiftrt:DI (mult:DI (sign_extend:DI
-;;				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-;;			       (sign_extend:DI
-;;				(match_operand:SI 2 "gpc_reg_operand" "r")))
-;;		      (const_int 32))))]
-;;  ""
-;;  "mulhw %0,%1,%2"
-;;  [(set_attr "type" "imul")])
-
-;;(define_insn "umulsi3_highpart"
-;;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;;	(truncate:SI
-;;	 (lshiftrt:DI (mult:DI (zero_extend:DI
-;;				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-;;			       (zero_extend:DI
-;;				(match_operand:SI 2 "gpc_reg_operand" "r")))
-;;		      (const_int 32))))]
-;;  ""
-;;  "*return \"mr 3,%2\;mr 4,%1\;bl __umulsi3_highpart\;mr %0,3\";"
-;;  [(set_attr "type" "imul")])
+(define_insn "smulsi3_highpart"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (sign_extend:DI
+				(match_operand:SI 1 "gpc_reg_operand" "%r"))
+			       (sign_extend:DI
+				(match_operand:SI 2 "gpc_reg_operand" "r")))
+		      (const_int 32))))]
+  "rs6000_cpu != PROCESSOR_PPE42"
+  "mulhw %0,%1,%2"
+  [(set_attr "type" "imul")])
+
+(define_insn "umulsi3_highpart"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (zero_extend:DI
+				(match_operand:SI 1 "gpc_reg_operand" "%r"))
+			       (zero_extend:DI
+				(match_operand:SI 2 "gpc_reg_operand" "r")))
+		      (const_int 32))))]
+  "rs6000_cpu != PROCESSOR_PPE42"
+  "*return \"mr 3,%2\;mr 4,%1\;bl __umulsi3_highpart\;mr %0,3\";"
+  [(set_attr "type" "imul")])
 
 ;; Shift by a variable amount is too complex to be worth open-coding.  We
 ;; just handle shifts by constants.
@@ -9089,7 +9130,7 @@
    || gpc_reg_operand (operands[1], QImode)"
   "@
    mr %0,%1
-   lbz%U1%X1 %0,%1
+   lbz%U1%X1 %0,%1 #DEBUGME 3 %1
    stb%U0%X0 %1,%0
    li %0,%1
    mf%1 %0