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authorjrv <jrv@138bc75d-0d04-0410-961f-82ee72b054a4>1992-03-03 19:42:18 +0000
committerjrv <jrv@138bc75d-0d04-0410-961f-82ee72b054a4>1992-03-03 19:42:18 +0000
commit5d70629f550969d9507f7ff52211ab7dfe38df8b (patch)
tree5c1c1d841ef9fa455867fd72889d390a7eca900d
parente45ce1bfb3e3d1800fd77d23d9e497477c94e070 (diff)
downloadppe42-gcc-5d70629f550969d9507f7ff52211ab7dfe38df8b.tar.gz
ppe42-gcc-5d70629f550969d9507f7ff52211ab7dfe38df8b.zip
*** empty log message ***
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@381 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/config/i386/i386.c2
-rw-r--r--gcc/config/i386/i386.h14
2 files changed, 10 insertions, 6 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index cd81f699901..6aed00d1d6b 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -49,7 +49,7 @@ static char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
{
/* ax, dx, cx, bx */
- AREG, DREG, CREG, Q_REGS,
+ AREG, DREG, CREG, BREG,
/* si, di, bp, sp */
SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
/* FP registers */
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index c0cd287b3d2..e24cbd149c8 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -309,13 +309,16 @@ extern int target_flags;
in a smaller-numbered class.
For any two classes, it is very desirable that there be another
- class that represents their union. */
-
+ class that represents their union.
+
+ It might seem that class BREG is unnecessary, since no useful 386
+ opcode needs reg %ebx. But some systems pass args to the OS in ebx,
+ and the "b" register constraint is useful in asms for syscalls. */
enum reg_class
{
NO_REGS,
- AREG, DREG, CREG,
+ AREG, DREG, CREG, BREG,
Q_REGS, /* %eax %ebx %ecx %edx */
SIREG, DIREG,
INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
@@ -331,7 +334,7 @@ enum reg_class
#define REG_CLASS_NAMES \
{ "NO_REGS", \
- "AREG", "DREG", "CREG", \
+ "AREG", "DREG", "CREG", "BREG", \
"Q_REGS", \
"SIREG", "DIREG", \
"INDEX_REGS", \
@@ -346,7 +349,7 @@ enum reg_class
#define REG_CLASS_CONTENTS \
{ 0, \
- 0x1, 0x2, 0x4, /* AREG, DREG, CREG */ \
+ 0x1, 0x2, 0x4, 0x8, /* AREG, DREG, CREG, BREG */ \
0xf, /* Q_REGS */ \
0x10, 0x20, /* SIREG, DIREG */ \
0x1007f, /* INDEX_REGS */ \
@@ -409,6 +412,7 @@ extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
(C) == 't' ? FP_TOP_REG : \
(C) == 'u' ? FP_SECOND_REG : \
(C) == 'a' ? AREG : \
+ (C) == 'b' ? BREG : \
(C) == 'c' ? CREG : \
(C) == 'd' ? DREG : \
(C) == 'D' ? DIREG : \
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