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| author | davem <davem@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-12-02 00:38:56 +0000 |
|---|---|---|
| committer | davem <davem@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-12-02 00:38:56 +0000 |
| commit | 4a88b9bad73b255f1cf89441f9537df42cc130fc (patch) | |
| tree | 255562d61a77abe8039f3238b537a23925cda44a | |
| parent | 91599c6e814c8fa80b40da6d0b9b18adf7fbccb1 (diff) | |
| download | ppe42-gcc-4a88b9bad73b255f1cf89441f9537df42cc130fc.tar.gz ppe42-gcc-4a88b9bad73b255f1cf89441f9537df42cc130fc.zip | |
* config/sparc/sparc.md (movsf_const_intreg): Add constraints for
regclass' sake.
(movdf_const_intreg_sp32): Likewise. Prefer the memory load
alternative because setting up 64bit constant is usually costly,
especially when reload is in progress or completed.
(movdf_const_intreg_sp64): Likewise.
(movdf_const_intreg split): Fix building up constants when
HOST_BITS_PER_WIDE_INT is 64 yet long is 32bit.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@30750 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 14 |
2 files changed, 18 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index deb8060e40e..0737719128a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +1999-12-01 Jakub Jelinek <jakub@redhat.com> + + * config/sparc/sparc.md (movsf_const_intreg): Add constraints for + regclass' sake. + (movdf_const_intreg_sp32): Likewise. Prefer the memory load + alternative because setting up 64bit constant is usually costly, + especially when reload is in progress or completed. + (movdf_const_intreg_sp64): Likewise. + (movdf_const_intreg split): Fix building up constants when + HOST_BITS_PER_WIDE_INT is 64 yet long is 32bit. + Wed Dec 1 16:51:22 1999 Jeffrey A Law (law@cygnus.com) * combine.c (if_then_else_cond): Use const_true_rtx instead of diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 95c68685227..1dcbf35499e 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -2765,7 +2765,7 @@ (define_insn "*movsf_const_intreg" [(set (match_operand:SF 0 "register_operand" "=f,r") - (match_operand:SF 1 "const_double_operand" "m,F"))] + (match_operand:SF 1 "const_double_operand" "m#F,F"))] "TARGET_FPU" "* { @@ -2932,8 +2932,8 @@ (set_attr "length" "1")]) (define_insn "*movdf_const_intreg_sp32" - [(set (match_operand:DF 0 "register_operand" "=e,e,r") - (match_operand:DF 1 "const_double_operand" "T,o,F"))] + [(set (match_operand:DF 0 "register_operand" "=e,e,?r") + (match_operand:DF 1 "const_double_operand" "T#F,o#F,F"))] "TARGET_FPU && ! TARGET_ARCH64" "@ ldd\\t%1, %0 @@ -2945,8 +2945,8 @@ ;; Now that we redo life analysis with a clean slate after ;; instruction splitting for sched2 this can work. (define_insn "*movdf_const_intreg_sp64" - [(set (match_operand:DF 0 "register_operand" "=e,r") - (match_operand:DF 1 "const_double_operand" "m,F"))] + [(set (match_operand:DF 0 "register_operand" "=e,?r") + (match_operand:DF 1 "const_double_operand" "m#F,F"))] "TARGET_FPU && TARGET_ARCH64" "@ ldd\\t%1, %0 @@ -2978,8 +2978,8 @@ #if HOST_BITS_PER_WIDE_INT == 64 HOST_WIDE_INT val; - val = ((HOST_WIDE_INT)l[1] | - ((HOST_WIDE_INT)l[0] << 32)); + val = ((HOST_WIDE_INT)(unsigned long)l[1] | + ((HOST_WIDE_INT)(unsigned long)l[0] << 32)); emit_insn (gen_movdi (operands[0], GEN_INT (val))); #else emit_insn (gen_movdi (operands[0], |
