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| author | kazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-02-01 17:01:34 +0000 |
|---|---|---|
| committer | kazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-02-01 17:01:34 +0000 |
| commit | 47b897c486a4465cd74fd864aeaa9b8a710bb82e (patch) | |
| tree | 2d56cdee303713f4fdbccfc9f2e737e30f59d1c2 | |
| parent | b97ba337a3e6ad5275dd8f727bb8f551cb9adc4c (diff) | |
| download | ppe42-gcc-47b897c486a4465cd74fd864aeaa9b8a710bb82e.tar.gz ppe42-gcc-47b897c486a4465cd74fd864aeaa9b8a710bb82e.zip | |
* config/h8300/h8300.md (two peephole2's): New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@77076 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/h8300/h8300.md | 35 |
2 files changed, 39 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 63063ce999a..6c579629098 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2004-02-01 Kazu Hirata <kazu@cs.umass.edu> + + * config/h8300/h8300.md (two peephole2's): New. + 2004-02-01 Eric Botcazou <ebotcazou@libertysurf.fr> * config/sparc/sol2-bi.h: Handle TARGET_CPU_ultrasparc3. diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index b8c0c922737..c0a9575f4cd 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -4969,3 +4969,38 @@ "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0])); operands[6] = gen_int_mode (INTVAL (operands[1]), QImode); operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);") + +;; These triggers right at the end of allocation of locals in the +;; prologue. The only profitable cases are when we have stack +;; adjustment of -4 or -12. That of -8 won't happen because it is +;; always split into two consecutive subtractions of -4. + +(define_peephole2 + [(set (reg:SI SP_REG) + (plus:SI (reg:SI SP_REG) + (const_int -4))) + (set (mem:SI (reg:SI SP_REG)) + (match_operand:SI 0 "register_operand" ""))] + "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE + && REGNO (operands[0]) != SP_REG" + [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) + (match_dup 0))] + "") + +(define_peephole2 + [(set (reg:SI SP_REG) + (plus:SI (reg:SI SP_REG) + (const_int -12))) + (set (mem:SI (reg:SI SP_REG)) + (match_operand:SI 0 "register_operand" ""))] + "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE + && REGNO (operands[0]) != SP_REG" + [(set (reg:SI SP_REG) + (plus:SI (reg:SI SP_REG) + (const_int -4))) + (set (reg:SI SP_REG) + (plus:SI (reg:SI SP_REG) + (const_int -4))) + (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) + (match_dup 0))] + "") |
