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authorrsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4>2007-04-01 11:23:54 +0000
committerrsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4>2007-04-01 11:23:54 +0000
commit34a438224e02552a93eb285271b9cf4179ac0faf (patch)
treef3beda1fc6d7a4561745b16ef9bd5a83fdaf23a0
parentbb7ffa7a86e0b0ac0f6ceff7547eef17bc444795 (diff)
downloadppe42-gcc-34a438224e02552a93eb285271b9cf4179ac0faf.tar.gz
ppe42-gcc-34a438224e02552a93eb285271b9cf4179ac0faf.zip
gcc/
PR target/31388 * config/mips/mips.md (load_const_gp): New insn. * config/mips/mips.c (mips_split_symbol): Avoid using or creating the MIPS16 GP pseudo register if no_new_pseudos. (mips16_gp_pseudo_reg): Use gen_load_const_gp. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@123398 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog8
-rw-r--r--gcc/config/mips/mips.c19
-rw-r--r--gcc/config/mips/mips.md5
3 files changed, 22 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 91ab03c1af7..7d8f39bb7d9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2007-04-01 Richard Sandiford <richard@codesourcery.com>
+
+ PR target/31388
+ * config/mips/mips.md (load_const_gp): New insn.
+ * config/mips/mips.c (mips_split_symbol): Avoid using or creating
+ the MIPS16 GP pseudo register if no_new_pseudos.
+ (mips16_gp_pseudo_reg): Use gen_load_const_gp.
+
2007-03-31 Andrew Pinski <andrew_pinski@playstation.sony.com>
PR target/31364
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 7203a83a7cc..4c0ce09a36d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -1888,10 +1888,15 @@ mips_split_symbol (rtx temp, rtx addr)
{
rtx high;
- if (TARGET_MIPS16)
- high = mips16_gp_pseudo_reg ();
- else
+ if (!TARGET_MIPS16)
high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
+ else if (no_new_pseudos)
+ {
+ emit_insn (gen_load_const_gp (copy_rtx (temp)));
+ high = temp;
+ }
+ else
+ high = mips16_gp_pseudo_reg ();
return gen_rtx_LO_SUM (Pmode, high, addr);
}
@@ -7808,19 +7813,13 @@ mips16_gp_pseudo_reg (void)
{
if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
{
- rtx unspec;
rtx insn, scan;
cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
/* We want to initialize this to a value which gcc will believe
is constant. */
- start_sequence ();
- unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
- emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
- gen_rtx_CONST (Pmode, unspec));
- insn = get_insns ();
- end_sequence ();
+ insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
push_topmost_sequence ();
/* We need to emit the initialization after the FUNCTION_BEG
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 9d07cec4d91..cfe7150d495 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4074,6 +4074,11 @@
[(set_attr "type" "mfc")
(set_attr "mode" "SF")])
+;; Move a constant that satisfies CONST_GP_P into operand 0.
+(define_expand "load_const_gp"
+ [(set (match_operand 0 "register_operand" "=d")
+ (const (unspec [(const_int 0)] UNSPEC_GP)))])
+
;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
;; of _gp from the start of this function. Operand 1 is the incoming
;; function address.
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