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| author | kazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-04-29 18:37:27 +0000 |
|---|---|---|
| committer | kazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-04-29 18:37:27 +0000 |
| commit | 31cd4ca7cf242d5cead02bdc8f9559fbff6496ce (patch) | |
| tree | 30957193528cce3b6e23010e2a7a12deaab6a233 | |
| parent | 9c9bad970601f22c1e83f9333b912bbb2d9f7763 (diff) | |
| download | ppe42-gcc-31cd4ca7cf242d5cead02bdc8f9559fbff6496ce.tar.gz ppe42-gcc-31cd4ca7cf242d5cead02bdc8f9559fbff6496ce.zip | |
* config/mips/mips.md, config/mips/sb1.md,
config/rs6000/rs6000.c: Fix comment typos.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@81296 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 2 | ||||
| -rw-r--r-- | gcc/config/mips/sb1.md | 2 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 2 |
4 files changed, 8 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b660fdbf794..f54823bcc11 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2004-04-29 Kazu Hirata <kazu@cs.umass.edu> + * config/mips/mips.md, config/mips/sb1.md, + config/rs6000/rs6000.c: Fix comment typos. + +2004-04-29 Kazu Hirata <kazu@cs.umass.edu> + * builtins.c, cgraph.c, cgraphunit.c, final.c, fold-const.c: Fix comment typos. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index d5071dd7da3..38c5b0bab74 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -5236,7 +5236,7 @@ dsrl\t%3,%3,1\n\ ;; The HI and LO registers are not truly independent. If we move an mthi ;; instruction before an mflo instruction, it will make the result of the -;; mflo unpredicatable. The same goes for mtlo and mfhi. +;; mflo unpredictable. The same goes for mtlo and mfhi. ;; ;; We cope with this by making the mflo and mfhi patterns use both HI and LO. ;; Operand 1 is the register we want, operand 2 is the other one. diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md index a58992be525..91346107f09 100644 --- a/gcc/config/mips/sb1.md +++ b/gcc/config/mips/sb1.md @@ -204,7 +204,7 @@ ;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX ;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to ;; another LS insn (excluding store data). A simple alu insn issued on an EX -;; unit has a latency of 5 cycles when the results goes to a LS unit (exluding +;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding ;; store data), otherwise a latency of 1 cycle. ;; ??? We can not handle latencies properly for simple alu instructions diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 7195805b18e..c405abd88a5 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1678,7 +1678,7 @@ easy_fp_constant (rtx op, enum machine_mode mode) abort (); } -/* Returns the constant for the splat instrunction, if exists. */ +/* Returns the constant for the splat instruction, if exists. */ static int easy_vector_splat_const (int cst, enum machine_mode mode) |
