diff options
| author | Doug Gilbert <dgilbert@us.ibm.com> | 2015-12-17 14:03:37 -0600 |
|---|---|---|
| committer | Patrick Williams <patrick@stwcx.xyz> | 2016-08-15 11:45:09 -0500 |
| commit | 2f2eb785a0bc373e8de83e077a3aa6f6c948f791 (patch) | |
| tree | c678e6db7324213333e024249b838e2ed24c509b | |
| parent | 60db5f9d146fa1925d19524b822dd68e210b93d5 (diff) | |
| download | ppe42-gcc-2f2eb785a0bc373e8de83e077a3aa6f6c948f791.tar.gz ppe42-gcc-2f2eb785a0bc373e8de83e077a3aa6f6c948f791.zip | |
Turn off 64bit load/stores in epilog/proglog
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 4 |
2 files changed, 6 insertions, 4 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index be5e111279d..ca5f547f093 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -23475,7 +23475,7 @@ rs6000_emit_prologue (void) if ((strategy & SAVE_INLINE_GPRS)) { // ppe42 - use 64 bit stores - No evidence that this gained anything - if(rs6000_cpu == PROCESSOR_PPE42) + if(rs6000_cpu == PROCESSOR_TITAN) // TODO disable for now PROCESSOR_PPE42) { i = 0; if((info->first_gp_reg_save & 0x01) == 1) // odd reg num @@ -23589,7 +23589,7 @@ rs6000_emit_prologue (void) int i; // ppe42 save using 64-bit stores - if(rs6000_cpu == PROCESSOR_PPE42) + if(rs6000_cpu == PROCESSOR_TITAN) // TODO disable for now PROCESSOR_PPE42) { i = 0; if((info->first_gp_reg_save & 0x1) == 1) // odd regnum @@ -25046,7 +25046,7 @@ rs6000_emit_epilogue (int sibcall) else { // ppe42 - use 64 bit loads - if(rs6000_cpu == PROCESSOR_PPE42) + if(rs6000_cpu == PROCESSOR_TITAN) // TODO turn off PROCESSOR_PPE42) { i = 0; if((info->first_gp_reg_save & 0x1) == 1) // odd reg diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 53229f0c911..4255db4310f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -892,6 +892,8 @@ (const_string "load_u") (const_string "*")))])]) +;; FIXME this insn has a length problem - needs to be split +;; one when two instructions are used the set_addr "length" "8" (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m")))] @@ -10279,7 +10281,7 @@ "@ stvd%U0%X0 %1, %0 lvd%U1%X1 %0, %1 - # movedi_internal32 %0, %1 FIXME + # movedi_internal32 %0, %1 REPORT ME! stfd%U0%X0 %1,%0 lfd%U1%X1 %0,%1 fmr %0,%1 |
