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| author | clyon <clyon@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-12-19 16:32:04 +0000 |
|---|---|---|
| committer | clyon <clyon@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-12-19 16:32:04 +0000 |
| commit | 2f2163a4db1e11694539e95b53723d0bc970ea06 (patch) | |
| tree | 226b332068aa9bbe95a6e12777d4c838679930e4 | |
| parent | 6d92059b612326d7f54a2c82e5b4758590c0d153 (diff) | |
| download | ppe42-gcc-2f2163a4db1e11694539e95b53723d0bc970ea06.tar.gz ppe42-gcc-2f2163a4db1e11694539e95b53723d0bc970ea06.zip | |
2013-12-19 Charles Baylis <charles.baylis@linaro.org>
PR target/59142
* config/arm/predicates.md (vfp_hard_register_operand): New predicate.
* config/arm/arm.md (vfp_pop_multiple_with_writeback): Use
vfp_hard_register_operand.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206123 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 2 | ||||
| -rw-r--r-- | gcc/config/arm/predicates.md | 6 |
3 files changed, 15 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 47dfb73660b..7ff9d7c7fc1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,11 @@ -o2013-12-19 Tejas Belagod <tejas.belagod@arm.com> +2013-12-19 Charles Baylis <charles.baylis@linaro.org> + + PR target/59142 + * config/arm/predicates.md (vfp_hard_register_operand): New predicate. + * config/arm/arm.md (vfp_pop_multiple_with_writeback): Use + vfp_hard_register_operand. + +2013-12-19 Tejas Belagod <tejas.belagod@arm.com> * config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins): Define builtin types for poly64_t poly128_t. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index c474ff16d51..6e1b47d69e2 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12253,7 +12253,7 @@ [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) (match_operand:SI 2 "const_int_operand" "I"))) - (set (match_operand:DF 3 "arm_hard_register_operand" "") + (set (match_operand:DF 3 "vfp_hard_register_operand" "") (mem:DF (match_dup 1)))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "* diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 29e1e5c8276..24f05489aaf 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -98,6 +98,12 @@ && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); }) +(define_predicate "vfp_hard_register_operand" + (match_code "reg") +{ + return (IS_VFP_REGNUM (REGNO (op))); +}) + (define_predicate "zero_operand" (and (match_code "const_int,const_double,const_vector") (match_test "op == CONST0_RTX (mode)"))) |
