* config/pa/fptr.c: Fix comment typos.

	* config/pa/pa-64.h: Likewise.
	* config/pa/pa.c: Likewise.
	* config/pa/pa.h: Likewise.
	* config/rs6000/603.md: Likewise.
	* config/rs6000/7xx.md: Likewise.
	* config/rs6000/darwin.h: Likewise.
	* config/rs6000/freebsd.h: Likewise.
	* config/rs6000/rs6000.c: Likewise.
	* config/rs6000/rs6000.md: Likewise.
	* config/rs6000/spe.h: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@68947 138bc75d-0d04-0410-961f-82ee72b054a4

12 files changed, 30 insertions, 16 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index dbe03760f96..f393bfa544c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2003-07-04  Kazu Hirata  <kazu@cs.umass.edu>
+
+	* config/pa/fptr.c: Fix comment typos.
+	* config/pa/pa-64.h: Likewise.
+	* config/pa/pa.c: Likewise.
+	* config/pa/pa.h: Likewise.
+	* config/rs6000/603.md: Likewise.
+	* config/rs6000/7xx.md: Likewise.
+	* config/rs6000/darwin.h: Likewise.
+	* config/rs6000/freebsd.h: Likewise.
+	* config/rs6000/rs6000.c: Likewise.
+	* config/rs6000/rs6000.md: Likewise.
+	* config/rs6000/spe.h: Likewise.
+
 2003-07-04  Ulrich Weigand  <uweigand@de.ibm.com>
 
 	* config/s390/2064.md: Change GNU CC to GCC.
diff --git a/gcc/config/pa/fptr.c b/gcc/config/pa/fptr.c
index 36ed49c3084..680cb20c3a4 100644
--- a/gcc/config/pa/fptr.c
+++ b/gcc/config/pa/fptr.c
@@ -94,7 +94,7 @@ __canonicalize_funcptr_for_compare (fptr)
       /* Find the first "bl" branch in the offset search list.  This is a
 	 call to fixup or a magic branch to fixup at the beginning of the
 	 trampoline template.  The fixup function does the actual runtime
-	 resolution of function decriptors.  We only look for "bl" branches
+	 resolution of function descriptors.  We only look for "bl" branches
 	 with a 17-bit pc-relative displacement.  */
       for (i = 0; i < NOFFSETS; i++)
 	{
diff --git a/gcc/config/pa/pa-64.h b/gcc/config/pa/pa-64.h
index 646f5f147d7..6cb289e3b41 100644
--- a/gcc/config/pa/pa-64.h
+++ b/gcc/config/pa/pa-64.h
@@ -93,6 +93,6 @@ Boston, MA 02111-1307, USA.  */
    next argument, if that argument is smaller than its aligned space as
    controlled by PARM_BOUNDARY.  If this macro is not defined, all such
    arguments are padded down when BYTES_BIG_ENDIAN is true.  We don't
-   want aggregrates padded down.  */
+   want aggregates padded down.  */
 
 #define PAD_VARARGS_DOWN (!AGGREGATE_TYPE_P (type))
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index e7b0b8abbe2..9287583bd7d 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1467,7 +1467,7 @@ force_mode (mode, orig)
    normally.
 
    Note SCRATCH_REG may not be in the proper mode depending on how it
-   will be used.  This routine is resposible for creating a new copy
+   will be used.  This routine is responsible for creating a new copy
    of SCRATCH_REG in the proper mode.  */
 
 int
@@ -7585,7 +7585,7 @@ pa_function_ok_for_sibcall (decl, exp)
     return (decl != NULL_TREE);
 
   /* Sibcalls are not ok because the arg pointer register is not a fixed
-     register.  This prevents the sibcall optimization from occuring.  In
+     register.  This prevents the sibcall optimization from occurring.  In
      addition, there are problems with stub placement using GNU ld.  This
      is because a normal sibcall branch uses a 17-bit relocation while
      a regular call branch uses a 22-bit relocation.  As a result, more
@@ -8641,7 +8641,7 @@ function_arg (cum, mode, type, named)
 	     This is magic.  Normally, using a PARALLEL results in left
 	     justified data on a big-endian target.  However, using a
 	     single double-word register provides the required right
-	     justication for 5 to 8 byte structures.  This has nothing
+	     justification for 5 to 8 byte structures.  This has nothing
 	     to do with the direction of padding specified for the argument.
 	     It has to do with how the data is widened and shifted into
 	     and from the register.
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 9c6a4a4727f..3f61074e632 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -197,7 +197,7 @@ extern int target_flags;
    difference calls.  This is a call variant similar to the long pic
    pc-relative call.  Long pic symbol difference calls are only used with
    the HP SOM linker.  Currently, only the HP assembler supports these
-   calls.  GAS doesn't allow an arbritrary difference of two symbols.  */
+   calls.  GAS doesn't allow an arbitrary difference of two symbols.  */
 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
 
 /* Define to a C expression evaluating to true to use long pic
diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md
index fe37fbedfdd..7ae038e33e0 100644
--- a/gcc/config/rs6000/603.md
+++ b/gcc/config/rs6000/603.md
@@ -33,7 +33,7 @@
 ;; the insn that sets CR bits should be separated from the branch insn
 ;; that evaluates them; separation by more than 9 insns ensures that the CR
 ;; bits will be immediately available for execution.
-;; This could be artificially achieved by exagerating the latency of
+;; This could be artificially achieved by exaggerating the latency of
 ;; compare insns but at the expense of a poorer schedule.
 
 ;; CR insns get executed in the SRU.  Not modelled.
diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md
index eb84f29fbac..de8a7b7552d 100644
--- a/gcc/config/rs6000/7xx.md
+++ b/gcc/config/rs6000/7xx.md
@@ -38,7 +38,7 @@
 ;; the insn that sets CR bits should be separated from the branch insn
 ;; that evaluates them.  There is no advantage have more than 10 cycles
 ;; of separation.
-;; This could be artificially achieved by exagerating the latency of
+;; This could be artificially achieved by exaggerating the latency of
 ;; compare insns but at the expense of a poorer schedule.
 
 ;; Branches go straight to the BPU.  All other insns are handled
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 52340a8e029..b28544ade3b 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -208,7 +208,7 @@ do {									\
 #define PROCESSOR_DEFAULT  PROCESSOR_PPC7400
 
 /* Default target flag settings.  Despite the fact that STMW/LMW
-   serializes, it's still a big codesize win to use them.  Use FSEL by
+   serializes, it's still a big code size win to use them.  Use FSEL by
    default as well.  */
 
 #undef  TARGET_DEFAULT
diff --git a/gcc/config/rs6000/freebsd.h b/gcc/config/rs6000/freebsd.h
index be71d5d3eea..fe6a801bb2c 100644
--- a/gcc/config/rs6000/freebsd.h
+++ b/gcc/config/rs6000/freebsd.h
@@ -40,7 +40,7 @@
 #define	LINK_OS_DEFAULT_SPEC "%(link_os_freebsd)"
 
 /* XXX: This is wrong for many platforms in sysv4.h.
-   We should work on getting that defination fixed.  */
+   We should work on getting that definition fixed.  */
 #undef  LINK_SHLIB_SPEC
 #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}}"
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index df5d775ee16..40748c9383f 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1684,7 +1684,7 @@ output_vec_const_move (operands)
       /* Vector constant 0 is handled as a splitter of V2SI, and in the
 	 pattern of V1DI, V4HI, and V2SF.
 
-	 FIXME: We should probabl return # and add post reload
+	 FIXME: We should probably return # and add post reload
 	 splitters for these, but this way is so easy ;-).
       */
       operands[1] = GEN_INT (cst);
@@ -7762,7 +7762,7 @@ includes_rldic_lshift_p (shiftop, andop)
 
 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
    to perform a left shift.  It must have SHIFTOP or more least
-   signifigant 0's, with the remainder of the word 1's.  */
+   significant 0's, with the remainder of the word 1's.  */
 
 int
 includes_rldicr_lshift_p (shiftop, andop)
@@ -7777,7 +7777,7 @@ includes_rldicr_lshift_p (shiftop, andop)
       shift_mask <<= INTVAL (shiftop);
       c = INTVAL (andop);
 
-      /* Find the least signifigant one bit.  */
+      /* Find the least significant one bit.  */
       lsb = c & -c;
 
       /* It must be covered by the shift mask.
@@ -10663,7 +10663,7 @@ get_TOC_alias_set ()
     return set;
 }   
 
-/* This retuns nonzero if the current function uses the TOC.  This is
+/* This returns nonzero if the current function uses the TOC.  This is
    determined by the presence of (unspec ... UNSPEC_TOC) or
    use (unspec ... UNSPEC_TOC), which are generated by the various
    load_toc_* patterns.  */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index cb50e7e8ab8..1d471efbf85 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -9869,7 +9869,7 @@
   "HAVE_AS_TLS && TARGET_64BIT"
   "addi %0,%1,%2@tprel@l")
 
-;; "b" output contraint here and on tls_tls input to support linker tls
+;; "b" output constraint here and on tls_tls input to support linker tls
 ;; optimization.  The linker may edit the instructions emitted by a
 ;; tls_got_tprel/tls_tls pair to addis,addi.
 (define_insn "tls_got_tprel_32"
diff --git a/gcc/config/rs6000/spe.h b/gcc/config/rs6000/spe.h
index c469fadff96..ca90b8068d8 100644
--- a/gcc/config/rs6000/spe.h
+++ b/gcc/config/rs6000/spe.h
@@ -992,7 +992,7 @@ __ev_set_s16_internal (__ev64_opaque__ a, int16_t b, uint32_t pos)
 #define __ev_lower_fs_tst_eq(a, b)	__builtin_spe_evfststeq (__pred_lower, (a), (b))
 #define __ev_select_fs_tst_eq		__builtin_spe_evsel_fststeq
 
-/* SPEFSCR accesor functions.  */
+/* SPEFSCR accessor functions.  */
 
 #define __SPEFSCR_SOVH		0x80000000
 #define __SPEFSCR_OVH		0x40000000