diff options
| author | cgd <cgd@138bc75d-0d04-0410-961f-82ee72b054a4> | 2003-10-05 23:57:56 +0000 |
|---|---|---|
| committer | cgd <cgd@138bc75d-0d04-0410-961f-82ee72b054a4> | 2003-10-05 23:57:56 +0000 |
| commit | 267ca031efaba73f0a9f0e5e578ebc669f60c971 (patch) | |
| tree | 7db093aa313a8804948b943da5a421d06b806579 | |
| parent | 9381e7a70d5b8b1b6962eeedf097b37105f114a2 (diff) | |
| download | ppe42-gcc-267ca031efaba73f0a9f0e5e578ebc669f60c971.tar.gz ppe42-gcc-267ca031efaba73f0a9f0e5e578ebc669f60c971.zip | |
2003-10-05 Chris Demetriou <cgd@broadcom.com>
* config/mips/mips.md (*divsf3): Move description of
SB-1 F2 erratum from here to...
(divsf3): Here. Disable if TARGET_FIX_SB1 is set and
flag_unsafe_math_optimizations is not.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@72123 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 20 |
2 files changed, 18 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8bc30bb59d8..5b3dd9699e0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2003-10-05 Chris Demetriou <cgd@broadcom.com> + + * config/mips/mips.md (*divsf3): Move description of + SB-1 F2 erratum from here to... + (divsf3): Here. Disable if TARGET_FIX_SB1 is set and + flag_unsafe_math_optimizations is not. + 2003-10-05 Aldy Hernandez <aldyh@redhat.com> * config/rs6000/linuxspe.h: Define TARGET_SPE_ABI, TARGET_SPE, diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index b645973cc2a..932025fdd93 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -2407,11 +2407,19 @@ (const_int 4)))]) +;; This pattern works around the early SB-1 rev2 core "F2" erratum: +;; +;; In certain cases, div.s and div.ps may have a rounding error +;; and/or wrong inexact flag. +;; +;; Therefore, we only allow div.s if not working around SB-1 rev2 +;; errata, or if working around those errata and a slight loss of +;; precision is OK (i.e., flag_unsafe_math_optimizations is set). (define_expand "divsf3" [(set (match_operand:SF 0 "register_operand" "") (div:SF (match_operand:SF 1 "reg_or_const_float_1_operand" "") (match_operand:SF 2 "register_operand" "")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)" { if (const_float_1_operand (operands[1], SFmode)) if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations)) @@ -2421,14 +2429,8 @@ ;; This pattern works around the early SB-1 rev2 core "F1" erratum (see ;; "divdf3" comment for details). ;; -;; This pattern works around the early SB-1 rev2 core "F2" erratum: -;; -;; In certain cases, div.s and div.ps may have a rounding error -;; and/or wrong inexact flag. -;; -;; Therefore, we only allow div.s if not working around SB-1 rev2 -;; errata, or if working around those errata and a slight loss of -;; precision is OK (i.e., flag_unsafe_math_optimizations is set). +;; This pattern works around the early SB-1 rev2 core "F2" erratum (see +;; "divsf3" comment for details). (define_insn "*divsf3" [(set (match_operand:SF 0 "register_operand" "=f") (div:SF (match_operand:SF 1 "register_operand" "f") |
