diff options
| author | wschmidt <wschmidt@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-09-09 23:22:24 +0000 |
|---|---|---|
| committer | wschmidt <wschmidt@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-09-09 23:22:24 +0000 |
| commit | 24c020e32216264a65f5c5fc62dc9a61ba9616c1 (patch) | |
| tree | daed5120cf079ba811d6a2762a8c6eae660ec3d4 | |
| parent | ad879ddca3904ed8633e6e46a064c6d49e2a7568 (diff) | |
| download | ppe42-gcc-24c020e32216264a65f5c5fc62dc9a61ba9616c1.tar.gz ppe42-gcc-24c020e32216264a65f5c5fc62dc9a61ba9616c1.zip | |
2014-09-09 Bill Schmidt <wschmidt@us.ibm.com>
Backported from mainline
2014-09-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/vsx.md (*vsx_extract_<mode>_load): Always match
selection of 0th memory doubleword, regardless of endianness.
2014-09-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backported from mainline
2014-09-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-extract-1.c: Test 0th doubleword
regardless of endianness.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@215096 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c | 8 |
4 files changed, 18 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fe351fc527d..1c7d152c0d3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2014-09-09 Bill Schmidt <wschmidt@us.ibm.com> + + Backported from mainline + 2014-09-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/vsx.md (*vsx_extract_<mode>_load): Always match + selection of 0th memory doubleword, regardless of endianness. + 2014-09-09 James Greenhalgh <james.greenhalgh@arm.com> Backport from mainline diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 2cf5e7a9490..1138145e55c 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1647,7 +1647,7 @@ [(set (match_operand:<VS_scalar> 0 "register_operand" "=d,wv,wr") (vec_select:<VS_scalar> (match_operand:VSX_D 1 "memory_operand" "m,Z,m") - (parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))] + (parallel [(const_int 0)])))] "VECTOR_MEM_VSX_P (<MODE>mode)" "@ lfd%U1%X1 %0,%1 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b847f620180..0b4226b289b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2014-09-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backported from mainline + 2014-09-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/vsx-extract-1.c: Test 0th doubleword + regardless of endianness. + 2014-09-09 Richard Biener <rguenther@suse.de> Backport from mainline diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c index e1f0ca8e887..c4e76e6ac0e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c @@ -7,10 +7,4 @@ #include <altivec.h> -#if __LITTLE_ENDIAN__ -#define OFFSET 1 -#else -#define OFFSET 0 -#endif - -double get_value (vector double *p) { return vec_extract (*p, OFFSET); } +double get_value (vector double *p) { return vec_extract (*p, 0); } |
